CN112382233A - Internal compensation circuit and control method thereof - Google Patents

Internal compensation circuit and control method thereof Download PDF

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Publication number
CN112382233A
CN112382233A CN202011304592.8A CN202011304592A CN112382233A CN 112382233 A CN112382233 A CN 112382233A CN 202011304592 A CN202011304592 A CN 202011304592A CN 112382233 A CN112382233 A CN 112382233A
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transistor
gate
compensation circuit
capacitor
controlling
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CN202011304592.8A
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Chinese (zh)
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璐炬旦
贾浩
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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Priority to CN202011304592.8A priority Critical patent/CN112382233A/en
Publication of CN112382233A publication Critical patent/CN112382233A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Abstract

The invention relates to the technical field of compensation circuits of displays, in particular to an internal compensation circuit and a control method thereof, wherein the internal compensation circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a capacitor C1, a capacitor C2 and a light-emitting diode OLED, the transistor T3, the transistor T4 and the transistor T6 are all polysilicon thin film transistors and are all arranged between a substrate and a dielectric layer, and the transistor T1, the transistor T2 and the transistor T5 are all oxide thin film transistors and are all arranged above the dielectric layer; the compensation circuit structure designed in this way can reduce the occupied area of pixels, increase the resolution, improve PPI and improve the display effect.

Description

Internal compensation circuit and control method thereof
Technical Field
The invention relates to the technical field of display compensation circuits, in particular to an internal compensation circuit and a control method thereof.
Background
In order to achieve the highest resolution in a limited space, the occupied area of each Pixel is required to be smaller; for an OLED (Organic Light Emitting Diode) panel, an in-plane 2T1C (two TFTs and a capacitor) Pixel circuit is affected by Vth (threshold voltage) drift to cause uneven panel luminance, so that the compensation circuit can improve the panel display effect, and in order to achieve a better compensation effect, the compensation circuit has a plurality of TFTs (Thin Film transistors), but the area occupied by the Pixel is increased due to too many TFTs, and further the number of pixels contained in the panel is reduced, that is, the resolution is low, and the requirement of high resolution cannot be met.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: an internal compensation circuit and a control method thereof are provided.
In order to solve the above technical problems, a first technical solution adopted by the present invention is:
an internal compensation circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a capacitor C1, a capacitor C2 and a light-emitting diode (OLED), wherein the transistor T3, the transistor T4 and the transistor T6 are all polycrystalline silicon thin film transistors and are all arranged between a substrate and a dielectric layer, and the transistor T1, the transistor T2 and the transistor T5 are all oxide thin film transistors and are all arranged above the dielectric layer;
the gate of the transistor T1 is connected to a first scan signal, the source of the transistor T1 is connected to a data signal, the drain of the transistor T1 is electrically connected to one end of the capacitor C1 and the source of the transistor T2, the gate of the transistor T2 is connected to the second scan signal, the drain of the transistor T2 is electrically connected to the source of the transistor T3 and one end of the capacitor C2, the gate of the transistor T3 is connected to the third scan signal, the drain of the transistor T3 is electrically connected to the gate of the transistor T4 and the source of the transistor T5 respectively, the drain electrode of the transistor T4 is connected with a power signal, the source electrode of the transistor T4 is respectively and electrically connected with the source electrode of the transistor T6 and the other end of the capacitor C2, the gate of the transistor T5 is connected to the second scan signal, the drain of the transistor T6 is electrically connected to the anode of the light emitting diode OLED, and the gate of the transistor T6 is connected to the second scan signal.
The second technical scheme adopted by the invention is as follows:
a method of controlling an internal compensation circuit, comprising the steps of:
step S1, in the first time period, controlling the gate of the transistor T1 to input a low level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S2, in the second time period, controlling the gate of the transistor T1 and the gate of the transistor T3 to input a high level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S3 of controlling the gate of the transistor T2, the gate of the transistor T5, and the gate of the transistor T6 to all input a low level in a third period;
step S4, in a fourth time period, controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level, and controlling the gate of the transistor T3 to input a high level; the first time period, the second time period, the third time period and the fourth time period are sequentially continuous time periods.
The invention has the beneficial effects that:
the transistor T3, the transistor T4 and the transistor T6 which are designed by the scheme are all polysilicon thin film transistors and are all arranged between the substrate and the dielectric layer, and the transistor T1, the transistor T2 and the transistor T5 are all oxide thin film transistors and are all arranged above the dielectric layer, so that the designed internal compensation circuit can compensate Vth drift, and the problem of poor performance caused by Vth drift is solved; the compensation circuit structure designed in this way can reduce the occupied area of pixels, increase the resolution, improve PPI and improve the display effect.
Drawings
FIG. 1 is a schematic diagram of an internal compensation circuit according to the present invention;
FIG. 2 is a schematic diagram of a hierarchical structure of an internal compensation circuit according to the present invention;
FIG. 3 is a schematic diagram of a hierarchical structure of an internal compensation circuit according to the present invention;
FIG. 4 is a waveform diagram of an internal compensation circuit according to the present invention;
FIG. 5 is a schematic diagram illustrating the structure of the stage T1 of the internal compensation circuit according to the present invention;
FIG. 6 is a schematic diagram illustrating the structure of the stage T2 of the internal compensation circuit according to the present invention;
FIG. 7 is a schematic diagram illustrating the structure of the stage T3 of the internal compensation circuit according to the present invention;
FIG. 8 is a schematic diagram illustrating the structure of the stage T4 of the internal compensation circuit according to the present invention;
FIG. 9 is a flow chart of the steps of a method of controlling an internal compensation circuit according to the present invention;
description of reference numerals:
1. an upper layer; 2. and a lower layer.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, a technical solution provided by the present invention:
an internal compensation circuit comprises a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a capacitor C1, a capacitor C2 and a light-emitting diode (OLED), wherein the transistor T3, the transistor T4 and the transistor T6 are all polycrystalline silicon thin film transistors and are all arranged between a substrate and a dielectric layer, and the transistor T1, the transistor T2 and the transistor T5 are all oxide thin film transistors and are all arranged above the dielectric layer;
the gate of the transistor T1 is connected to a first scan signal, the source of the transistor T1 is connected to a data signal, the drain of the transistor T1 is electrically connected to one end of the capacitor C1 and the source of the transistor T2, the gate of the transistor T2 is connected to the second scan signal, the drain of the transistor T2 is electrically connected to the source of the transistor T3 and one end of the capacitor C2, the gate of the transistor T3 is connected to the third scan signal, the drain of the transistor T3 is electrically connected to the gate of the transistor T4 and the source of the transistor T5 respectively, the drain electrode of the transistor T4 is connected with a power signal, the source electrode of the transistor T4 is respectively and electrically connected with the source electrode of the transistor T6 and the other end of the capacitor C2, the gate of the transistor T5 is connected to the second scan signal, the drain of the transistor T6 is electrically connected to the anode of the light emitting diode OLED, and the gate of the transistor T6 is connected to the second scan signal.
From the above description, the beneficial effects of the present invention are:
the transistor T3, the transistor T4 and the transistor T6 which are designed by the scheme are all polysilicon thin film transistors and are all arranged between the substrate and the dielectric layer, and the transistor T1, the transistor T2 and the transistor T5 are all oxide thin film transistors and are all arranged above the dielectric layer, so that the designed internal compensation circuit can compensate Vth drift, and the problem of poor performance caused by Vth drift is solved; the compensation circuit structure designed in this way can reduce the occupied area of pixels, increase the resolution, improve PPI and improve the display effect.
Further, the capacitor C1 is disposed above the dielectric layer.
Further, the capacitor C2 is disposed between the substrate and the dielectric layer.
Furthermore, the transistor also comprises a first connecting line and a second connecting line which penetrate through the dielectric layer, the drain electrode of the transistor T2 is connected with the drain electrode of the transistor T3 through the first connecting line, and the source electrode of the transistor T5 is connected with the drain electrode of the transistor T3 through the second connecting line.
Referring to fig. 9, another technical solution provided by the present invention:
a method of controlling an internal compensation circuit, comprising the steps of:
step S1, in the first time period, controlling the gate of the transistor T1 to input a low level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S2, in the second time period, controlling the gate of the transistor T1 and the gate of the transistor T3 to input a high level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S3 of controlling the gate of the transistor T2, the gate of the transistor T5, and the gate of the transistor T6 to all input a low level in a third period;
step S4, in a fourth time period, controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level, and controlling the gate of the transistor T3 to input a high level; the first time period, the second time period, the third time period and the fourth time period are sequentially continuous time periods.
From the above description, the beneficial effects of the present invention are:
in the first period, the gate of the control transistor T1 inputs a low level, the gates of the control transistor T2, the transistor T5 and the transistor T6 input a high level, in the second period, the gate of the control transistor T1 and the gate of the transistor T3 input a high level, the gates of the control transistor T2, the transistor T5 and the transistor T6 input a high level, in the third period, the gates of the control transistor T2, the transistor T5 and the transistor T6 input a low level, in the fourth period, the gates of the control transistor T2, the transistor T5 and the transistor T6 input a high level, and the gate of the control transistor T3 inputs a high level, so that Vth shift can be compensated, and a problem of failure caused by Vth shift is improved; the compensation circuit structure designed in this way can reduce the occupied area of pixels, increase the resolution, improve PPI and improve the display effect.
Referring to fig. 1 to 8, a first embodiment of the present invention is:
referring to fig. 1, an internal compensation circuit includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a capacitor C1, a capacitor C2, and a light emitting diode OLED;
referring to fig. 2 and 3, the transistor T3, the transistor T4, and the transistor T6 are all polysilicon thin film transistors and are all disposed between the substrate and the dielectric layer (i.e., the lower layer 2), and the transistor T1, the transistor T2, and the transistor T5 are all oxide thin film transistors and are all disposed above the dielectric layer (i.e., the upper layer 1);
referring to fig. 1, the gate of the transistor T1 is connected to a first scan signal, the source of the transistor T1 is connected to a data signal, the drain of the transistor T1 is electrically connected to one end of the capacitor C1 and the source of the transistor T2, the gate of the transistor T2 is connected to the second scan signal, the drain of the transistor T2 is electrically connected to the source of the transistor T3 and one end of the capacitor C2, the gate of the transistor T3 is connected to the third scan signal, the drain of the transistor T3 is electrically connected to the gate of the transistor T4 and the source of the transistor T5 respectively, the drain electrode of the transistor T4 is connected with a power signal, the source electrode of the transistor T4 is respectively and electrically connected with the source electrode of the transistor T6 and the other end of the capacitor C2, the gate of the transistor T5 is connected to the second scan signal, the drain of the transistor T6 is electrically connected to the anode of the light emitting diode OLED, and the gate of the transistor T6 is connected to the second scan signal.
Referring to fig. 1, the capacitor C1 is disposed above the dielectric layer.
Referring to fig. 1, the capacitor C2 is disposed between the substrate and the dielectric layer.
Referring to fig. 1, the semiconductor device further includes a first connection line and a second connection line penetrating through the dielectric layer, the drain of the transistor T2 is connected to the drain of the transistor T3 through the first connection line, and the source of the transistor T5 is connected to the drain of the transistor T3 through the second connection line.
The working principle of the internal compensation circuit is as follows:
referring to fig. 4 and 5, at the stage T1, the first Scan signal Scan1 is written with a low level, the transistor T1 is turned on, the B point is written with a data signal (Vdata) voltage, the second Scan signal Scan2 is written with a high level, the transistor T2 and the transistor T5 are turned off, and V is turned offB＝Vdata；
Referring to fig. 4 and 6, at stage T2, the first Scan signal Scan1 is turned off, the transistor T1 is turned off, the second Scan signal Scan2 is still turned on, the transistor T2 and the transistor T5 are still turned off, the transistor T6 is still turned on, the third Scan signal Scan3 is turned on, the transistor T3 is turned off, and the S-point is discharged to the cross voltage across the two ends of the light emitting diode OLED, i.e., VS＝VOLED；
Referring to fig. 4 and 7, at stage T3, the second Scan signal Scan2 is written low, the transistor T2 and the transistor T5 are turned on, Vdata (data signal) voltage is written at point a, Vref (reference voltage) is written at point G, and point S is reached (VrefVth), i.e. when V is presentA＝Vdata，VG＝Vref，VS＝Vref –Vth；
Referring to FIGS. 4 and 8, at stage T4, the second Scan signal Scan2 is asserted highThe transistor T2 and the transistor T5 are turned off, the transistor T6 is turned on, the third Scan signal Scan3 writes a high level, and the transistor T3 is turned on; vdata (data signal) voltage, i.e. V, is written at point GG＝Vdata，VS＝VrefVth, then VGS＝VG-VS＝Vdata-(VrefVth) substituted into N-type TFT saturation region current formula IOLED＝1/2μnCOXW/L(VGS-VTH)2To obtain IOLED＝1/2μnCOXW/L(Vdata-Vref)2(Note that μ n is the field Effect mobility, COXAn insulating layer capacitor per unit area; W/L is TFT channel width to length).
The formula shows that the light emitting current of the light emitting diode OLED in the circuit is only related to Vdata and Vref signals, is irrelevant to Vth, has relatively fixed other parameters, and cannot be influenced by other unstable factors (such as VDD, VSS, VOLED and the like), and meanwhile, the layered structure enables the occupied area of pixels to be smaller, the number of the pixels contained in the panel to be larger, and the resolution to be higher.
Referring to fig. 4 to fig. 9, a second embodiment of the present invention is:
referring to fig. 9, a method for controlling an internal compensation circuit includes the following steps:
step S1, in the first time period, controlling the gate of the transistor T1 to input a low level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S2, in the second time period, controlling the gate of the transistor T1 and the gate of the transistor T3 to input a high level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S3 of controlling the gate of the transistor T2, the gate of the transistor T5, and the gate of the transistor T6 to all input a low level in a third period;
step S4, in a fourth time period, controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level, and controlling the gate of the transistor T3 to input a high level; the first time period, the second time period, the third time period and the fourth time period are sequentially continuous time periods.
The specific embodiment of the scheme is as follows:
referring to fig. 4 and 5, in a first period (i.e., at the stage of T1), the first Scan signal Scan1 writes a low level, the transistor T1 is turned on, the B-point writes a Vdata (data signal) voltage, the first Scan signal Scan2 writes a high level, the transistor T2 and the transistor T5 are turned off, and V is turned onB＝Vdata；
Referring to fig. 4 and 6, in a second time period (i.e., at the stage T2), the first Scan signal Scan1 is turned off, the transistor T1 is turned off, the second Scan signal Scan2 is still turned on, the transistor T2 and the transistor T5 are still turned off, the transistor T6 is still turned on, the third Scan signal Scan3 is turned off, the transistor T3 is turned off, and the S-point is discharged to the cross voltage across the light emitting diode OLED, i.e., VS＝VOLED；
Referring to fig. 4 and 7, in a third period (i.e., a period T3), the second Scan signal Scan2 is written with a low level, the transistor T2 and the transistor T5 are turned on, a point a is written with a Vdata (data signal) voltage, a point G is written with a Vref (reference voltage), and a point S reaches (V) pointrefVth), i.e. when V is presentA＝Vdata，VG＝Vref，VS＝Vref–Vth；
Referring to fig. 4 and 8, during a fourth time period (i.e., a period T4), the second Scan signal Scan2 is written high, the transistor T2 and the transistor T5 are turned off, the transistor T6 is turned on, the third Scan signal Scan3 is written high, and the transistor T3 is turned on; vdata (data signal) voltage, i.e. V, is written at point GG＝Vdata，VS＝VrefVth, then VGS＝VG-VS＝Vdata-(VrefVth) substituted into N-type TFT saturation region current formula IOLED＝1/2μnCOXW/L(VGS-Vth)2To obtain IOLED＝1/2μnCOXW/L(Vdata-Vref)2(Note that μ n is the field Effect mobility, COXAn insulating layer capacitor per unit area; W/L is TFT channel width to length).
The formula shows that the light emitting current of the light emitting diode OLED in the circuit is only related to Vdata and Vref signals, is irrelevant to Vth, has relatively fixed other parameters, and cannot be influenced by other unstable factors (such as VDD, VSS, VOLED and the like), and meanwhile, the layered structure enables the occupied area of pixels to be smaller, the number of the pixels contained in the panel to be larger, and the resolution to be higher.
In summary, according to the internal compensation circuit and the control method thereof provided by the present invention, the transistor T3, the transistor T4, and the transistor T6 of the present invention are all polysilicon thin film transistors and are all disposed between the substrate and the dielectric layer, and the transistor T1, the transistor T2, and the transistor T5 are all oxide thin film transistors and are all disposed above the dielectric layer, so that the designed internal compensation circuit can compensate Vth drift, and the problem of defects caused by Vth drift is improved; the compensation circuit structure designed in this way can reduce the occupied area of pixels, increase the resolution, improve PPI and improve the display effect.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.

Claims (5)

1. An internal compensation circuit is characterized by comprising a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a capacitor C1, a capacitor C2 and a light emitting diode OLED, wherein the transistor T3, the transistor T4 and the transistor T6 are all polycrystalline silicon thin film transistors and are all arranged between a substrate and a dielectric layer, and the transistor T1, the transistor T2 and the transistor T5 are all oxide thin film transistors and are all arranged above the dielectric layer;
the gate of the transistor T1 is connected to a first scan signal, the source of the transistor T1 is connected to a data signal, the drain of the transistor T1 is electrically connected to one end of the capacitor C1 and the source of the transistor T2, the gate of the transistor T2 is connected to the second scan signal, the drain of the transistor T2 is electrically connected to the source of the transistor T3 and one end of the capacitor C2, the gate of the transistor T3 is connected to the third scan signal, the drain of the transistor T3 is electrically connected to the gate of the transistor T4 and the source of the transistor T5 respectively, the drain electrode of the transistor T4 is connected with a power signal, the source electrode of the transistor T4 is respectively and electrically connected with the source electrode of the transistor T6 and the other end of the capacitor C2, the gate of the transistor T5 is connected to the second scan signal, the drain of the transistor T6 is electrically connected to the anode of the light emitting diode OLED, and the gate of the transistor T6 is connected to the second scan signal.
2. The internal compensation circuit of claim 1, wherein the capacitor C1 is disposed over a dielectric layer.
3. The internal compensation circuit of claim 1, wherein the capacitor C2 is disposed between the substrate and the dielectric layer.
4. The internal compensation circuit of claim 1, further comprising a first connection line and a second connection line penetrating the dielectric layer, wherein the drain of the transistor T2 is connected to the drain of the transistor T3 through the first connection line, and the source of the transistor T5 is connected to the drain of the transistor T3 through the second connection line.
5. A method for controlling an internal compensation circuit according to claim 1, comprising the steps of:
step S1, in the first time period, controlling the gate of the transistor T1 to input a low level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S2, in the second time period, controlling the gate of the transistor T1 and the gate of the transistor T3 to input a high level, and controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level;
step S3 of controlling the gate of the transistor T2, the gate of the transistor T5, and the gate of the transistor T6 to all input a low level in a third period;
step S4, in a fourth time period, controlling the gate of the transistor T2, the gate of the transistor T5 and the gate of the transistor T6 to input a high level, and controlling the gate of the transistor T3 to input a high level; the first time period, the second time period, the third time period and the fourth time period are sequentially continuous time periods.
CN202011304592.8A 2020-11-19 2020-11-19 Internal compensation circuit and control method thereof Pending CN112382233A (en)

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CN202011304592.8A CN112382233A (en) 2020-11-19 2020-11-19 Internal compensation circuit and control method thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114743500A (en) * 2022-04-25 2022-07-12 福建华佳彩有限公司 High-resolution 5T2C LTPO internal compensation circuit and control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114743500A (en) * 2022-04-25 2022-07-12 福建华佳彩有限公司 High-resolution 5T2C LTPO internal compensation circuit and control method thereof

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