CN111369943A - Layered pixel compensation circuit - Google Patents
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- CN111369943A CN111369943A CN202010236251.5A CN202010236251A CN111369943A CN 111369943 A CN111369943 A CN 111369943A CN 202010236251 A CN202010236251 A CN 202010236251A CN 111369943 A CN111369943 A CN 111369943A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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Abstract
A layered pixel compensation circuit comprises a lower thin film transistor area, an upper thin film transistor area and an insulating layer, wherein the lower thin film transistor area and the upper thin film transistor area are arranged on a substrate, the insulating layer is arranged between the upper thin film transistor area and the lower thin film transistor area, an electrode of the upper thin film transistor area is connected with an electrode of the lower thin film transistor area through a connecting wire penetrating through the insulating layer, an organic light emitting diode is further patterned in the upper thin film transistor area, and a thin film transistor in the upper thin film transistor area and a thin film transistor in the lower thin film transistor area are connected to form the compensation circuit of the organic light emitting diode; be different from prior art, above-mentioned technical scheme is through the lower floor film transistor area in district and the upper strata film transistor area in district that the design base plate is last different, finally through the area that a plurality of film transistors of reducing pixel compensation circuit in vertical direction occupy for the area occupied of single pixel reduces, finally improves the resolution of screen.
Description
Technical Field
The invention relates to a design of a pixel compensation circuit, in particular to a novel pixel compensation circuit design with an upper layer and a lower layer.
Background
Nowadays, with the continuous improvement of the technology level, the demand for the display screen is also increasing, i.e. the demand for high resolution is increasing, for example, the resolution of VR, AR, MR and other displays is as high as 2000PPI or more. For the OLED panel, the 2T1CPixel circuit in the plane is affected by Vth drift to cause uneven panel luminance, the compensation circuit is required to improve the panel display effect, and in order to achieve better compensation effect, the compensation circuit has a plurality of TFTs, which may have 4T, 5T, and 6T …, so that the occupied area of pixels is increased due to excessive TFTs, and further the number of pixels accommodated by the panel is reduced, that is, the resolution becomes low, and the requirement of high resolution cannot be met.
Nowadays, the level of display quality demand on the panel is higher and higher, and it is important to improve the resolution of the display. It is known that for an OLED panel, due to the influence of the manufacturing process and aging, such as Vth shift, the display effect of the panel is greatly affected, in order to eliminate the influence, a Pixel circuit of the OLED panel usually adds a TFT as a compensation circuit, and generally, the better the compensation effect is, the more the TFTs are, which results in an overlarge Pixel occupied area and reduced resolution; if the Driving TFT in the Pixel compensation circuit is replaced with an LTPS TFT with higher electron mobility, that is, an LTPO (Low temperature polycrystalline Oxide) structure, the size of the TFT can be reduced, the resolution can be increased, and the circuit is layered, the original 6T1C Pixel circuit can be divided into an upper layer and a lower layer, namely, an upper layer 3 Oxide TFTs and a lower layer 3 LTPS TFTs, so as to further reduce the Pixel area and increase the resolution, and meanwhile, the practical LTPO can have the advantages of high LTPS electron mobility and small IGZO leakage current.
Therefore, it is an important issue to improve the resolution of the OLED panel, and to manufacture an OLED panel with a good compensation effect and an ultra-high resolution.
Disclosure of Invention
Therefore, it is desirable to provide a new layered pixel compensation circuit, which achieves the technical effects of reducing the TFT layout area and improving the panel resolution.
In order to achieve the above object, the inventor provides a layered pixel compensation circuit, which includes a lower thin film transistor region, an upper thin film transistor region, and an insulating layer disposed between the upper thin film transistor region and the lower thin film transistor region, wherein the lower thin film transistor region and the upper thin film transistor region are disposed on a substrate;
the lower thin film transistor region comprises thin film transistors T2, T3, T5 and capacitors C1 and C2; the upper thin film transistor region comprises T1, T4 and T6; the source electrode of the T1 is connected with VDD, and the drain electrode is connected with the source electrode of the T4; the drain electrode of the T4 is also connected with the anode of the organic light-emitting diode; the cathode of the organic light-emitting diode is also connected with the drain electrode of the T6;
the grid electrode of the T1 is also connected with the grid electrode of the T3 through a first upper and lower layer connection line, the drain electrode of the T3 is connected with the drain electrode of the T2, the source electrode of the T3 is connected with a DATA line, and the grid electrode of the T4 is also connected with the drain electrode of the T3 through a second upper and lower layer connection line; the drain of the T3 is further connected with one end of a capacitor C1, the other end of the C1 is further connected with one end of a C2, the other end of the C2 is further connected with the drain of the T4 through a third upper and lower layer connecting line, the other end of the C1 is further connected with the source of the T5, and the drain of the T5 is connected with the source of the T6 through a fourth upper and lower layer connecting line.
Furthermore, the lower thin film transistor is a polysilicon thin film transistor, the lower thin film transistor region comprises a polysilicon active layer connected with the metal electrode, the polysilicon active layer is coated with a barrier layer, the barrier layer is provided with a first gate layer, the polysilicon active layer, the metal electrode and the first gate layer are patterned into a plurality of polysilicon thin film transistors,
the upper thin film transistor area comprises an oxide active layer, and the upper thin film transistor area is patterned with oxide thin film transistors and AMOLED pixels;
the pixel compensation circuit further comprises a connecting wire, and the polycrystalline silicon thin film transistor is connected with the oxide thin film transistor through the connecting wire to form the pixel compensation circuit.
Specifically, the barrier layer and the first gate layer are further coated with a dielectric layer, and the dielectric layer is arranged below the insulating layer.
Optionally, the dielectric layer is hydrogenated amorphous silicon nitride.
Specifically, the barrier layer is a silicon oxide or aluminum oxide film.
Specifically, the insulating layer is further provided with a flat layer, and the flat layer is an organic insulating material film.
Specifically, the insulating layer is a silicon oxide film.
Specifically, the pixel is an LTPO pixel.
Optionally, the substrate is a glass substrate.
Be different from prior art, above-mentioned technical scheme is through the lower floor film transistor area in district and the upper strata film transistor area in district that the design base plate is last different, finally through the area that a plurality of film transistors of reducing pixel compensation circuit in vertical direction occupy for the area occupied of single pixel reduces, finally improves the resolution of screen.
Drawings
FIG. 1 is a prior art pixel compensation circuit according to an embodiment;
FIG. 2 is a schematic diagram of a hierarchical pixel compensation circuit according to an embodiment;
FIG. 3 is a diagram illustrating a compensation circuit for pixels in different processes according to one embodiment;
FIG. 4 is a diagram illustrating the operation state of the Reset phase according to an embodiment;
FIG. 5 is a schematic diagram illustrating an operating state of the compensation phase according to an embodiment;
FIG. 6 is a schematic diagram illustrating the operation of the hold phase according to an embodiment;
fig. 7 is a schematic diagram of the working state of the light-emitting stage according to the embodiment.
Description of the reference numerals
001. A first dielectric layer;
002. a second dielectric layer;
003. a third dielectric layer;
004. a fourth dielectric layer;
1. an electrode metal;
2、a-Si；
3. a gate metal;
4、IGZO；
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1, a conventional 6T2C compensation circuit is shown in fig. 1, and although the compensation effect is good, pixels occupy a large area and have low resolution; in order to improve PPI, a compensation circuit architecture is invented as shown in fig. 2, the upper layer includes three oxidetfts and an organic light emitting diode, the lower layer includes three LTPS TFTs and two capacitors, the architecture is a new LTPO compensation circuit, LTPO has the advantages of IGZO and LTPS, and the panel has a better display effect. The circuit architecture is divided into an upper layer and a lower layer by using a dotted line to reduce the Pixel occupied area; the TFT layer diagram is shown in fig. 3, and for convenience of description, only one Oxide TFT and one LTPS TFT are shown, which are an upper Oxide TFT and a lower LTPS TFT, respectively.
As shown in fig. 3, in the pixel compensation circuit, a lower thin film transistor region and an upper thin film transistor region are disposed on a substrate buffer, and an insulating layer (medium 001) is further disposed between the upper thin film transistor region and the lower thin film transistor region, and the insulating layer may be a thin film made of silicon oxide. The electrodes of the upper thin film transistor region and the lower thin film transistor region are connected by a connection line 100 passing through the insulating layer, the upper thin film transistor region further patterns an organic light emitting diode (not shown), and the thin film transistor of the upper thin film transistor region and the thin film transistor of the lower thin film transistor region are connected to form a compensation circuit of the organic light emitting diode. The thin film transistors on the upper and lower layers are designed in the pixel compensation circuit, the thin film transistors on the lower layer can be selected in different patterning modes according to the actual connection relation of the pixel compensation circuit, the manufactured thin film transistors on the lower layer are fully covered by the insulating layer, the situations of electric leakage and the like are prevented, the thin film transistors on the upper layer and the related organic light emitting diodes, namely AMOLED pixels, are arranged above the insulating layer, and the thin film transistors on the upper layer and the lower layer are designed, so that the area required by tiling arrangement of the pixel compensation circuit relative to a single layer can be reduced, and the area required by the pixel compensation circuit is increased.
In other aspects, the LTPS process requires laser irradiation of amorphous silicon (a-si), and the a-si absorbs laser energy and then transforms into a polysilicon structure (poly-si), which is completed at 600 ℃. The metal-oxide semiconductor has unstable characteristics and is easily damaged by high temperature, light, water and oxygen to cause the failure of the TFT. Therefore, laser light and high temperature environment in LTPS process may damage metal-oxide semiconductor, so in some further embodiments, referring to fig. 1, the lower thin film transistor is a polysilicon thin film transistor, the lower thin film transistor region includes a polysilicon active layer (p-si), the polysilicon active layer is connected to a metal electrode, the polysilicon active layer is coated with a barrier layer (medium 002) for gate insulation, the barrier layer is provided with a first gate layer, the polysilicon active layer, the metal electrode and the first gate layer are patterned into a plurality of polysilicon thin film transistors, in alternative embodiments, the barrier layer is used to isolate the gate metal and the metal electrode, and the material may be silicon oxide or aluminum oxide thin film.
The upper thin film transistor region comprises an oxide active layer, and the medium of the active layer can be an oxide semiconductor, such as IGZO. In this embodiment, a dielectric layer is further disposed on the first gate layer, the dielectric layer is disposed below the insulating layer, and the dielectric layer is used to isolate the upper and lower thin film transistors, and the material of the dielectric layer may be hydrogenated amorphous silicon nitride, such as a-SiNx: H. The dielectric layer covers the barrier layer and the first gate layer. Patterning oxide thin film transistors and AMOLED pixels above the insulating layer; the thin film transistor above the insulating layer is an Oxide transistor adopting Oxide process, and the thin film transistor further comprises a connecting wire, and the polycrystalline silicon thin film transistor is connected with the Oxide thin film transistor through the connecting wire to form a pixel compensation circuit.
By the scheme, the LTPS thin film transistor is arranged on the lower layer, so that the LTPS manufacturing process and the Oxide manufacturing process can be compatible, the advantages of high resolution, high reaction speed, high brightness, high aperture opening ratio and the like of the LTPS manufacturing process can be compatible in the AMOLED pixel compensation circuit, the electron mobility can be improved, and the area can be reduced.
In some other further embodiments shown in fig. 3, the insulating layer is further provided with a planarization layer (dielectric 003), which is disposed on the insulating layer to provide a planar upper surface for the upper tft layer, and the planarization layer is an organic insulating material film.
The following provides some examples of manufacturing Pixel compensation circuits based on the main concept of layered Pixel circuits, and the 6T2C compensation circuit is shown in fig. 1, although the compensation effect is good, the Pixel occupies a large area and has low resolution; in order to improve PPI, a compensation circuit architecture is invented as shown in fig. 2, the upper layer includes three Oxide TFTs and an organic light emitting diode, the lower layer includes three LTPS TFTs and two capacitors, the architecture is a new LTPO compensation circuit, LTPO has the advantages of IGZO and LTPS, and the panel has a better display effect. The circuit architecture is divided into an upper layer and a lower layer by using a dotted line to reduce the Pixel occupied area; the TFT layer diagram is shown in fig. 3, and for convenience of description, only one Oxide TFT and one LTPS TFT are shown, which are an upper Oxide TFT and a lower LTPS TFT, respectively.
The peripheral wiring and the working principle of the pixel compensation circuit are similar to those of the prior art, and the following are introduced:
as shown in FIG. 4, during the Reset phase, Scan2 is written low, T2 is turned on, and the DATA signal is written VREFVoltage, VA＝VREF；VCVSS; high voltage is written into Scan3 and Scan1, T5 and T1 are turned on, the light emitting diode is turned on briefly, and point B is Reset, VB＝VOLED+VSS。
As shown in fig. 5, during the compensation phase, Scan1 writes high voltage, Scan3 writes low voltage, T1 turns on,t5 is turned off and VDD write raises the voltage at point B to VREF-VTHAt time T4 is closed, at which time VB＝VREF-VTHI.e. to a VTH；VAAnd VCRemain unchanged, i.e. VA＝VREF,VC＝VSS。
As shown in FIG. 6, during the Data write phase, Scan1 writes low, T1 turns off, T3 turns on, VA＝VREF+VDATA,VCHeld at VSS voltage, i.e. VCThe voltage at point B remains constant due to the capacitance between BC, i.e. V, VSSB＝VREF-VTH。
As shown in FIG. 7, in the lighting phase, Scan1 and Scan4 write high voltage, T1 and T5 turn on, T2 and T3 turn off, LED turns on, VB＝VOLED+ VSS, V due to the effect of capacitance between BCC＝VSS+VOLED+VSS-(VREF-VTH) Due to the capacitive effect between the AC, VA＝VDATA+VOLED+VSS+VTH，Then VGS＝VA-VB＝VDATA+VTHSubstituting into the current formula I in the saturation regionOLED＝1/2μnCOXW/L(VGS-VTH)2To obtain IOLED＝1/2μnCOXW/L(VDATA)2(Note. mu.)nIs field effect mobility, COXAn insulating layer capacitor per unit area; W/L is TFT channel width to length).
The formula can be used for obtaining that the OLED luminous current of the circuit is only equal to VDATARelated to VTHThe design method has the advantages that the design purpose is achieved through the design, the compensation effect can be achieved by using a smaller Pixel area, and the resolution of the panel can be finally improved.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (9)
1. A layered pixel compensation circuit is characterized by comprising a lower thin film transistor area, an upper thin film transistor area and an insulating layer, wherein the lower thin film transistor area and the upper thin film transistor area are arranged on a substrate;
the lower thin film transistor region comprises thin film transistors T2, T3, T5 and capacitors C1 and C2; the upper thin film transistor region comprises T1, T4 and T6; the source electrode of the T1 is connected with VDD, and the drain electrode is connected with the source electrode of the T4; the drain electrode of the T4 is also connected with the anode of the organic light-emitting diode; the cathode of the organic light-emitting diode is also connected with the drain electrode of the T6;
the grid electrode of the T1 is also connected with the grid electrode of the T3 through a first upper and lower layer connection line, the drain electrode of the T3 is connected with the drain electrode of the T2, the source electrode of the T3 is connected with a DATA line, and the grid electrode of the T4 is also connected with the drain electrode of the T3 through a second upper and lower layer connection line; the drain of the T3 is further connected with one end of a capacitor C1, the other end of the C1 is further connected with one end of a C2, the other end of the C2 is further connected with the drain of the T4 through a third upper and lower layer connecting line, the other end of the C1 is further connected with the source of the T5, and the drain of the T5 is connected with the source of the T6 through a fourth upper and lower layer connecting line.
2. The layered pixel compensation circuit of claim 1, wherein the lower TFT is a polysilicon TFT, the lower TFT comprises a polysilicon active layer connected to a metal electrode, the polysilicon active layer is covered with a barrier layer, the barrier layer is provided with a first gate layer, the polysilicon active layer, the metal electrode and the first gate layer are patterned into a plurality of polysilicon TFTs,
the upper thin film transistor area comprises an oxide active layer, and the upper thin film transistor area is patterned with oxide thin film transistors and AMOLED pixels;
the pixel compensation circuit further comprises a connecting wire, and the polycrystalline silicon thin film transistor is connected with the oxide thin film transistor through the connecting wire to form the pixel compensation circuit.
3. The layered pixel compensation circuit of claim 2, wherein the barrier layer and the first gate layer are further covered with a dielectric layer disposed under the insulating layer.
4. The layered pixel compensation circuit of claim 3, wherein the dielectric layer is hydrogenated amorphous silicon nitride.
5. The layered pixel compensation circuit of claim 2, wherein the blocking layer is a silicon oxide or aluminum oxide film.
6. The layered pixel compensation circuit of claim 1, wherein the insulating layer is further provided with a planarization layer, and the planarization layer is a thin film of organic insulating material.
7. The layered pixel compensation circuit of claim 1, wherein the insulating layer is a silicon oxide film.
8. The hierarchical pixel compensation circuit of claim 1, wherein the pixel is an LTPO pixel.
9. The layered pixel compensation circuit of claim 1, wherein the substrate is a glass substrate.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112071268A (en) * | 2020-08-12 | 2020-12-11 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114743500A (en) * | 2022-04-25 | 2022-07-12 | 福建华佳彩有限公司 | High-resolution 5T2C LTPO internal compensation circuit and control method thereof |
| CN114927098A (en) * | 2022-05-07 | 2022-08-19 | 重庆邮电大学 | Pixel driving circuit and pixel driving method |
| US11950456B2 (en) | 2020-10-27 | 2024-04-02 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Array substrate and display device |
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| US11950456B2 (en) | 2020-10-27 | 2024-04-02 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Array substrate and display device |
| CN114743500A (en) * | 2022-04-25 | 2022-07-12 | 福建华佳彩有限公司 | High-resolution 5T2C LTPO internal compensation circuit and control method thereof |
| CN114927098A (en) * | 2022-05-07 | 2022-08-19 | 重庆邮电大学 | Pixel driving circuit and pixel driving method |
| CN114927098B (en) * | 2022-05-07 | 2024-04-19 | 重庆邮电大学 | Pixel driving circuit and pixel driving method |
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