CN210864684U - Can debug expansibility development board - Google Patents
Can debug expansibility development board Download PDFInfo
- Publication number
- CN210864684U CN210864684U CN201922483676.1U CN201922483676U CN210864684U CN 210864684 U CN210864684 U CN 210864684U CN 201922483676 U CN201922483676 U CN 201922483676U CN 210864684 U CN210864684 U CN 210864684U
- Authority
- CN
- China
- Prior art keywords
- pin
- chip
- connector
- jumper cap
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The utility model relates to an electronic circuit field, concretely relates to can debug expansibility development board, include: the device comprises an interface circuit, a first signal output circuit, a signal conversion circuit, a second signal output circuit and a jumper cap; the interface circuit is connected with the first signal output circuit and the signal conversion circuit, and the signal conversion circuit is connected with the second signal output circuit; the J113 connector is an interface for signal input and output; the first signal output circuit includes: a U6 chip and J1 connector; the signal conversion circuit comprises a U12 chip; the second signal output circuit includes: u8 chip, USBB-A seat and U15 chip. By the method, a user can perform secondary development or more than secondary development of expansibility on the development board developed by the method according to requirements, and various interfaces are fully utilized to expand the functions of the development board to the maximum extent.
Description
Technical Field
The utility model discloses the electronic circuit field particularly, relates to an expansibility development board can debug.
Background
At present, consumer electronic products all use development boards, such as image navigation equipment, monitoring equipment, camera equipment and the like, all need to use circuit boards, but the traditional development boards only support a single chip microcomputer or an ARM processor of the same type, and onboard resources are fixed and unchanged. Such experimental development panels present significant disadvantages; that is, only a designated processor can be used, the development board cannot be upgraded, the development board resources are fixed, the expansibility is greatly limited, and secondary development is difficult to perform; moreover, because the processor and resources are fixed, the application range is small, the method can only be used for simple experimental development, the practicability is poor, the method is only limited to control over hardware on the board, the emphasis is placed on the hardware, and the application in software directions such as digital signal processing, upper computer communication, image processing, file systems and the like is lacked.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, an object of the present invention is to provide an extensibility-adjustable development board, which allows users to perform extensibility development on a development board developed by the present application and software communication debugging directly on the development board according to requirements, without additionally purchasing debugging equipment.
The utility model aims at realizing through the following technical scheme:
the utility model provides a pair of can debug expansibility development board, include: the device comprises an interface circuit, a first signal output circuit, a signal conversion circuit, a second signal output circuit and a jumper cap; the interface circuit is connected with the first signal output circuit and the signal conversion circuit, and the signal conversion circuit is connected with the second signal output circuit; the interface circuit comprises a J113 connector, and the J113 connector is an interface for signal input and output; the first signal output circuit includes: a U6 chip for processing signals output by the J113 connector, and a J1 connector for outputting signals processed by the U6 chip; the signal conversion circuit includes: a U12 chip for converting signals output by the J113 connector; the second signal output circuit includes: the chip comprises a U8 chip for outputting signals converted by the U12 chip, a USBB-A seat for receiving signals output by the U8 chip and a U15 chip for debugging software of a development board; the jumper cap is used for communicating or gating the circuit.
Further, pin 29 of the J113 connector is connected to pin 62 of the U6 chip through jumper cap JP 12-1; the pin 35 of the J113 connector is connected with the pin 63 of the U6 chip through a jumper cap JP 13-1; the pin 36 of the J113 connector is connected with the pin 64 of the U6 chip through a jumper cap JP 12-1; pin 23 of the J113 connector is connected to pin 67 of the U6 chip through jumper cap JP 28; pin 22 of the J113 connector is connected to pin 68 of the U6 chip through jumper cap JP 18; pin 14 of the J113 connector is connected to pin 69 of the U6 chip through jumper cap JP 5-1; pin 13 of the J113 connector is connected with pin 70 of the U6 chip through jumper cap JP 6-1; pin 16 of the J113 connector is connected with pin 71 of the U6 chip through jumper cap JP 7-1; pin 17 of the J113 connector is connected to pin 72 of the U6 chip through jumper cap JP 8-1; pin 18 of the J113 connector is connected to pin 73 of the U6 chip through jumper cap JP 19-1; pin 19 of the J113 connector is connected with pin 74 of the U6 chip through jumper cap JP 9-1; pin 20 of the J113 connector is connected to pin 75 of the U6 chip through jumper cap JP 10-1; pin 21 of the J113 connector is connected with pin 76 of the U6 chip through jumper cap JP 11-1; pin 31 of the J113 connector is connected to pin 50 of the U6 chip through jumper cap JP 16; pin 12 of the J113 connector is connected to pin 51 of the U6 chip through jumper cap JP 15; pin 10 of the J113 connector is connected to pin 52 of the U6 chip by jumper cap JP 17.
Further, pin 12 of the J113 connector is connected to pin 17 of the U12 chip through jumper cap JP27-1 and pin 43 through jumper cap JP 27-3; pin 10 of the J113 connector is connected with pin 18 of the U12 chip through jumper cap JP 26-1; the pin 35 of the J113 connector is connected with a resistor R58 of the U12 circuit through a jumper cap JP13-3, and a resistor R58 is connected with a pin 19 of the U12 chip; the pin 29 of the J113 connector is connected with a resistor R60 of the U12 circuit through a jumper cap JP12-3, and a resistor R60 is connected with the pin 20 of the U12 chip; pin 36 of the J113 connector is connected to pin 21 of the U12 chip through jumper cap JP 14; pin 14 of the J113 connector is connected to pin 26 of the U12 chip through jumper cap JP 5-3; pin 13 of the J113 connector is connected with pin 27 of the U12 chip through jumper cap JP 6-3; pin 16 of the J113 connector is connected to pin 28 of the U12 chip through jumper cap JP 7-3; pin 17 of the J113 connector is connected to pin 29 of the U12 chip through jumper cap JP 8-3; pin 18 of the J113 connector is connected to pin 30 of the U12 chip through jumper cap JP 19-3; pin 19 of the J113 connector is connected with pin 31 of the U12 chip through jumper cap JP 9-3; pin 20 of the J113 connector is connected to pin 32 of the U12 chip through jumper cap JP 10-3; pin 21 of the J113 connector is connected to pin 33 of the U12 chip by jumper cap JP 11-3.
Further, pin 17 of the U12 chip is connected to pin 51 of the U6 chip through jumper cap JP27-1 and jumper cap JP 15; pins 18 of the U12 chip are connected to pins 52 of the U6 chip by jumper cap JP26-1 and jumper cap JP 17.
Further, pin 4 of the U12 chip is connected to pin 27 of the U8 chip; pin 5 of the U12 chip is connected to pin 28 of the U8 chip.
Further, the interface circuit further includes a sixth power supply circuit connected to the pin 39 and the pin 41 of the J113 connector through JP 20-1.
Further, the first signal output circuit further comprises a seventh power supply circuit, a U10 chip and a U11 chip; the seventh power supply circuit is connected to pin 31 of the J113 connector through jumper cap JP16 and to pin 50 of the U6 chip through jumper cap JP 16; pin 1 of the J1 connector and pin 5 of the U11 chip connect pin 37 of the U6 chip; pin 3 of the J1 connector and pin 4 of the U11 chip connect pin 36 of the U6 chip; pin 4 of the J1 connector and pin 2 of the U11 chip connect pin 34 of the U6 chip; pin 6 of the J1 connector and pin 1 of the U11 chip are connected to pin 33 of the U6 chip; pin 7 of the J1 connector and pin 5 of the U10 chip are connected to pin 31 of the U6 chip; pin 9 of the J1 connector and pin 4 of the U10 chip are connected to pin 30 of the U6 chip; pin 10 of the J1 connector and pin 2 of the U10 chip connect pin 28 of the U6 chip; pin 12 of the J1 connector and pin 1 of the U10 chip connect to pin 27 of the U6 chip.
Furthermore, the signal conversion circuit also comprises a first power supply circuit, a second power supply circuit, a third power supply circuit, a fourth power supply circuit and a fifth power supply circuit, wherein each power supply circuit is used for supplying power to the signal or data conversion circuit; the first power supply circuit is connected with the pin 1, the pin 11, the pin 36 and the pin 54 of the U12 chip; the third power supply circuit, the fourth power supply circuit and the fifth power supply circuit are connected with the pin 2 and the pin 44 of the U12 chip; the second power supply circuit is connected to pin 15, pin 38, and pin 50 of the U12 chip.
Further, the second signal output circuit further includes an eighth power supply circuit, pin 5 of the chip U2 of which is connected to pin 16 of the U8 chip.
Further, pin 15 of the U15 chip is connected to pin 3 of the U8 chip, and pin 16 of the U15 chip is connected to pin 2 of the U8 chip; pin 1 of the U15 chip is connected to pin 9 of the J113 connector through jumper cap JP22, and pin 5 of the U15 chip is connected to pin 7 of the J113 connector through jumper cap JP 23.
The utility model has the advantages that: the interface circuit is connected with the first signal output circuit and transmits signals, the signals are processed by the U6 chip and output by the J1 connector, and development of an HDMI camera product is achieved; the interface circuit is connected with the signal conversion circuit and transmits signals, the U12 chip of the signal conversion circuit converts the received signals, the signal conversion circuit transmits the converted signals to the connected second signal output circuit, and the signals are output to the USBB-A seat through the U8 chip, so that the development of USBCAMERTA products is realized. Through the connection design of the circuit, a user can perform secondary development or more than secondary development of expansibility on the development board developed by the application according to the requirement, namely, the secondary design of some application functions is newly added on the interface of the development board according to the requirement, and various interfaces are fully utilized to furthest expand the functions of the development board; in addition, through the U15 chip, the user can directly carry out software communication debugging on the development board without additionally purchasing debugging equipment.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:
FIG. 1 is a schematic circuit diagram of the scalable extensibility development board of the present invention;
FIG. 2 is a circuit diagram of an interface circuit of the development board with debug extensibility of the present invention;
fig. 2-1 is a circuit diagram of the J113 connector of the debuggable extensibility development board of the present invention;
fig. 2-2 is a circuit diagram of a sixth power supply circuit of the debuggable extended development board of the present invention;
FIGS. 2-3 are schematic diagrams of the debugging extensible development board jumper cap of the present invention;
fig. 3 is a circuit diagram of the first signal output circuit of the development board with adjustable extensibility according to the present invention;
fig. 3-1 is a circuit diagram of a U6 chip of a first signal output circuit of the debuggable extended development board of the present invention;
fig. 3-2 is a circuit diagram of the J1 connector of the first signal output circuit of the debuggable extended development board of the present invention;
3-3 are circuit diagrams of seventh power supply circuits of the debuggable extended development board of the present invention;
fig. 3-4 are circuit diagrams of the chip U10 and the chip U11 of the first signal output circuit of the development board with adjustable extensibility according to the present invention;
FIG. 4 is a circuit diagram of the debug extensibility development board signal conversion circuit of the present invention;
fig. 4-1 is a circuit diagram of the chip U12 circuit of the signal conversion circuit of the debug extensibility development board of the present invention;
fig. 4-2 is a circuit diagram of a first power supply circuit of the signal conversion circuit of the debuggable extended development board of the present invention;
fig. 4-3 are circuit diagrams of second power supply circuits of the signal conversion circuit of the debuggable extended development board of the present invention;
fig. 4-4 are circuit diagrams of a third power supply circuit of the signal conversion circuit of the debuggable extended development board of the present invention;
fig. 4-5 are circuit diagrams of a fourth power supply circuit of the signal conversion circuit of the debuggable extended development board of the present invention;
fig. 4 to 6 are circuit diagrams of a fifth power supply circuit of the signal conversion circuit of the debuggable extensible development board of the present invention;
FIGS. 4-7 are schematic diagrams of jumper cap connections for the development board with debug extensibility of the present invention;
fig. 5 is a circuit diagram of a second output circuit of the debuggable extensibility development board of the present invention;
FIG. 5-1 is a circuit diagram of the chip U8 circuit of the second output circuit of the debug extensibility development board of the present invention;
fig. 5-2 is a circuit diagram of the chip 15 circuit of the second output circuit of the debuggable extensibility development board of the present invention;
fig. 5-3 are circuit diagrams of an eighth power supply circuit of the second output circuit of the debuggable extended development board of the present invention.
Wherein the reference numerals are: 101-interface circuit module, 102-first signal output module, 103-signal conversion circuit module, 104-second output circuit module, 2-interface circuit, 21-J133 connector, 22-sixth power supply circuit, 3-first signal output circuit, 31-U6 chip, 32-J1 connector, 33-seventh power supply circuit, 341-U10 chip, 342-U11 chip, 4-signal conversion circuit, 41-U12 chip, 42-first power supply circuit, 43-second power supply circuit, 44-third power supply circuit, 45-fourth power supply circuit, 46-fifth power supply circuit, 5-second signal output circuit, 51-U8 chip, 52-U15 chip, 53-eighth power supply circuit.
Detailed Description
In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
As shown in fig. 1-5-3, a tunable expandability development plate of an embodiment of the present invention includes: the device comprises an interface circuit 2, a first signal output circuit 3, a signal conversion circuit 4, a second signal output circuit 5 and a jumper cap; the interface circuit 2 is connected with a first signal output circuit 3 and a signal conversion circuit 4, and the signal conversion circuit 4 is connected with a second signal output circuit 5; the interface circuit 2 comprises a J113 connector 21, and the J113 connector 21 is an interface for signal input and output; the first signal output circuit 3 includes: a U6 chip 31 for processing signals output by the J113 connector 21, and a J1 connector 32 for outputting signals processed by the U6 chip 31; the signal conversion circuit 4 includes: a U12 chip 41 for converting the signal output by the J113 connector 21; the second signal output circuit 5 includes: a U8 chip 51 for outputting the signal converted by the U12 chip 41, a USBB-A socket for receiving the signal output by the U8 chip 51 and a U15 chip 52 for software debugging the development board; the jumper cap is used for communicating or gating a circuit.
In the embodiment, in operation, the interface circuit 2 receives a DVP image signal, and outputs the received DVP image signal to the signal conversion circuit 4 and the first output circuit through the jumper caps, respectively; the U12 chip 41 of the signal conversion circuit 4 converts the received DVP image signal into a USB signal, which is output to the USB socket USB-a through the U8 chip 51; the U6 chip 31 of the first output circuit converts the received DVP image signal into an HDMI signal and transmits the HDMI signal to the J1 connector 32 for output; through the design connection of the circuit and the conversion and output of the signal, a user can perform secondary development or more than secondary development on the development board according to the requirement, namely, the secondary or more than secondary design of some application functions is newly added on the expansion interface of the development board.
In an embodiment, pin 29 of the J113 connector 21 is connected to pin 62 of the U6 chip 31 through jumper cap JP 12-1; pin 35 of J113 connector 21 is connected to pin 63 of U6 chip 31 by jumper cap JP 13-1; pin 36 of J113 connector 21 is connected to pin 64 of U6 chip 31 through jumper cap JP 12-1; pin 23 of J113 connector 21 is connected to pin 67 of U6 chip 31 through jumper cap JP 28; pin 22 of J113 connector 21 is connected to pin 68 of U6 chip 31 by jumper cap JP 18; pin 14 of J113 connector 21 is connected to pin 69 of U6 chip 31 through jumper cap JP 5-1; pin 13 of the J113 connector 21 is connected to pin 70 of the U6 chip 31 through jumper cap JP 6-1; pin 16 of the J113 connector 21 is connected to pin 71 of the U6 chip 31 through jumper cap JP 7-1; pin 17 of J113 connector 21 is connected to pin 72 of U6 chip 31 through jumper cap JP 8-1; pin 18 of J113 connector 21 is connected to pin 73 of U6 chip 31 through jumper cap JP 19-1; pin 19 of the J113 connector 21 is connected to pin 74 of the U6 chip 31 through jumper cap JP 9-1; pin 20 of J113 connector 21 is connected to pin 75 of U6 chip 31 through jumper cap JP 10-1; pin 21 of J113 connector 21 is connected to pin 76 of U6 chip 31 by jumper cap JP 11-1; pin 31 of J113 connector 21 is connected to pin 50 of U6 chip 31 by jumper cap JP 16; pin 12 of J113 connector 21 is connected to pin 51 of U6 chip 31 through jumper cap JP 15; pin 10 of J113 connector 21 is connected to pin 52 of U6 chip 31 by jumper cap JP 17.
In an embodiment, the U6 chip 31 is model CV8788, and the J113 connector 21 gates the first output circuit through a jumper cap and transmits the DVP signal to the U6 chip 31; the U6 chip 31 converts the DVP signal into an HDMI signal, and the HDMI signal is transmitted to the J1 connector 32, being output by the J1 connector 32.
In the embodiment, the pin 12 of the J113 connector 21 is connected with the pin 17 of the U12 chip 41 through a jumper cap JP27-1 and the pin 43 through a jumper cap JP 27-3; pin 10 of J113 connector 21 is connected to pin 18 of U12 chip 41 through jumper cap JP 26-1; the pin 35 of the J113 connector 21 is connected with a resistor R58 of the U12 circuit through a jumper cap JP13-3, and a resistor R58 is connected with a pin 19 of the U12 chip 41; the pin 29 of the J113 connector 21 is connected with a resistor R60 of the U12 circuit through a jumper cap JP12-3, and a resistor R60 is connected with the pin 20 of the U12 chip 41; pin 36 of J113 connector 21 is connected to pin 21 of U12 chip 41 by jumper cap JP 14; pin 14 of J113 connector 21 is connected to pin 26 of U12 chip 41 through jumper cap JP 5-3; pin 13 of J113 connector 21 is connected to pin 27 of U12 chip 41 by jumper cap JP 6-3; pin 16 of J113 connector 21 is connected to pin 28 of U12 chip 41 by jumper cap JP 7-3; pin 17 of J113 connector 21 is connected to pin 29 of U12 chip 41 through jumper cap JP 8-3; pin 18 of J113 connector 21 is connected to pin 30 of U12 chip 41 by jumper cap JP 19-3; pin 19 of J113 connector 21 is connected to pin 31 of U12 chip 41 by jumper cap JP 9-3; pin 20 of J113 connector 21 is connected to pin 32 of U12 chip 41 through jumper cap JP 10-3; pin 21 of J113 connector 21 is connected to pin 33 of U12 chip 41 by jumper cap JP 11-3.
In the embodiment, the signal of the U12 chip 41 is SN9C291B, the J113 connector 21 gates the U12 chip 41 through a jumper cap, and transmits the received DVP signal to the U12 chip 41; the U12 chip 41 converts the received DVP signal into a USB signal.
In the embodiment, the pin 17 of the U12 chip 41 is connected to the pin 51 of the U6 chip 31 through the jumper cap JP27-1 and the jumper cap JP 15; pins 18 of the U12 chip 41 are connected to pins 52 of the U6 chip 31 through jumper cap JP26-1 and jumper cap JP 17.
In an embodiment, pin 4 of the U12 chip 41 is connected to pin 27 of the U8 chip 51; pin 5 of the U12 chip 41 is connected to pin 28 of the U8 chip 51.
In an embodiment, the U8 chip 51 is a GL850G model chip supporting a two-way USB device; in this embodiment, one path is designed as a USB CMAERA signal output circuit, and the other path is designed as a USB signal to RS232 or RS485 signal communication circuit.
In the embodiment, the interface circuit 2 further includes a sixth power supply circuit 22, and the sixth power supply circuit 22 is connected to the pin 39 and the pin 41 of the J113 connector 21 through JP 20-1.
In one embodiment, the first signal output circuit 3 further includes a seventh power circuit 33, a U10 chip 341, and a U11 chip 342; the seventh power supply circuit 33 is connected to the pin 31 of the J113 connector 21 through the jumper cap JP16 and to the pin 50 of the U6 chip 31 through the jumper cap JP 16;
In an embodiment, the signal conversion circuit 4 further includes a first power circuit 42, a second power circuit 43, a third power circuit 44, a fourth power circuit 45, and a fifth power circuit 46, each of which is configured to supply power to the signal conversion circuit 4; the first power supply circuit 42 is connected with the pin 1, the pin 11, the pin 36 and the pin 54 of the U12 chip 41; the third power supply circuit 44, the fourth power supply circuit 45 and the fifth power supply circuit 46 are connected to the pin 2 and the pin 44 of the U12 chip 41; second power supply circuit 43 is connected to pin 15, pin 38, and pin 50 of U12 chip 41.
In an embodiment, the second signal output circuit 5 further includes an eighth power supply circuit 53, and the pin 5 of the chip U2 of the eighth power supply circuit 53 is connected to the pin 16 of the U8 chip 51.
In the embodiment, pin 15 of the U15 chip 52 is connected to pin 3 of the U8 chip 51, and pin 16 of the U15 chip 52 is connected to pin 2 of the U8 chip 51; pin 1 of the U15 chip is connected to pin 9 of the J113 connector through jumper cap JP22, and pin 5 of the U15 chip is connected to pin 7 of the J113 connector through jumper cap JP 23.
In the embodiment, the model of the U15 chip 52 is FT232RL, which is used to convert USB signals into RS232 or RS485 signals, and a user can directly perform software communication debugging on the development board through the U15 chip 52.
As shown in fig. 1, the interface circuit module 101 is connected to the first signal output circuit module 102 and the signal conversion circuit module 103, and the signal conversion circuit module 103 is connected to the second signal output circuit module 104; the interface circuit module 101 is used for signal input and output; the first signal output circuit module 102 is configured to process and output a signal output by the interface circuit module 101; the signal conversion circuit module 103 is configured to convert a signal output by the interface circuit module 103, and the second output circuit module 104 is configured to process and output the signal converted by the signal conversion circuit module 103.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A scalable extensibility development board, comprising: the device comprises an interface circuit, a first signal output circuit, a signal conversion circuit, a second signal output circuit and a jumper cap; the interface circuit is connected with the first signal output circuit and the signal conversion circuit, and the signal conversion circuit is connected with the second signal output circuit;
the interface circuit comprises a J113 connector, and the J113 connector is an interface for signal input and output;
the first signal output circuit includes: a U6 chip for processing the signals output by the J113 connector, and a J1 connector for outputting the signals processed by the U6 chip;
the signal conversion circuit includes: a U12 chip for converting the signal output by the J113 connector;
the second signal output circuit includes: the chip comprises a U8 chip for outputting signals converted by the U12 chip, a USBB-A seat for receiving signals output by the U8 chip and a U15 chip for debugging software of a development board;
the jumper cap is used for communicating or gating a circuit.
2. The scalable extensibility development board of claim 1, wherein: the pin 29 of the J113 connector is connected with the pin 62 of the U6 chip through a jumper cap JP 12-1;
the pin 35 of the J113 connector is connected with the pin 63 of the U6 chip through a jumper cap JP 13-1;
the pin 36 of the J113 connector is connected with the pin 64 of the U6 chip through a jumper cap JP 12-1;
pin 23 of the J113 connector is connected to pin 67 of the U6 chip through jumper cap JP 28;
the pin 22 of the J113 connector is connected with the pin 68 of the U6 chip through a jumper cap JP 18;
pin 14 of the J113 connector is connected to pin 69 of the U6 chip through jumper cap JP 5-1;
pin 13 of the J113 connector is connected with pin 70 of the U6 chip through jumper cap JP 6-1;
the pin 16 of the J113 connector is connected with the pin 71 of the U6 chip through a jumper cap JP 7-1;
pin 17 of the J113 connector is connected with pin 72 of the U6 chip through jumper cap JP 8-1;
pin 18 of the J113 connector is connected to pin 73 of the U6 chip through jumper cap JP 19-1;
the pin 19 of the J113 connector is connected with the pin 74 of the U6 chip through a jumper cap JP 9-1;
pin 20 of the J113 connector is connected to pin 75 of the U6 chip through jumper cap JP 10-1;
the pin 21 of the J113 connector is connected with the pin 76 of the U6 chip through a jumper cap JP 11-1;
pin 31 of the J113 connector is connected to pin 50 of the U6 chip through jumper cap JP 16;
pin 12 of the J113 connector is connected to pin 51 of the U6 chip through jumper cap JP 15;
pin 10 of the J113 connector is connected to pin 52 of the U6 chip by jumper cap JP 17.
3. The scalable extensibility development board of claim 1, wherein: the pin 12 of the J113 connector is connected with the pin 17 of the U12 chip through a jumper cap JP27-1 and the pin 43 through a jumper cap JP 27-3;
pin 10 of the J113 connector is connected with pin 18 of the U12 chip through jumper cap JP 26-1;
the pin 35 of the J113 connector is connected with the resistor R58 of the U12 circuit through a jumper cap JP13-3, and the resistor R58 is connected with the pin 19 of the U12 chip;
the pin 29 of the J113 connector is connected with a resistor R60 of the U12 circuit through a jumper cap JP12-3, and the resistor R60 is connected with the pin 20 of the U12 chip;
the pin 36 of the J113 connector is connected with the pin 21 of the U12 chip through a jumper cap JP 14;
pin 14 of the J113 connector is connected with pin 26 of the U12 chip through jumper cap JP 5-3;
pin 13 of the J113 connector is connected with pin 27 of the U12 chip through jumper cap JP 6-3;
pin 16 of the J113 connector is connected to pin 28 of the U12 chip through jumper cap JP 7-3;
pin 17 of the J113 connector is connected to pin 29 of the U12 chip through jumper cap JP 8-3;
pin 18 of the J113 connector is connected with pin 30 of the U12 chip through jumper cap JP 19-3;
pin 19 of the J113 connector is connected with pin 31 of the U12 chip through jumper cap JP 9-3;
the pin 20 of the J113 connector is connected with the pin 32 of the U12 chip through a jumper cap JP 10-3;
pin 21 of the J113 connector is connected to pin 33 of the U12 chip by jumper cap JP 11-3.
4. The scalable extensibility development board of claim 1, wherein: the pin 17 of the U12 chip is connected with the pin 51 of the U6 chip through a jumper cap JP27-1 and a jumper cap JP 15; the pins 18 of the U12 chip are connected to the pins 52 of the U6 chip through jumper caps JP26-1 and JP 17.
5. The scalable extensibility development board of claim 1, wherein: pin 4 of the U12 chip is connected to pin 27 of the U8 chip; pin 5 of the U12 chip connects to pin 28 of the U8 chip.
6. The scalable extensibility development board of claim 1, wherein: the interface circuit further includes a sixth power supply circuit connected to pin 39 and pin 41 of the J113 connector through JP 20-1.
7. The scalable extensibility development board of claim 1, wherein: the first signal output circuit further comprises a seventh power supply circuit, a U10 chip and a U11 chip; the seventh power circuit is connected with the pin 31 of the J113 connector through a jumper cap JP16 and is connected with the pin 50 of the U6 chip through a jumper cap JP 16;
pin 1 of the J1 connector and pin 5 of the U11 chip are connected with pin 37 of the U6 chip; pin 3 of the J1 connector and pin 4 of the U11 chip are connected to pin 36 of the U6 chip; pin 4 of the J1 connector and pin 2 of the U11 chip are connected to pin 34 of the U6 chip; pin 6 of the J1 connector and pin 1 of the U11 chip are connected to pin 33 of the U6 chip; pin 7 of the J1 connector and pin 5 of the U10 chip are connected to pin 31 of the U6 chip; pin 9 of the J1 connector and pin 4 of the U10 chip are connected to pin 30 of the U6 chip; pin 10 of the J1 connector and pin 2 of the U10 chip connect to pin 28 of the U6 chip; pin 12 of the J1 connector and pin 1 of the U10 chip connect to pin 27 of the U6 chip.
8. The scalable extensibility development board of claim 1, wherein: the signal conversion circuit also comprises a first power supply circuit, a second power supply circuit, a third power supply circuit, a fourth power supply circuit and a fifth power supply circuit, wherein each power supply circuit is used for supplying power to the signal conversion circuit; the first power supply circuit is connected with a pin 1, a pin 11, a pin 36 and a pin 54 of the U12 chip; the third power supply circuit, the fourth power supply circuit and the fifth power supply circuit are connected with a pin 2 and a pin 44 of the U12 chip; the second power circuit connects pin 15, pin 38, and pin 50 of the U12 chip.
9. The scalable extensibility development board of claim 1, wherein: the second signal output circuit further comprises an eighth power supply circuit, pin 5 of the U2 chip of which is connected to pin 16 of the U8 chip.
10. The scalable extensibility development board of claim 1, wherein: pin 15 of the U15 chip is connected to pin 3 of the U8 chip, and pin 16 of the U15 chip is connected to pin 2 of the U8 chip; pin 1 of the U15 chip is connected to pin 9 of the J113 connector through jumper cap JP22, and pin 5 of the U15 chip is connected to pin 7 of the J113 connector through jumper cap JP 23.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922483676.1U CN210864684U (en) | 2019-12-31 | 2019-12-31 | Can debug expansibility development board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922483676.1U CN210864684U (en) | 2019-12-31 | 2019-12-31 | Can debug expansibility development board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210864684U true CN210864684U (en) | 2020-06-26 |
Family
ID=71293508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922483676.1U Active CN210864684U (en) | 2019-12-31 | 2019-12-31 | Can debug expansibility development board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210864684U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112348763A (en) * | 2020-11-09 | 2021-02-09 | 西安宇视信息科技有限公司 | Image enhancement method, device, electronic equipment and medium |
-
2019
- 2019-12-31 CN CN201922483676.1U patent/CN210864684U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112348763A (en) * | 2020-11-09 | 2021-02-09 | 西安宇视信息科技有限公司 | Image enhancement method, device, electronic equipment and medium |
| CN112348763B (en) * | 2020-11-09 | 2024-05-14 | 西安宇视信息科技有限公司 | Image enhancement method, device, electronic equipment and medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103226506B (en) | Chip-embedded USB to JTAG debugging device and debugging method | |
| EP2587385B1 (en) | Usb key device and method for realizing intelligent card communication using usb interface | |
| CN108111382B (en) | Communication device based on I3C bus and communication method thereof | |
| CN207408936U (en) | A kind of multiplex roles PCIE device adapter | |
| RU195362U1 (en) | ARINC 429 and ARINC 825 Signal Input / Output Mezzanine Module | |
| CN105653461A (en) | System for converting single USB interface into plurality of UART debugging interfaces | |
| CN206684725U (en) | A kind of system that cpu temperature is obtained based on BMC | |
| CN210864684U (en) | Can debug expansibility development board | |
| CN116680220A (en) | Signal transceiver and signal receiving and transmitting system | |
| CN114721992A (en) | Server and server management system thereof | |
| CN110362058A (en) | The system tested for multiple interfaces | |
| CN203250308U (en) | USB JTAG conversion debugging device internally embedded in chip | |
| US20030120970A1 (en) | Method and apparatus for debugging an electronic product using an internal I/O port | |
| CN211906271U (en) | Electronic equipment and connecting wire | |
| CN206039399U (en) | Embedded hardware systems with debugging facility | |
| CN207503207U (en) | For the integrated test system of multiplex roles | |
| RU173335U1 (en) | Processor Module (MVE8S-RS) | |
| CN202433896U (en) | Serial port converter | |
| CN115766901A (en) | Data transmission equipment and method of image sensor | |
| CN214586491U (en) | Vector signal generating module | |
| CN210572737U (en) | Secondary radar signal processing device | |
| CN213582152U (en) | PCIE signal bit width automatic switching device of desktop and server system | |
| CN204302969U (en) | The USB/RS232-CAN translation debugging device of various configurations mode | |
| CN112968332A (en) | Compatible device and method for switching TYPE-C interface of tablet personal computer mainboard to UART serial port communication | |
| CN107885621B (en) | Hot standby computer based on Feiteng platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |