CN210835997U - Mainboard with LDO power supply oscillation suppression circuit - Google Patents
Mainboard with LDO power supply oscillation suppression circuit Download PDFInfo
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- CN210835997U CN210835997U CN201922227132.9U CN201922227132U CN210835997U CN 210835997 U CN210835997 U CN 210835997U CN 201922227132 U CN201922227132 U CN 201922227132U CN 210835997 U CN210835997 U CN 210835997U
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- mainboard
- power supply
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Abstract
The utility model discloses a mainboard with LDO power supply oscillation suppression circuit, including the mainboard body, be equipped with the LDO circuit on the mainboard body, the LDO circuit includes R661, R662, R659, C419, C323, CT9, Q56 and U21B, and the LDO circuit still includes R660, and the first end of R660 is connected with 4 feet of Q56, and the R660 second end is connected with 1, 2, 3 feet of Q56. The utility model discloses increase R660, make the modification to R659's resistance to R660 furthest offsets the utmost point capacitive characteristic of mos pipe GS, makes its characteristic be close high-power NPN triode more, and whole loop is more stable, guarantees that U21B state is best, and the amplitude is also the biggest, more can handle the fluctuation of various heavy loads from the beginning.
Description
Technical Field
The utility model relates to a computer motherboard field especially relates to a mainboard with LDO power supply oscillation suppression circuit.
Background
In the prior art, in order to reduce the cost of a main board on the market, many power supplies with output current of more than 6A are supplied by linear power Supplies (LDOs), and the cost of the power supplies is only about 1/5 of a switching power supply. However, because the dynamic of the load current of the main board is very large, when the traditional LDO is used at the place, if the control is not good, the vibration phenomenon can occur, the power output is completely changed into sawtooth waves, and the main board of the computer is halted or restarted.
According to the traditional large-current LDO principle, as shown in FIG. 1, R661 and R662 provide a non-inverting input end for an operational amplifier to provide a reference voltage, R659 is used for controlling the conduction time of a mos tube Q56, and C419, CT9 and C323 are power supply filter capacitors. Because the power devices of the main board LDO all adopt low-cost N-channel field effect transistors (see Q56), when the operational amplifier drives mos transistors, which are capacitive loads, the problems of high power output peak and oscillation are easily caused, and finally, the power output ripple is very high.
Accordingly, the prior art is deficient and needs improvement.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve is: the main board with the LDO power supply oscillation suppression circuit can cope with various large load fluctuations, ensure the stable output voltage of a power supply and has low cost.
The technical scheme of the utility model as follows: the utility model provides a mainboard with LDO power supply oscillation suppression circuit, includes the mainboard body, is provided with the LDO circuit on the mainboard body, the LDO circuit including: r661, R662, R659, C419, C323, CT9, Q56 and U21B, R661, R662 are connected respectively with the non inverting input end of U21B, U21B inverting input end is connected with 1, 2, 3 feet of Q56, U21B output end is connected with 4 feet of Q56 through R659, 5 feet of Q56 are grounded through C419, U21B inverting input end is also connected with CT9 first end and C323 first end respectively, CT9 second end and C323 second end are grounded respectively, the LDO circuit also includes R660, R660 first end is connected with 4 feet of Q56, R660 second end is connected with 1, 2, 3 feet of Q56.
By adopting the technical scheme, in the main board with the LDO power supply oscillation suppression circuit, the resistance value of R660 is 510 omega.
By adopting the technical scheme, in the main board with the LDO power supply oscillation suppression circuit, the resistance value of R659 is 100 omega.
Adopt above-mentioned each technical scheme, the utility model discloses an increase R660 to make the modification to R659's resistance, come the at utmost to offset the capacitive characteristic of mos pipe GS utmost point with R660's resistance, make its characteristic be close high-power NPN triode more, make whole loop more stable, guarantee that fortune is put U21B state best, the amplitude is also the biggest, more can the fluctuation of following various big loads leisurely, circuit design is simple, and the cost is very low.
Drawings
Fig. 1 is a schematic diagram of a conventional circuit structure of the present invention;
fig. 2 is a schematic diagram of an improved circuit structure of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
This embodiment provides a mainboard with LDO power supply oscillation suppression circuit, including the mainboard body, be provided with the LDO circuit on the mainboard body, the LDO circuit including: r661, R662, R659, C419, C323, CT9, Q56 and U21B, R661, R662 are connected respectively with the non inverting input end of U21B, U21B inverting input end is connected with 1, 2, 3 feet of Q56, U21B output end is connected with 4 feet of Q56 through R659, 5 feet of Q56 are grounded through C419, U21B inverting input end is also connected with CT9 first end and C323 first end respectively, CT9 second end and C323 second end are grounded respectively, the LDO circuit also includes R660, R660 first end is connected with 4 feet of Q56, R660 second end is connected with 1, 2, 3 feet of Q56.
Preferably, the resistance value of R660 is 510 Ω.
Preferably, the resistance of the R659 is 100 Ω.
As shown in FIG. 2, in order to make a smart improvement on the existing circuit, only one resistor is added, and other structures of the circuit are not modified, so that the low-cost improved circuit is realized to achieve a very ideal result. An R660 is arranged in the circuit, the resistance value of R659 is modified, and the resistance value of R659 is modified by 100 omega. Two ends of the R660 are respectively connected with the pin 4 of the Q56 and the pins 1, 2 and 3 of the Q56, the resistance value of the R660 is set to be a small resistance value which is 510 omega, the capacitive characteristic of the GS electrode of the mos tube is counteracted to the greatest extent by the small resistance value, and the characteristic of the GS electrode of the mos tube is made to be closer to that of a high-power NPN triode. R660 also provides negative feedback for Q56, making the overall loop more stable. In addition, R659 and R660 form a voltage divider circuit, so that while the power supply stabilizes the output voltage, the voltage of the 7 th pin of the operational amplifier U21B is ensured to be as close as possible to 1/2 × V12S (i.e., the operational amplifier supply voltage of 1/2), at this time, the operational state of the operational amplifier is optimal, the swing amplitude is also maximum, and various large load fluctuations can be coped with more easily.
Adopt above-mentioned each technical scheme, the utility model discloses an increase R660 to make the modification to R659's resistance, come the at utmost to offset the capacitive characteristic of mos pipe GS utmost point with R660's resistance, make its characteristic be close high-power NPN triode more, make whole loop more stable, guarantee that fortune is put U21B state best, the amplitude is also the biggest, more can the fluctuation of following various big loads leisurely, circuit design is simple, and the cost is very low.
The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (3)
1. The utility model provides a mainboard with LDO power supply oscillation suppression circuit, includes the mainboard body, is provided with the LDO circuit on the mainboard body, the LDO circuit including: r661, R662, R659, C419, C323, CT9, Q56 and U21B, wherein R661, R662 are connected with the non-inverting input terminal of U21B, the inverting input terminal of U21B is connected with 1, 2, 3 pins of Q56, the output terminal of U21B is connected with 4 pins of Q56 through R659, 5 pins of Q56 are grounded through C419, the inverting input terminal of U21B is connected with the first end of CT9 and the first end of C323, the second end of CT9 and the second end of C323 are grounded, respectively, characterized in that the LDO circuit further comprises R660, the first end of R660 is connected with 4 pins of Q56, and the second end of R660 is connected with 1, 2, 3 pins of Q56.
2. The motherboard having an LDO supply oscillation suppression circuit according to claim 1, wherein the resistance of R660 is 510 Ω.
3. The motherboard with an LDO supply oscillation suppression circuit according to claim 2, wherein the resistance of R659 is 100 Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922227132.9U CN210835997U (en) | 2019-12-12 | 2019-12-12 | Mainboard with LDO power supply oscillation suppression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922227132.9U CN210835997U (en) | 2019-12-12 | 2019-12-12 | Mainboard with LDO power supply oscillation suppression circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210835997U true CN210835997U (en) | 2020-06-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922227132.9U Active CN210835997U (en) | 2019-12-12 | 2019-12-12 | Mainboard with LDO power supply oscillation suppression circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210835997U (en) |
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2019
- 2019-12-12 CN CN201922227132.9U patent/CN210835997U/en active Active
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