CN105159385A - Low-power-dissipation low-dropout voltage regulator - Google Patents
Low-power-dissipation low-dropout voltage regulator Download PDFInfo
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- CN105159385A CN105159385A CN201510622166.1A CN201510622166A CN105159385A CN 105159385 A CN105159385 A CN 105159385A CN 201510622166 A CN201510622166 A CN 201510622166A CN 105159385 A CN105159385 A CN 105159385A
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Abstract
The invention provides a low-power-dissipation low-dropout voltage regulator which comprises an output transistor, an operational amplifier, a control transistor and a standby mode controller. The first input end of the operational amplifier is connected with reference voltage, the second input end of the operational amplifier is connected with the output end of the low-dropout voltage regulator, and the output end of the operational amplifier is connected with the control end of the output transistor; the first connecting end of the control transistor is connected with the voltage end of an input power supply, and the second connecting end of the control transistor is connected with the control end of the output transistor; the output end of the standby mode controller is connected with the enabled end of the operational amplifier and the control end of the control transistor. The input end of the standby mode controller receives a standby signal, when the standby signal is valid, the standby mode controller outputs periodic enabled signals with the preset duty ratio, and when the enabled signals are invalid, the control transistor is turned on, and the output transistor is cut off. Accordingly, the power dissipation of the low-dropout voltage regulator can be lowered.
Description
[technical field]
The present invention relates to low difference voltage regulator, particularly a kind of low-power consumption low difference voltage regulator.
[background technology]
Fig. 1 is the circuit diagram of existing a kind of low difference voltage regulator.
As shown in Figure 1, described low difference voltage regulator comprises operational amplifier OP1, output transistor MP1, output capacitance C1, the first resistance R1 and the second resistance R2.First resistance R1 and the second resistance R2 is series between output terminal VOUT and ground.The negative-phase input of operational amplifier is connected with reference voltage VREF, normal phase input end and between the first resistance R1 and the second resistance R2.The output terminal of operational amplifier is connected with the grid of output transistor MP1, and the source electrode of described output transistor MP1 is connected with input supply voltage VIN, and the drain electrode of output transistor MP1 is connected with output terminal VOUT.Output capacitance C1 is connected between output terminal VOUT and earth terminal.
The power end of described operational amplifier OP1 is connected with input supply voltage VIN.When normally working, on operational amplifier OP1, leakage current is the drive current that lop, MP1 flow through is Idrive, and load current is Iload.These two input signals can be done computing by described operational amplifier OP1, the voltage then after the output terminal of operational amplifier OP1 sends computing to control output transistor MP1, to provide the electric current needed for applicable load end.After the computing in whole loop, finally can obtain stable output voltage VO UT=VREF* (R1+R2)/R2.
When this low difference voltage regulator enters holding state (during Iload=0), in order to maintain the work of operational amplifier OP1, leakage current Iop still needs existence, that is, simultaneously, because resistance R1 and R2 has certain power consumption equally, like this for the situation of some battery applications, the serviceable life of battery will be shortened.
Along with present battery applications is more and more extensive, also more and more stronger to the demand of low-power consumption.Therefore, be necessary to propose a kind of improved plan to reduce the power consumption of described low difference voltage regulator when standby.
[summary of the invention]
An object of the present invention is to provide low-power consumption low difference voltage regulator, and it has very low power consumption in stand-by mode, also can keep the stable of output voltage in stand-by mode simultaneously.
In order to solve the problem, the invention provides a kind of low difference voltage regulator, it comprises: output transistor, it comprises the first link, the second link and control end, its first link is connected with input supply voltage end, and its second link is as the output terminal of described low difference voltage regulator, operational amplifier, it comprises first input end, the second input end, output terminal and Enable Pin, its first input end connects reference voltage, and the second input end is connected with the output terminal of described low difference voltage regulator, and its output terminal is connected with the control end of described output transistor, control transistor, it comprises the first link, the second link and control end, and its first link is connected with input supply voltage end, and its second link is connected with the control end of output transistor, standby mode controller, it comprises input end and output terminal, described output terminal is connected with the Enable Pin of described operational amplifier and the control end of described control transistor, wherein, described standby mode controller input end receives standby signal, when standby signal is effective, described standby mode controller exports the periodic enable signal of predetermined duty cycle, when described enable signal is invalid, described control transistor turns, described output transistor cut-off, described operational amplifier quits work, when described enable signal is effective, described control transistor cutoff, described output transistor conducting, described operational amplifier normally works.
Further, the dutycycle of described enable signal refers to the ratio effectively continuing duration and minimum clock cycle, and described predetermined duty cycle is lower than 20%.
Further, when standby signal is invalid, described standby mode controller exports the enable signal REG_EN of continuous and effective.
Further, low difference voltage regulator also includes: output capacitance, between its output terminal being series at described low difference voltage regulator and earth terminal.
Further, when described operational amplifier quits work, power consumption is zero.
Further, described control transistor and described output transistor are PMOS transistor, the source electrode of PMOS transistor is called as the first link, the drain electrode of PMOS transistor is called as the second link, the grid of PMOS transistor is called as control end, the first input end of described operational amplifier is negative-phase input, and the second input end is normal phase input end.
Compared with prior art, the present invention, when entering standby mode, makes this operational amplifier and the step work of output transistor, thus greatly reduces operational amplifier power consumption in stand-by mode.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 shows the circuit diagram of existing low difference voltage regulator;
Fig. 2 shows low difference voltage regulator of the present invention circuit diagram in one embodiment;
Fig. 3 is the sequential chart of each signal in Fig. 2.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
Fig. 2 shows low difference voltage regulator of the present invention circuit diagram in one embodiment.As shown in Figure 2, described low difference voltage regulator comprises output transistor MP3, controls transistor MP4, output capacitance C2, operational amplifier OP2, standby mode controller.In one embodiment, output transistor MP3, control transistor MP4, operational amplifier OP2, standby mode controller are integrated in same chip, and output capacitance C2 is positioned at outside chip.
Described output transistor MP3 comprises the first link, the second link and control end, and its first link is connected with input supply voltage end VIN, and its second link is as the output terminal VOUT of described low difference voltage regulator.Described operational amplifier comprises first input end, the second input end, output terminal and Enable Pin REG_EN, its first input end connects reference voltage VREF, second input end is connected with the output terminal VOUT of described low difference voltage regulator, and its output terminal is connected with the control end of described output transistor MP3.Described control transistor MP4 comprises the first link, the second link and control end, and its first link is connected with input supply voltage end VIN, and its second link is connected with the control end of output transistor.Described standby mode controller comprises input end and output terminal, and described output terminal is connected with the Enable Pin of described operational amplifier OP2 and the control end of described control transistor MP4.In one embodiment, described control transistor MP3 and described output transistor MP4 is PMOS transistor, the source electrode of PMOS transistor is called as the first link, and the source electrode of PMOS transistor is called as the second link, and the grid of PMOS transistor is called as control end.
The input end of described standby mode controller receives standby signal SLEEP, when standby signal SLEEP is effective, described standby mode controller exports the periodic enable signal REG_EN of predetermined duty cycle, when described enable signal is invalid, described control transistor MP4 conducting, described output transistor MP3 ends, described operational amplifier OP4 quits work, when described enable signal REG_EN is effective, described control transistor MP4 ends, described output transistor MP3 conducting, described operational amplifier OP2 normally works.When standby signal is invalid, described standby mode controller exports the effective enable signal REG_EN continued.
When normal mode, due to the adjustment of described operational amplifier OP2, make the output voltage of output terminal VOUT controlledly can equal reference voltage VREF.
As shown in Figure 3, the high level of standby signal SLEEP is that effectively low level is invalid, and enable signal REG_EN high level is that effectively low level is invalid.Be normal mode when standby signal SLEEP is low level, be now normal mode, enable signal REG_EN is continuously high level, and described control transistor MP4 ends, described output transistor MP3 conducting, and described operational amplifier OP2 normally works.Leakage current lop exists.
It is standby mode when standby signal SLEEP is high level, now enable signal REG_EN is the periodic timing signal of predetermined duty cycle, when enable signal REG_EN is low level, described control transistor MP4 conducting, described output transistor MP3 ends, described operational amplifier OP2 quits work, output voltage VO UT can reduce gradually due to leakage current, when enable signal REG_EN is high level, described control transistor MP4 ends, described output transistor MP3 conducting, described operational amplifier OP2 normally works, thus output voltage VO UT adjustment is equaled described reference voltage VREF.In the present invention, do not arrange as divider resistance R1 and R2 in Fig. 1, output terminal VOUT leakage current in stand-by mode can be reduced like this, reduce power consumption.
Can find out, in part-time in stand-by mode, the power consumption of operational amplifier OP2 is 0, and within the other time, just consume certain electric current, greatly reduce operational amplifier OP2 power consumption in stand-by mode like this, also ensure that the output voltage VO UT in the present invention keeps relative stablizing, externally to provide basic voltage in stand-by mode simultaneously.
The dutycycle of described enable signal REG_EN refers to that high level continues the ratio of duration and minimum clock cycle.Preferably, described predetermined duty cycle is lower than 20%, and predetermined duty cycle is lower, and in stand-by mode, the power consumption of low difference voltage regulator is lower.But in order to keep output voltage VO UT can meet basic stability requirement, predetermined duty cycle can not be too low.The value of described predetermined duty cycle is relevant with the size of the minimum voltage of the capacitance of output capacitance C2, output voltage VO UT and the leakage current of output terminal VOUT, according to different application, can design different dutycycles.
In one embodiment, when enable signal REG_EN is invalid, directly by the dump of operational amplifier OP2, can quit work to make described operational amplifier OP2.Also can adopt other modes that described operational amplifier OP2 is quit work.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (6)
1. a low difference voltage regulator, is characterized in that, it comprises:
Output transistor, it comprises the first link, the second link and control end, and its first link is connected with input supply voltage end, and its second link is as the output terminal of described low difference voltage regulator;
Operational amplifier, it comprises first input end, the second input end, output terminal and Enable Pin, its first input end connects reference voltage, and the second input end is connected with the output terminal of described low difference voltage regulator, and its output terminal is connected with the control end of described output transistor;
Control transistor, it comprises the first link, the second link and control end, and its first link is connected with input supply voltage end, and its second link is connected with the control end of output transistor;
Standby mode controller, it comprises input end and output terminal, and described output terminal is connected with the Enable Pin of described operational amplifier and the control end of described control transistor, wherein,
Described standby mode controller input end receives standby signal, when standby signal is effective, described standby mode controller exports the periodic enable signal of predetermined duty cycle, when described enable signal is invalid, and described control transistor turns, described output transistor cut-off, described operational amplifier quits work, when described enable signal is effective, and described control transistor cutoff, described output transistor conducting, described operational amplifier normally works.
2. low difference voltage regulator according to claim 1, is characterized in that, the dutycycle of described enable signal refers to the ratio effectively continuing duration and minimum clock cycle, and described predetermined duty cycle is lower than 20%.
3. low difference voltage regulator according to claim 1, is characterized in that, when standby signal is invalid, described standby mode controller exports the enable signal REG_EN of continuous and effective.
4. low difference voltage regulator according to claim 1, is characterized in that, it also includes:
Output capacitance, between its output terminal being series at described low difference voltage regulator and earth terminal.
5. low difference voltage regulator according to claim 1, is characterized in that, when described operational amplifier quits work, power consumption is zero.
6. low difference voltage regulator according to claim 1, it is characterized in that, described control transistor and described output transistor are PMOS transistor, the source electrode of PMOS transistor is called as the first link, the drain electrode of PMOS transistor is called as the second link, the grid of PMOS transistor is called as control end
The first input end of described operational amplifier is negative-phase input, and the second input end is normal phase input end.
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| CN201510622166.1A CN105159385B (en) | 2015-09-25 | 2015-09-25 | Low-power-dissipation low-dropout voltage regulator |
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| CN201510622166.1A CN105159385B (en) | 2015-09-25 | 2015-09-25 | Low-power-dissipation low-dropout voltage regulator |
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| CN105159385B CN105159385B (en) | 2017-01-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160419A (en) * | 2016-08-23 | 2016-11-23 | 黄继颇 | Low voltage difference voltage-stabilized power supply circuit structure |
| CN109753099A (en) * | 2018-12-21 | 2019-05-14 | 西安电子科技大学 | A kind of digital simulation dual-loop low dropout regulator |
| CN111781980A (en) * | 2020-06-15 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Voltage control circuit and control method thereof |
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| CN202257345U (en) * | 2011-09-28 | 2012-05-30 | 北京经纬恒润科技有限公司 | Low drop-out linear voltage regulator |
| CN203520222U (en) * | 2013-11-12 | 2014-04-02 | 北京经纬恒润科技有限公司 | LDO (low dropout regulator) |
| US20150015223A1 (en) * | 2013-07-15 | 2015-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low Dropout Regulator and Related Method |
| CN104881072A (en) * | 2015-05-22 | 2015-09-02 | 无锡中星微电子有限公司 | Low-dropout voltage regulator and power supply system |
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2015
- 2015-09-25 CN CN201510622166.1A patent/CN105159385B/en active Active
Patent Citations (5)
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| US6414537B1 (en) * | 2000-09-12 | 2002-07-02 | National Semiconductor Corporation | Voltage reference circuit with fast disable |
| CN202257345U (en) * | 2011-09-28 | 2012-05-30 | 北京经纬恒润科技有限公司 | Low drop-out linear voltage regulator |
| US20150015223A1 (en) * | 2013-07-15 | 2015-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low Dropout Regulator and Related Method |
| CN203520222U (en) * | 2013-11-12 | 2014-04-02 | 北京经纬恒润科技有限公司 | LDO (low dropout regulator) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106160419A (en) * | 2016-08-23 | 2016-11-23 | 黄继颇 | Low voltage difference voltage-stabilized power supply circuit structure |
| CN106160419B (en) * | 2016-08-23 | 2018-09-14 | 黄继颇 | Low voltage difference voltage-stabilized power supply circuit structure |
| CN109753099A (en) * | 2018-12-21 | 2019-05-14 | 西安电子科技大学 | A kind of digital simulation dual-loop low dropout regulator |
| CN111781980A (en) * | 2020-06-15 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Voltage control circuit and control method thereof |
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| CN105159385B (en) | 2017-01-18 |
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Denomination of invention: Low-power-dissipation low-dropout voltage regulator Effective date of registration: 20180420 Granted publication date: 20170118 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
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Date of cancellation: 20190416 Granted publication date: 20170118 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
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Address after: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |