CN105159385B - Low-power-dissipation low-dropout voltage regulator - Google Patents
Low-power-dissipation low-dropout voltage regulator Download PDFInfo
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- CN105159385B CN105159385B CN201510622166.1A CN201510622166A CN105159385B CN 105159385 B CN105159385 B CN 105159385B CN 201510622166 A CN201510622166 A CN 201510622166A CN 105159385 B CN105159385 B CN 105159385B
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Abstract
The invention provides a low-power-dissipation low-dropout voltage regulator which comprises an output transistor, an operational amplifier, a control transistor and a standby mode controller. The first input end of the operational amplifier is connected with reference voltage, the second input end of the operational amplifier is connected with the output end of the low-dropout voltage regulator, and the output end of the operational amplifier is connected with the control end of the output transistor; the first connecting end of the control transistor is connected with the voltage end of an input power supply, and the second connecting end of the control transistor is connected with the control end of the output transistor; the output end of the standby mode controller is connected with the enabled end of the operational amplifier and the control end of the control transistor. The input end of the standby mode controller receives a standby signal, when the standby signal is valid, the standby mode controller outputs periodic enabled signals with the preset duty ratio, and when the enabled signals are invalid, the control transistor is turned on, and the output transistor is cut off. Accordingly, the power dissipation of the low-dropout voltage regulator can be lowered.
Description
[technical field]
The present invention relates to low difference voltage regulator, particularly to a kind of low-power consumption low difference voltage regulator.
[background technology]
Fig. 1 is a kind of circuit diagram of existing low difference voltage regulator.
As shown in figure 1, described low difference voltage regulator includes operational amplifier op1, output transistor mp1, output electricity
Hold c1, first resistor r1 and second resistance r2.First resistor r1 and second resistance r2 are series between output end vout and ground.Fortune
The negative-phase input calculating amplifier is connected with reference voltage vref, normal phase input end and first resistor r1 and second resistance r2 it
Between.The output end of operational amplifier is connected with the grid of output transistor mp1, the source electrode of described output transistor mp1 and input
Supply voltage vin is connected, and the drain electrode of output transistor mp1 is connected with output end vout.Output capacitance c1 is connected to output end
Between vout and earth terminal.
The power end of described operational amplifier op1 is connected with input supply voltage vin.In normal work, operation amplifier
On device op1, leakage current is iop, and the driving current that mp1 flows through is idrive, and load current is iload.Described operational amplifier
This two input signals can be done computing by op1, and the voltage after then the output end in operational amplifier op1 sends computing is controlling
Output transistor mp1, to provide the electric current needed for suitable load end.After the computing in whole loop, finally can obtain one
Stable output voltage vout=vref* (r1+r2)/r2.
When this low difference voltage regulator enters holding state (during iload=0), in order to maintain operational amplifier
The work of op1, leakage current iop still needs presence that is to say, that simultaneously as resistance r1 and r2 equally has certain work(
Consumption, when so for some battery applications, will shorten the service life of battery.
More and more extensive with present battery applications, also more and more stronger to the demand of low-power consumption.Therefore, it is necessary to propose
A kind of improved plan is reducing power consumption when standby for the described low difference voltage regulator.
[content of the invention]
An object of the present invention is to provide low-power consumption low difference voltage regulator, and it has very low in stand-by mode
Power consumption, also can keep stablizing of output voltage in stand-by mode simultaneously.
In order to solve the above problems, the present invention provides a kind of low difference voltage regulator, comprising: output transistor, its
Including the first connection end, the second connection end and control end, its first connection end is connected with input supply voltage end, its second connection
End is as the output end of described low difference voltage regulator；Operational amplifier, it includes first input end, the second input, defeated
Go out end and Enable Pin, its first input end connects reference voltage, the output of the second input and described low difference voltage regulator
End is connected, and its output end is connected with the control end of described output transistor；Controlling transistor, it include the first connection end, second
Connection end and control end, its first connection end is connected with input supply voltage end, the control of its second connection end and output transistor
End processed is connected；Standby mode controller, it includes input and output end, the output end of described standby mode controller with described
The control end of the Enable Pin of operational amplifier and described controlling transistor is connected, wherein, described standby mode controller input
End receives standby signal, and when standby signal is effective, described standby mode controller exports periodically making of predetermined duty cycle
Energy signal, in described enable invalidating signal, described controlling transistor conducting, described output transistor cut-off, described computing is put
Big device quits work, when described enable signal is effective, described controlling transistor cut-off, and described output transistor conducting, described
Operational amplifier normal work.
Further, the described dutycycle enabling signal refers to the ratio of effective duration and minimum clock cycle, institute
State predetermined duty cycle and be less than 20%.
Further, when standby signal is invalid, described standby mode controller exports the enable signal of continuous and effective
reg_en.
Further, low difference voltage regulator also includes: output capacitance, and it is series at described low drop voltage and adjusts
Between the output end of device and earth terminal.
Further, when described operational amplifier quits work, power consumption is zero.
Further, described controlling transistor and described output transistor are pmos transistor, the source electrode of pmos transistor
It is referred to as the first connection end, the drain electrode of pmos transistor is referred to as the second connection end, and the grid of pmos transistor is referred to as controlling
End, the first input end of described operational amplifier is negative-phase input, and the second input is normal phase input end.
Compared with prior art, the present invention when entering standby mode so that this operational amplifier and output transistor
Step work, thus greatly reduce operational amplifier power consumption in stand-by mode.
[brief description]
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below will be to required use in embodiment description
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, without having to pay creative labor, it can also be obtained according to these accompanying drawings
Its accompanying drawing.Wherein:
Fig. 1 shows the circuit diagram of existing low difference voltage regulator；
Fig. 2 shows the low difference voltage regulator of present invention circuit diagram in one embodiment；
Fig. 3 is the sequential chart of each signal in Fig. 2.
[specific embodiment]
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings and specifically real
The present invention is further detailed explanation to apply mode.
" embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the present invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, is not single or optionally mutually exclusive with other embodiment embodiment.Unless stated otherwise, herein
In connection, be connected, connect represent that the word being electrically connected with all represents and is directly or indirectly electrical connected.
Fig. 2 shows the low difference voltage regulator of present invention circuit diagram in one embodiment.As shown in Figure 2
, described low difference voltage regulator includes output transistor mp3, controlling transistor mp4, output capacitance c2, operational amplifier
Op2, standby mode controller.In one embodiment, output transistor mp3, controlling transistor mp4, operational amplifier op2,
Standby mode controller is integrated in same chip, and output capacitance c2 is located at outside chip.
Described output transistor mp3 includes the first connection end, the second connection end and control end, its first connection end and input
Power voltage terminal vin is connected, and its second connection end is as output end vout of described low difference voltage regulator.Described computing is put
Big device includes first input end, the second input, output end and Enable Pin reg_en, and its first input end connects reference voltage
Vref, the second input is connected with output end vout of described low difference voltage regulator, its output end and described output crystal
The control end of pipe mp3 is connected.Described controlling transistor mp4 includes the first connection end, the second connection end and control end, its first company
Connect end to be connected with input supply voltage end vin, its second connection end is connected with the control end of output transistor.Described standby mode
Controller includes input and output end, and described output end is brilliant with the Enable Pin of described operational amplifier op2 and described control
The control end of body pipe mp4 is connected.In one embodiment, described controlling transistor mp4 and described output transistor mp3 are pmos
Transistor, the source electrode of pmos transistor is referred to as the first connection end, and the drain electrode of pmos transistor is referred to as the second connection end, pmos
The grid of transistor is referred to as control end.
The input of described standby mode controller receives standby signal sleep, when standby signal sleep is effective, institute
State the periodic enable signal reg_en that standby mode controller exports predetermined duty cycle, in described enable invalidating signal,
Described controlling transistor mp4 conducting, described output transistor mp3 cut-off, described operational amplifier op2 quits work, described
When enable signal reg_en is effective, described controlling transistor mp4 cut-off, described output transistor mp3 conducting, described operation amplifier
Device op2 normal work.When standby signal is invalid, the lasting effective enable signal reg_ of described standby mode controller output
en.
In normal mode, because the adjustment of described operational amplifier op2 is so that the output voltage of output end vout can quilt
Adjustment equal to reference voltage vref.
As shown in Figure 3, the high level of standby signal sleep is effective, and low level is invalid, enables signal reg_en high
Level is effective, and low level is invalid.It is normal mode when standby signal sleep is for low level, now for normal mode, make
High level can be continuously by signal reg_en, described controlling transistor mp4 cut-off, described output transistor mp3 conducting, described computing
Amplifier op2 normal work.Leakage current iop exists.
It is standby mode when standby signal sleep is for high level, now enabling signal reg_en is predetermined duty cycle
Periodic timing signal, when enabling signal reg_en for low level, described controlling transistor mp4 conducting, described output crystal
Pipe mp3 ends, and described operational amplifier op2 quits work, and output voltage vout can be gradually lowered due to leakage current, is enabling
When signal reg_en is high level, described controlling transistor mp4 cut-off, described output transistor mp3 conducting, described operation amplifier
Device op2 normal work, thus output voltage vout adjustment is equal to described reference voltage vref.In the present invention, and be not provided with
As divider resistance r1 and r2 in Fig. 1, so can reduce output end vout leakage current in stand-by mode, reduce power consumption.
As can be seen that the power consumption of operational amplifier op2 is 0 in part-time in stand-by mode, and when other
The interior just certain electric current of consumption, so greatly reduces operational amplifier op2 power consumption in stand-by mode, also protects simultaneously
The output voltage vout having demonstrate,proved in the present invention keeps relative stablizing, externally to provide basic voltage in stand-by mode.
The dutycycle of described enable signal reg_en refers to the ratio of high level duration and minimum clock cycle.Preferably
, described predetermined duty cycle is less than 20%, and predetermined duty cycle is lower, in stand-by mode, the power consumption of low difference voltage regulator
Lower.However, in order to keep output voltage vout to disclosure satisfy that basic stability requirement, predetermined duty cycle nor too low.Institute
State the value of predetermined duty cycle and the capacitance of output capacitance c2, the minimum voltage of output voltage vout and output end vout
The size of leakage current is relevant, can design different dutycycles according to different applications.
In one embodiment, when it is invalid for enabling signal reg_en, can be directly by the power supply of operational amplifier op2
Cut-out, so that described operational amplifier op2 quits work.Described operational amplifier op2 can also be made using other modes
Quit work.
It is pointed out that any change that one skilled in the art is done to the specific embodiment of the present invention
Scope all without departing from claims of the present invention.Correspondingly, the scope of the claim of the present invention is also not merely limited to
In previous embodiment.
Claims (6)
1. a kind of low difference voltage regulator it is characterised in that comprising:
Output transistor, it includes the first connection end, the second connection end and control end, its first connection end and input supply voltage
End is connected, and its second connection end is as the output end of described low difference voltage regulator；
Operational amplifier, it includes first input end, the second input, output end and Enable Pin, and its first input end connects ginseng
Examine voltage, the second input is connected with the output end of described low difference voltage regulator, its output end and described output transistor
Control end be connected；
Controlling transistor, it includes the first connection end, the second connection end and control end, its first connection end and input supply voltage
End is connected, and its second connection end is connected with the control end of output transistor；
Standby mode controller, it includes input and output end, the output end of described standby mode controller and described computing
The control end of the Enable Pin of amplifier and described controlling transistor is connected, wherein,
Described standby mode controller input receives standby signal, when standby signal is effective, described standby mode controller
The periodic enable signal of output predetermined duty cycle, in described enable invalidating signal, described controlling transistor conducting, described
Output transistor ends, and described operational amplifier quits work, and when described enable signal is effective, described controlling transistor is cut
Only, described output transistor conducting, described operational amplifier normal work.
2. low difference voltage regulator according to claim 1 is it is characterised in that the dutycycle of described enable signal refers to
Effective duration and the ratio of minimum clock cycle, described predetermined duty cycle is less than 20%.
3. low difference voltage regulator according to claim 1 is it is characterised in that when standby signal is invalid, described treats
Machine mode controller exports the enable signal reg_en of continuous and effective.
4. low difference voltage regulator according to claim 1 is it is characterised in that it also includes:
Output capacitance, it is series between the output end of described low difference voltage regulator and earth terminal.
5. low difference voltage regulator according to claim 1 is it is characterised in that quit work in described operational amplifier
When, power consumption is zero.
6. low difference voltage regulator according to claim 1 is it is characterised in that described controlling transistor and described output
Transistor is pmos transistor, and the source electrode of pmos transistor is referred to as the first connection end, and the drain electrode of pmos transistor is referred to as the
Two connection ends, the grid of pmos transistor is referred to as control end,
The first input end of described operational amplifier is negative-phase input, and the second input is normal phase input end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510622166.1A CN105159385B (en) | 2015-09-25 | 2015-09-25 | Low-power-dissipation low-dropout voltage regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510622166.1A CN105159385B (en) | 2015-09-25 | 2015-09-25 | Low-power-dissipation low-dropout voltage regulator |
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| CN105159385A CN105159385A (en) | 2015-12-16 |
| CN105159385B true CN105159385B (en) | 2017-01-18 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106160419B (en) * | 2016-08-23 | 2018-09-14 | 黄继颇 | Low voltage difference voltage-stabilized power supply circuit structure |
| CN109753099B (en) * | 2018-12-21 | 2020-06-09 | 西安电子科技大学 | Digital analog double-loop low dropout linear voltage regulator |
| CN111781980B (en) * | 2020-06-15 | 2022-08-16 | 上海华虹宏力半导体制造有限公司 | Voltage control circuit and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6414537B1 (en) * | 2000-09-12 | 2002-07-02 | National Semiconductor Corporation | Voltage reference circuit with fast disable |
| CN202257345U (en) * | 2011-09-28 | 2012-05-30 | 北京经纬恒润科技有限公司 | Low drop-out linear voltage regulator |
| US9459642B2 (en) * | 2013-07-15 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low dropout regulator and related method |
| CN203520222U (en) * | 2013-11-12 | 2014-04-02 | 北京经纬恒润科技有限公司 | LDO (low dropout regulator) |
| CN104881072B (en) * | 2015-05-22 | 2016-05-11 | 无锡中感微电子股份有限公司 | Low difference voltage regulator and electric power system |
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Denomination of invention: Low-power-dissipation low-dropout voltage regulator Effective date of registration: 20180420 Granted publication date: 20170118 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
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Date of cancellation: 20190416 Granted publication date: 20170118 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
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Address after: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: 201203 7th floor, building 2, 1158 Zhangdong Road, Zhangjiang hi tech, Pudong New Area, Shanghai Patentee before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |