CN210743950U - 二极管结构和二极管 - Google Patents

二极管结构和二极管 Download PDF

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CN210743950U
CN210743950U CN201921627456.5U CN201921627456U CN210743950U CN 210743950 U CN210743950 U CN 210743950U CN 201921627456 U CN201921627456 U CN 201921627456U CN 210743950 U CN210743950 U CN 210743950U
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F·拉努瓦
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STMicroelectronics Tours SAS
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Abstract

本文描述了二极管结构和二极管。一种二极管结构包括：衬底，具有沟槽；第一传导区域，位于所述沟槽中并且与所述衬底分离第一距离，所述第一距离短于约10nm；以及第二传导区域，位于所述沟槽中并且比所述第一传导区域更深地延伸。

Description

二极管结构和二极管
技术领域
本公开一般地涉及电子电路，更具体地涉及二极管结构和二极管。
背景技术
在某些应用中，例如在功率电子应用中，期望二极管能够利用二极管两端尽可能低的电压降来在正向电流中传导高值，例如大于1A、或者甚至大于100A。进一步期望二极管在反向偏置时传导尽可能低的电流。进一步期望二极管能够阻挡电流流动来获得高反向电压值，例如大于10V、或甚至大于100V。
实用新型内容
一个实施例提供了克服已知二极管结构的全部或部分的缺点。
一个实施例提供了能够获得具有最大反向电压或雪崩电压的二极管的结构，相对于已知的二极管，正向电压降和/或漏电流得到改善。
在一个方面，提供了一种二极管结构。该二极管结构包括：衬底，具有沟槽；第一传导区域，位于所述沟槽中并且与所述衬底分离第一距离，所述第一距离短于10nm；以及第二传导区域，位于所述沟槽中并且比所述第一传导区域更深地延伸。
在一些实施例中，所述第二传导区域与所述衬底分离第二距离，所述第二距离大于所述第一距离。
在一些实施例中，所述二极管结构进一步包括：第一电介质层，将所述第一传导区域与所述衬底分离；以及第二电介质层，将所述第二传导区域与所述衬底分离。
在一些实施例中，所述衬底是半导体。
在一些实施例中，所述二极管结构包括覆盖所述衬底和所述沟槽的传导层，所述传导层电连接到所述衬底以及电连接到所述第一传导区域和所述第二传导区域。
在一些实施例中，所述传导层与所述衬底接触或者与所述衬底分离小于300nm。
在另一方面，提供了一种二极管。该二极管包括：衬底，具有第一沟槽；阴极和阳极，耦合到所述衬底；第一传导区域，位于所述沟槽中并且与所述衬底分离第一距离，所述第一距离短于10nm；以及第二传导区域，位于所述沟槽中并且比所述第一传导区域更深地延伸。
在一些实施例中，所述衬底包括第二沟槽，所述二极管进一步包括：至少一个晶体管，具有在所述第一沟槽和所述第二沟槽之间延伸的至少一个沟道区域，所述第一传导区域限定所述至少一个晶体管的栅极。
在一些实施例中，所述二极管包括：传导层，覆盖所述衬底以及所述第一沟槽和所述第二沟槽；以及接触区域，形成在所述衬底中并且将所述沟道区域电连接到所述传导层。
在一些实施例中，所述第一传导区域和所述第二传导区域是半导体区域，所述沟道区域和所述第一传导区域掺杂有相反的导电类型。
在一些实施例中，所述二极管包括漏极区域，所述漏极区域在所述沟道区域下方以及在所述第一沟槽和所述第二沟槽之间延伸。
在一些实施例中，所述漏极区域比所述沟道区域更少地被重掺杂。
在一些实施例中，所述漏极区域在所述第一沟槽和所述第二沟槽下方延伸。
在另一方面，提供了一种二极管。该二极管包括：半导体衬底；阴极和阳极，耦合到所述衬底；第一垂直晶体管，位于所述衬底中，所述第一垂直晶体管包括：电耦合到所述阳极的第一源极区域、垂直延伸到所述衬底中并且电耦合到所述阳极的第一栅极、电耦合到所述阴极的第一漏极区域、位于所述第一源极区域和所述第一漏极区域之间的第一沟道区域、以及在所述衬底中延伸并且位于所述第一栅极和所述第一沟道区域之间的第一栅极电介质。
在一些实施例中，所述栅极是第一传导区域，所述第一传导区域与所述沟道区域分离第一距离，所述二极管进一步包括：第二传导区域，比所述第一传导区域更深地延伸到所述衬底中并且与所述漏极区域分离第二距离，所述第二距离大于所述第一距离。
在一些实施例中，所述二极管进一步包括：第二垂直晶体管，位于所述衬底中，所述第二垂直晶体管包括：电耦合到所述阳极的第二源极区域、垂直延伸到所述衬底中并且电耦合到所述阳极的第二栅极、电耦合到所述阴极的第二漏极区域、位于所述第二源极区域和所述第二漏极区域之间的第二沟道区域、以及在所述衬底中延伸并且位于所述第二栅极和所述第二沟道区域之间的第二栅极电介质。
在一些实施例中，所述二极管包括：传导层，覆盖所述衬底以及所述第一垂直晶体管和所述第二垂直晶体管；以及接触区域，形成在所述衬底中并且将所述第一沟道区域和所述第二沟道区域电连接到所述传导层。
因此，一个实施例提供了一种结构，该结构在衬底的沟槽中包括：第一传导区域，其与衬底分离第一距离，第一距离短于约10nm；以及第二传导区域，其比第一区域更深地延伸。
根据一个实施例，第二区域与衬底分离第二距离，第二距离大于第一距离。
根据一个实施例，第一区域通过第一电介质层与衬底分离，并且第二区域通过第二电介质层与衬底分离。
根据一个实施例，该衬底是半导体。
根据一个实施例，该结构包括覆盖衬底和沟槽的传导层部分，所述部分电连接到衬底以及第一区域和第二区域。
根据一个实施例，所述部分与衬底接触或者与衬底分离小于300nm。
一个实施例提供了包括一个或多个以上限定的结构的二极管。
根据一个实施例，该二极管由一个或多个晶体管限定，晶体管具有在两个沟槽之间延伸的至少一个沟道区域，第一区域限定晶体管栅极。
根据一个实施例，该二极管包括将沟道区域电连接到传导层的接触区域。
根据一个实施例，第一区域是半导体区域，沟道区域和第一区域掺杂有相反的导电类型。
根据一个实施例，该二极管包括漏极区域，漏极区域在两个沟槽之间的沟道区域下方延伸，并且优选地在沟槽下方延伸。
根据一个实施例，漏极区域比沟道区域更少地被重掺杂。
根据本公开的实施例，已知二极管结构的全部或部分的缺点被克服，并且正向电压降和/或漏电流得到改善。
附图说明
参考附图，在下面以说明而非限制的方式给出的具体实施例的描述中将详细描述前述特征和优点以及其他特征和优点，在附图中：
图1是图示二极管的实施例的简化截面图；以及
图2A至图2F图示了制造图1的二极管的方法的实现方式的步骤。
具体实施方式
在各个附图中，相同的元件用相同的附图标记表示，并且各个附图未按比例绘制。为清楚起见，仅示出并详细描述了对理解所描述的实施例有用的那些步骤和元件。
在以下描述中，当参考限定绝对位置(例如，术语“前”、“后”、“顶部”、“底部”、“左”、“右”等)或相对位置(例如，术语“之上”、“之下”、“上方”、“下方”等)的术语或参考限定方向(例如，术语“水平”、“垂直”等)的术语时，指的是有关元件在附图中的定向，应理解，在实践中，所描述的器件可以不同地定向。除非另有说明，否则表述“约”、“大约”、“基本上”和“……数量级”表示在10％以内、优选在5％以内。
图1是图示二极管10的实施例的简化截面图。
二极管10包括例如由诸如硅的半导体制成的衬底20。二极管包括例如电连接到衬底的下表面的阴极端子K以及阳极端子A。二极管10包括沟槽22。沟槽22在衬底20中从衬底的上表面延伸。沟槽22例如彼此平行。沟槽22例如规则地间隔开。作为变型，沟槽22呈同心环的形状。
二极管包括下文描述的结构30A，结构30A各自位于沟槽22中。二极管例如包括在二极管任一侧上的两个结构30A。在结构30A之间，二极管可以进一步包括一个或多个结构30。
在相关的沟槽22中，每个结构30包括电传导区域302。传导区域302位于沟槽22的上部分中。区域302与沟槽22的壁分离。区域302例如通过布置在区域302的任一侧上的电介质层304与壁分离。可以理解，层304可以是相同电介质层的一部分。区域302和壁分离短距离d，其优选地小于10nm，例如小于7nm。
每个结构30进一步包括在沟槽中比区域302更低地延伸的电传导区域306。在图1所示的示例中，区域306从区域302延伸。换言之，区域302和306是单件。区域306例如位于比区域302更远离沟槽壁。区域302例如通过覆盖沟槽22的壁和底部的电介质层308与衬底10分离。层308的厚度例如大于约100nm，优选地在从250nm到1000nm的范围内。
结构30A包括与结构30相同的元件。然而，重要的是在二极管的外侧上不存在上文提到的短距离d。作为示例，层308于是在二极管的外侧上在区域302与沟槽壁之间继续。层308可以连接覆盖二极管的外围上的衬底的绝缘层44。
作为示例，区域302和306由掺杂的多晶硅制成，并且层304和308由氧化硅制成。
如下文在二极管10的特定情况下所讨论，由此获得的区域302和306在施加电势时能够对与层304和308接触的衬底部分施加不同的静电影响。特别地，区域302距离衬底越近，与层304接触的衬底部分上的静电影响越强。
然后可以在与每个层304接触的衬底部分中形成晶体管T1，所考虑的区域302形成晶体管栅极。作为示例，晶体管T1具有N沟道。每个晶体管包括P型掺杂的沟道区域202(P)。作为示例，每个沟道区域202在两个相邻的沟槽22之间延伸，并且因此对于两个相邻的晶体管T1是公共的。沟道区域例如顶部具有接触区域204(P+)。接触区域204比沟道区域202更重地被P型掺杂。
每个晶体管进一步包括位于沟道区域下方的漏极区域206(N-)。作为示例，每个漏极区域206在两个相邻的沟槽22之间延伸并且对于相邻的晶体管T1是公共的。漏极区域206可以在沟槽下方延伸，并且漏极区域于是可以在沟槽下方连接。漏极区域例如在衬底下部部分上延伸的接触区域208(N+)的顶部上并且与接触区域208(N+)接触。区域208比漏极区域206更重地被掺杂。区域208电连接到端子K。
每个晶体管进一步包括源极区域210(N+)，其优选地位于抵靠层304。源极区域210例如比漏极区域206更重地被N型掺杂。
当如上所述的晶体管处于导通状态时，沟道区域202中的位于抵靠层304的垂直传导沟道将源极区域210连接到漏极区域206。晶体管的沟道长度因此对应于沟道区域202的厚度。选择沟道区域202和源极区域210的注入能量来获得期望的沟道长度。作为示例，区域202的厚度在从150nm到800nm的范围内。
在二极管10中，晶体管T1的栅极区域302、源极区域210和接触区域204优选地电连接到阳极端子A。这使得晶体管能够限定二极管10。为了实现这一点，作为示例，传导层40覆盖衬底20和沟槽22。层40例如由铝、铝-铜或铝-硅-铜制成。层40可以布置在传导界面层42上。区域302在沟槽中从层40或可能的界面层42延伸。层42例如旨在便于在层40和区域302、204、210以及可能的区域306之间形成电接触件(下面的图2A至图2F的方法)。层42可以由硅化物制成或者可以是例如由钛制成的金属层。层42可以备选地包括硅化物层和金属层，金属层覆盖硅化物层并且例如由钛制成。硅化物因此形成电接触件，而金属层提供对层40的粘附。层42可以至少部分地通过自对准硅化工艺来获得，并且硅化物然后是不连续的并且不覆盖层304的上部部分。层42的厚度优选地小于300nm，例如小于100nm。
由于区域302和沟道区域202通过上述短距离d分离的事实，可以选择沟道区域202的掺杂水平以及区域302的掺杂类型和水平来获得二极管的饱和电流密度，其在25℃时例如在1nA/mm2和1mA/mm2之间。优选地，区域202的掺杂水平在2×1016和1018原子/cm3之间。为了获得该饱和电流密度，区域302是重N型掺杂的(例如大于5×1018原子/cm3)，或者更一般地通过与沟道区域202的传导类型相反的传导类型来被重掺杂。电流密度饱和度在此由以下来确定：a)测量由大于0.1V的直流电压偏置的二极管的电流密度-电压特性的两个点或更多点；以及然后b)获得电压的指数函数，其中该函数通过两个点或者在多于两个点的情况下则最靠近点。然后，饱和电流密度是指数函数针对零电压的值。在步骤a)期间，特性的每个点的电压值被测量，使得它基本上不包括例如在1mV内的、二极管的寄生接入电阻的电压降。每个点的电流密度对应于流过二极管的电流值除以俯视图中沟槽之间的表面积。在步骤b)中，优选地通过将电流密度的对数与指数函数的对数之间的差的平方和最小化来确定指数函数。
当二极管被反向偏置时，由区域306通过层308引起的静电影响使得能够限制沟道区域和漏极区域中的电场(即，相对于区域306和层308不在那里的情况下的电场，减小了该电场)。这限制了二极管中的漏电流。此外，这使得能够在漏极区域的给定掺杂水平下增加雪崩电压以及/或者在给定雪崩电压下增加漏极区域的掺杂水平。增加漏极区域的掺杂水平的优点在于，当该掺杂水平高时，二极管的电导率更大，并且当电流在正向方向上流动时，二极管中的电压降因此受到限制。
作为示例，漏极区域具有的掺杂水平在从3.1015到1017原子/cm3的范围内。沟道区域具有的掺杂水平例如在从2.1016到1018原子/cm3的范围内。此外，沟槽被分离的距离例如在从0.5μm到3.0μm的范围内)。在沟道区域的较低水平下，沟槽穿透到衬底中向下至例如0.5μm和8μm之间的水平。
图2A至图2F图示了使用与图1的结构30相同的元件制造图1的结构30的变型的方法的实现方式的连续步骤。
在图2A的步骤中，将沟槽22蚀刻到衬底中。为了实现这一点，作为示例，衬底被覆盖有未示出的掩模层，掩膜层例如由氧化硅制成。例如通过光刻将开口形成到未来沟槽位置上方的掩模层中，之后对沟槽进行蚀刻。然后去除掩蔽层。
此后，例如通过沟槽壁的热氧化和/或通过沉积氧化硅层，共形地形成层308。层308覆盖沟槽壁。层308还可以覆盖沟槽外部的衬底20。层308的厚度小于沟槽宽度的一半，使得开口500保持在沟槽的中心处。
在图2B的步骤中，利用区域306的传导材料来填充开口500，例如直到衬底的上部水平或者直到接近衬底的上部水平的水平。为此目的，例如执行掺杂多晶硅的共形沉积。然后将多晶硅向下蚀刻至期望水平。由此获得区域306。
在图2C的步骤中，从未来区域302的上表面到下部水平蚀刻层308。作为示例，化学地执行蚀刻。因此，在区域306的任一侧上、在沟槽的上部部分中获得腔502。
在图2D的步骤中，形成层304。为此目的，作为示例，沟槽壁和区域306的在图2C的步骤中可以接近的部分被热氧化。由此形成在腔502的壁上的热氧化物层304可以在衬底和区域306的上表面上连续。
在图2E的步骤中，腔502被填充，例如直到衬底的上部水平或者直到接近衬底的上部水平的水平。为此目的，例如执行掺杂多晶硅的共形沉积。然后将多晶硅向下蚀刻至期望水平。因此在区域306的任一侧上获得两个区域302。
在图2F的步骤中，去除位于衬底以及区域302和306的上表面上的可能元件，诸如层304的可接近部分。然后形成可能的层42和层40。
通过图2A至图2F的方法获得的结构30的变型与图1的结构30的不同之处在于，区域306与区域302分离并且一直延伸到层40或可能的层42，并且该变型包括在区域306的任一侧上的两个区域302。每个区域302与层40电接触。每个区域302通过层304与衬底分离。
可以通过与图2A至图2F的方法类似的方法来获得结构30A，其中在图2B和图2C的步骤之间进一步提供方法来形成掩蔽层，该掩蔽层保护位于沟槽22的单侧上的壁上的层308，并且使得层308在沟槽的另一侧上被暴露。在图2C的步骤中获得单个腔502。
已描述了特定实施例。本领域技术人员将容易想到各种改变、修改和改进。特别地，结构30和30A及其变体可以被使用在利用衬底上的传导区域通过绝缘层的静电影响的任何电子部件(例如，晶体管)。此外，单个沟槽可以被提供有例如至少在一侧上的晶体管。
此外，在所描述的实施例中，晶体管的N和P传导类型、N和P沟道类型以及二极管的阴极和阳极可以同时反转。
上文已描述了具有各种变型的各种实施例。应当注意，本领域技术人员可以将这些各种实施例和变型的各种元件进行组合。
最后，基于上文给出的功能指示，所描述的实施例的实际实现在本领域技术人员的能力范围内。
根据以上详细描述，可以对实施例进行这些和其他改变。通常，在所附权利要求中，所使用的术语不应被解释为将权利要求限制于说明书和权利要求中公开的特定实施例，而是应被解释为包括权利要求所要求保护的所有可能的实施例以及这样的等同物的全部范围。因此，权利要求不受本公开的限制。

Claims (17)

1.一种二极管结构，其特征在于，包括：
衬底，具有沟槽；
第一传导区域，位于所述沟槽中并且与所述衬底分离第一距离，所述第一距离短于10nm；以及
第二传导区域，位于所述沟槽中并且比所述第一传导区域更深地延伸。
2.根据权利要求1所述的二极管结构，其特征在于，所述第二传导区域与所述衬底分离第二距离，所述第二距离大于所述第一距离。
3.根据权利要求1所述的二极管结构，其特征在于，进一步包括：
第一电介质层，将所述第一传导区域与所述衬底分离；以及
第二电介质层，将所述第二传导区域与所述衬底分离。
4.根据权利要求1所述的二极管结构，其特征在于，所述衬底是半导体。
5.根据权利要求4所述的二极管结构，其特征在于，包括覆盖所述衬底和所述沟槽的传导层，所述传导层电连接到所述衬底以及电连接到所述第一传导区域和所述第二传导区域。
6.根据权利要求5所述的二极管结构，其特征在于，所述传导层与所述衬底接触或者与所述衬底分离小于300nm。
7.一种二极管，其特征在于，包括：
衬底，具有第一沟槽；
阴极和阳极，耦合到所述衬底；
第一传导区域，位于所述沟槽中并且与所述衬底分离第一距离，所述第一距离短于10nm；以及
第二传导区域，位于所述沟槽中并且比所述第一传导区域更深地延伸。
8.根据权利要求7所述的二极管，其特征在于，所述衬底包括第二沟槽，所述二极管进一步包括：
至少一个晶体管，具有在所述第一沟槽和所述第二沟槽之间延伸的至少一个沟道区域，所述第一传导区域限定所述至少一个晶体管的栅极。
9.根据权利要求8所述的二极管，其特征在于，包括：
传导层，覆盖所述衬底以及所述第一沟槽和所述第二沟槽；以及
接触区域，形成在所述衬底中并且将所述沟道区域电连接到所述传导层。
10.根据权利要求8所述的二极管，其特征在于，所述第一传导区域和所述第二传导区域是半导体区域，所述沟道区域和所述第一传导区域掺杂有相反的导电类型。
11.根据权利要求8所述的二极管，其特征在于，包括漏极区域，所述漏极区域在所述沟道区域下方以及在所述第一沟槽和所述第二沟槽之间延伸。
12.根据权利要求11所述的二极管，其特征在于，所述漏极区域比所述沟道区域更少地被重掺杂。
13.根据权利要求11所述的二极管，其特征在于，所述漏极区域在所述第一沟槽和所述第二沟槽下方延伸。
14.一种二极管，其特征在于，包括：
半导体衬底；
阴极和阳极，耦合到所述衬底；
第一垂直晶体管，位于所述衬底中，所述第一垂直晶体管包括：电耦合到所述阳极的第一源极区域、垂直延伸到所述衬底中并且电耦合到所述阳极的第一栅极、电耦合到所述阴极的第一漏极区域、位于所述第一源极区域和所述第一漏极区域之间的第一沟道区域、以及在所述衬底中延伸并且位于所述第一栅极和所述第一沟道区域之间的第一栅极电介质。
15.根据权利要求14所述的二极管，其特征在于，所述栅极是
第一传导区域，所述第一传导区域与所述沟道区域分离第一距离，所述二极管进一步包括：
第二传导区域，比所述第一传导区域更深地延伸到所述衬底中并且与所述漏极区域分离第二距离，所述第二距离大于所述第一距离。
16.根据权利要求14所述的二极管，其特征在于，进一步包括：
第二垂直晶体管，位于所述衬底中，所述第二垂直晶体管包括：电耦合到所述阳极的第二源极区域、垂直延伸到所述衬底中并且电耦合到所述阳极的第二栅极、电耦合到所述阴极的第二漏极区域、位于所述第二源极区域和所述第二漏极区域之间的第二沟道区域、以及在所述衬底中延伸并且位于所述第二栅极和所述第二沟道区域之间的第二栅极电介质。
17.根据权利要求16所述的二极管，其特征在于，包括：
传导层，覆盖所述衬底以及所述第一垂直晶体管和所述第二垂直晶体管；以及
接触区域，形成在所述衬底中并且将所述第一沟道区域和所述第二沟道区域电连接到所述传导层。
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