CN210639963U - Signal reflection suppression circuit and display device - Google Patents
Signal reflection suppression circuit and display device Download PDFInfo
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- CN210639963U CN210639963U CN201922258392.2U CN201922258392U CN210639963U CN 210639963 U CN210639963 U CN 210639963U CN 201922258392 U CN201922258392 U CN 201922258392U CN 210639963 U CN210639963 U CN 210639963U
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Abstract
The embodiment of the utility model discloses suppress signal reflection circuit and display device, suppress signal reflection circuit and set up in display device, display device still includes source drive circuit, its characterized in that, suppress signal reflection circuit and include: the signal acquisition module receives eye pattern data of a high-speed signal and outputs a first conversion data signal according to the eye pattern data; a comparison detection module that outputs a data code signal according to the received first converted data signal; and the adjusting module adjusts the resistance-capacitance parameters between the data sending end of the signal source and the data receiving end of the source electrode driving circuit according to the received data code signal. The embodiment of the utility model provides a technical scheme has solved the display signal because the reflection produces the problem of distortion, is favorable to avoiding display device after lighting, and the phenomenon of image flaw appears easily in display device.
Description
Technical Field
The embodiment of the utility model provides a relate to and show technical field, especially relate to a restrain signal reflection circuit and display device.
Background
At present, a display device using a plurality of source driving circuit structures is prone to image distortion when the display device is turned on, and the display quality of the display device is affected. The reason for this problem is that the high-speed signal line in the display device is routed in a T-type or L-type manner, and the reflection of the signal reduces the impedance at the branch of the line, which results in impedance mismatch, so that the eye diagram of the display signal output from the source driver circuit to the pixel unit cannot meet the specification requirement, and the display effect of the display device is affected.
In the prior art, the source driving circuit is strictly tested in the production process, but the production time and the cost of the display device are increased, and the fine adjustment of the improvement effect of the display device in the later period is difficult due to the large number of display signals.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a restrain signal reflection circuit and display device to when realizing lighting display device, can adjust the distortion that shows the signal conveniently, make the signal eye diagram that shows the signal satisfy the specification requirement.
In a first aspect, an embodiment of the present invention provides a signal reflection suppressing circuit, the signal reflection suppressing circuit is disposed in a display device, the display device further includes a source driving circuit, the signal reflection suppressing circuit includes:
the signal acquisition module receives eye pattern data of a high-speed signal and outputs a first conversion data signal according to the eye pattern data;
a comparison detection module that outputs a data code signal according to the received first converted data signal;
and the adjusting module adjusts the resistance-capacitance parameters between the data sending end of the signal source and the data receiving end of the source electrode driving circuit according to the received data code signal.
Preferably, the adjusting module includes a plurality of adjusting branches, a first end of each adjusting branch is electrically connected to the corresponding data sending end, and a second end of each adjusting branch is electrically connected to the corresponding data receiving end.
Preferably, each of the adjustment branches comprises:
a first end of each resistor is electrically connected with the corresponding data transmitting end, and a second end of each resistor is electrically connected with the corresponding data receiving end;
and the first end of the capacitor is electrically connected with the second end of the resistor, and the second end of the capacitor is connected with a set signal.
Preferably, the circuit for suppressing signal reflection further includes a signal measurement module, a first measurement end of the signal measurement module is electrically connected to a first end of the corresponding terminal resistor, a second measurement end of the signal measurement module is electrically connected to a second end of the corresponding terminal resistor, and the signal measurement module outputs the eye pattern data to the signal acquisition module according to input signals of the first measurement end and the second measurement end.
Preferably, the signal measurement module comprises an oscilloscope.
Preferably, the signal acquisition module includes:
and the analog-to-digital converter receives the eye pattern data of the high-speed signal, converts the eye pattern data in the form of an analog signal into a first converted data signal in the form of a digital signal and outputs the first converted data signal.
Preferably, the contrast detection module includes:
an arithmetic circuit, a first input terminal of the arithmetic circuit receiving a reference data signal, a second input terminal of the arithmetic circuit receiving the first converted data signal, the arithmetic circuit outputting a difference signal according to the reference data signal and the first converted data signal;
and the detection circuit outputs a data code signal matched with the difference signal according to the mapping relation between the difference signal and the data code.
Preferably, the circuit for suppressing signal reflection further includes a storage module, the storage module is electrically connected to the comparison detection module and the adjustment module, respectively, and the storage module is configured to store the data code signal and output the data code to the adjustment module.
Preferably, the signal reflection suppressing circuit further includes a power supply module, and the power supply module is configured to provide a power supply signal.
In a second aspect, the embodiment of the present invention further provides a display device, including display device and the reflection of suppressed signals circuit, the non-display area of display device is provided with source drive circuit, source drive circuit be used for to the pixel unit in display device display area provides data signal, the reflection of suppressed signals circuit with source drive circuit electricity is connected, the reflection of suppressed signals circuit is according to received the data sending end of eye pattern data adjustment signal source with resistance capacitance parameter between source drive circuit's the data receiving terminal.
The embodiment of the utility model provides a technical scheme, through the eye pattern data of the display signal of signal acquisition module collection display device, and according to the received eye pattern data output first conversion data signal, contrast detection module according to first conversion data signal output data code signal, the resistance capacitance parameter between signal source drive circuit is adjusted according to received data code signal to adjusting module, through the adjustment to resistance capacitance parameter, ensure that the display signal can not distort, therefore, compared with the prior art, the utility model provides a restrain signal reflection circuit when lighting up the display device automatically adjust the resistance mismatch capacitance parameter between signal source and source drive circuit, make the signal eye pattern of display signal satisfy the specification requirement, solved the problem that the display signal distorts because of impedance, be favorable to avoiding the display device after lighting up, the display device is prone to image defects.
Drawings
Fig. 1 is a block diagram of a circuit for suppressing signal reflection according to an embodiment of the present invention;
fig. 2 is a block diagram of another circuit for suppressing signal reflection according to an embodiment of the present invention;
fig. 3 is a block diagram of another circuit for suppressing signal reflection according to an embodiment of the present invention;
fig. 4 is a block diagram of another circuit for suppressing signal reflection according to an embodiment of the present invention;
fig. 5 is a waveform diagram of a display signal according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a block diagram of a circuit for suppressing signal reflection according to an embodiment of the present invention, the circuit for suppressing signal reflection is disposed in a display device, the display device further includes a source driving circuit, as shown in fig. 1, the circuit for suppressing signal reflection 100 includes:
the signal acquisition module 10 is used for receiving the eye pattern data SECD of the high-speed signal and outputting a first conversion data signal SDS according to the eye pattern data SECD by the signal acquisition module 10;
the comparison detection module 20, the comparison detection module 20 outputs a data CODE signal CODE according to the received first converted data signal SDS;
the adjusting module 30, the adjusting module 30 adjusts a resistance-capacitance parameter between the data transmitting end a of the signal source 300 and the data receiving end B of the source driving circuit 200 according to the received data CODE signal CODE, that is, an adjusting module parameter.
Specifically, the circuit 100 for suppressing signal reflection is disposed in the display device and electrically connected to the source driving circuit 200. When the display device is turned on, the signal acquisition module 10 receives eye diagram data SECD of a high-speed signal at a data receiving end of the source driving circuit 200, where the high-speed signal may be a display signal for driving the source driving circuit 200 to turn on the display device, the comparison detection module 20 receives a first converted data signal SDS output by the signal acquisition module 10 and compares the first converted data signal SDS with built-in standard data thereof, where the standard data built-in the comparison detection module 20 may be written in the module by a manufacturer with eye diagram information of a relevant model. The comparison detection module 20 outputs the matched data CODE signal CODE to the adjustment module 30 according to the first conversion data, and the adjustment module 30 adjusts the resistance-capacitance parameter between the data sending end a of the signal source 300 and the data receiving end B of the source driving circuit 200 according to the received data CODE signal CODE, so that the output impedance of the data sending end a of the signal source 300 is equal to the input impedance of the data receiving end B of the source driving circuit 200, thereby matching the impedance of the display signal between the signal source 300 and the source driving circuit 200, making the voltage and current of the display signal between the data sending end a of the signal source 300 and the data receiving end B of the source driving circuit 200 continuous, reducing the reflection of the display signal, suppressing the signal distortion caused by the reflection of the display signal, and making the eye diagram of the display signal meet the specification requirement.
The embodiment of the utility model provides a technical scheme, the eye pattern data SECD of display signal through signal acquisition module 10 collection display device, and according to the first conversion data signal SDS of received eye pattern data SECD output, contrast detection module 20 is according to first conversion data signal SDS output data CODE signal CODE, the resistance capacitance parameter between adjustment module according to received data CODE signal CODE adjustment signal source 300 and source drive circuit 200, through the adjustment to resistance capacitance parameter, make the output impedance of signal source 300's data sending end A equal with source drive circuit 200's data receiving end B's input impedance, ensure that the display signal can not take place the distortion. The embodiment of the utility model provides a through setting up suppression signal reflection circuit 100 in display device, adjust resistance value and capacitance value between signal source 300 and the source drive circuit 200 when lighting display device, make the signal eye diagram that shows the signal satisfy the specification requirement, solved because impedance mismatch leads to showing the problem of signal distortion. Therefore, compared with the prior art, the embodiment of the utility model provides an inhibit signal reflection circuit 100 has solved the display signal because the reflection produces the problem of distortion through the automatic adjustment resistance capacitance parameter, is favorable to avoiding display panel after lighting, and the phenomenon of image flaw appears easily in display device. In addition, the embodiment of the present invention provides a suppression signal reflection circuit 100 with high integration level, which is favorable for reducing the number of components, so as to save the space of the PCB board.
Further, fig. 2 is another kind of suppressing signal reflection circuit's that the embodiment of the utility model provides a block diagram, as shown in fig. 2, adjustment module 30 includes many adjustment branches 301, and each adjustment branch 301's first end 1 is connected with the data sending end a electricity that corresponds, and each adjustment branch 301's second end 2 is connected with the data receiving end B electricity that corresponds.
Specifically, the signal source 300 includes a plurality of data transmitting terminals a, the source driving circuit 200 includes a plurality of data receiving terminals B, the data transmitting terminals a correspond to the data receiving terminals B one by one, and each data transmitting terminal a is electrically connected to the corresponding data receiving terminal B through an adjusting branch 301. The data sending end a of the signal source 300 is electrically connected to the data receiving end B of the source driving circuit 200 through the separate adjusting branch 301, so that the display signals of the pixel units electrically connected to the source driving circuit 200 can be independently adjusted, and the adjusting branches 301 do not interfere with each other.
Further, on the basis of the above-described embodiment, with continued reference to fig. 2, each adjustment leg 301 includes:
the first end of the resistor is electrically connected with the corresponding data sending end A, and the second end of the resistor is electrically connected with the corresponding data receiving end B;
and the first end of the capacitor is electrically connected with the second end of the resistor, and the second end of the capacitor is connected with a set signal.
Specifically, each of the adjustment branches includes a resistor and a capacitor, and for convenience of description, the first adjustment branch 301 is connected to the first adjustment branchIs called a first resistor R1And a first capacitor C1The resistance and capacitance of the second adjusting branch 301 are referred to as a second resistance R2And a second capacitor C2… … and so on. The plurality of data senders A are respectively called a first data sender A1 and a second data sender A2 … … Nth data sender AN, and the plurality of data receivers B are respectively called a first data receiver B1 and a second data receiver B2 … … Nth data receiver BN. The first end 1 of the first adjusting branch 301 is electrically connected to the first data transmitting terminal a1 of the signal source 300, the second end 2 of the first adjusting branch 301 is electrically connected to the first data receiving terminal B1 of the source driving circuit 200 … …, and so on. The resistor and the capacitor can be connected in parallel, the second end of the capacitor is connected with a setting signal, and the setting signal can be a ground signal. The signal acquisition module 10 acquires eye pattern data SECD of different data receiving terminals B of the source driving circuit 200, respectively generates corresponding first conversion data signals SDS according to the eye pattern data SECD of each data receiving terminal B, outputs the first conversion data signals SDS to the comparison detection module 20 for operation, and after the comparison detection module 20 outputs corresponding data CODE signals CODE, the adjustment module 30 performs parameter adjustment on the resistance and capacitance of the corresponding adjustment branch 301 according to the received data CODE signals CODE, so that the display signal passing through each adjustment branch 301 is not distorted. The embodiment of the utility model provides a through setting up the adjustment branch road, be convenient for adjust the display signal of exporting to each pixel cell, be favorable to shortening the adjustment time.
Further, fig. 3 is a block diagram of another structure of the circuit for suppressing signal reflection according to the embodiment of the present invention, as shown in fig. 3, the circuit 100 for suppressing signal reflection further includes: a signal measurement module 40.
The first measurement terminal D1 of the signal measurement module 40 is electrically connected to the first terminal of the corresponding terminal resistor RT, the second measurement terminal D2 of the signal measurement module 40 is electrically connected to the second terminal of the corresponding terminal resistor RT, and the signal measurement module 40 outputs the eye diagram data SECD to the signal acquisition module 10 according to the input signals of the first measurement terminal D1 and the second measurement terminal D2.
Specifically, the signal measurement module 40 may be an external measurement module or an internal measurement module, for example, the external measurement module may be a measurement device such as an oscilloscope, and the internal measurement module may be a data measurement chip. The display signal received by the data receiving end of the source driving circuit is a differential signal, so that the differential signal on the two lines (not shown in fig. 3) needs to be sampled through the termination resistor RT. For example, if the signal measurement module 40 includes an oscilloscope, the differential signal can be measured by connecting a first measurement probe of the differential probe to the first end of the termination resistor RT and a second measurement probe to the second end of the termination resistor RT. After the oscilloscope is connected to the computer through the patch cord, the computer converts the waveform acquired by the oscilloscope into the eye pattern data SECD and transmits the eye pattern data SECD to the signal acquisition module 10.
Further, on the basis of the above embodiment, with continuing reference to fig. 3, the circuit 100 for suppressing signal reflection further includes a storage module 50, the storage module 50 is electrically connected to the comparison detection module 20 and the adjustment module 30, respectively, and the storage module 50 is configured to store the data CODE signal CODE and output the data CODE to the adjustment module 30.
Specifically, the storage module 50 is used for storing the optimal data codes, and when the display device is mass-produced, the adjustment of the resistance-capacitance parameters between the signal source 300 and the source driving circuit 200 can be realized only by reading the data codes stored in the storage module 50 through the adjustment module 30, so that the display signal output by the adjustment module 30 meets the requirements of the specification, and no distortion occurs. Therefore, the embodiment of the utility model provides a through the best data code among the direct reading storage module 50 can make things convenient for quick realization to the adjustment of resistance capacitance parameter, save adjustment time, be favorable to avoiding display device image distortion phenomenon.
Further, with continued reference to fig. 3, the suppressing signal reflecting circuit 100 further includes a power module 60, and the power module 60 is configured to provide a power signal.
Specifically, the power module 60 may be a DC/DC converter, and is configured to convert an external power voltage into a voltage required by the suppressed signal reflection circuit 100, so that each device inside the suppressed signal reflection circuit 100 can operate normally.
Further, fig. 4 is a block diagram of another structure of the circuit for suppressing signal reflection according to the embodiment of the present invention, as shown in fig. 4, the signal acquisition module 10 includes: the analog-to-digital converter 101, the analog-to-digital converter 101 receives the eye pattern data SECD of the high-speed signal and converts the eye pattern data SECD in the form of an analog signal into the first converted data signal SDS in the form of a digital signal and outputs the first converted data signal SDS.
Specifically, the signal measurement module 40 measures the analog differential signal at the data receiving end of the source driving circuit 200, but the signal received by the contrast detection module 20 is a digital signal, so the analog-to-digital converter 101 is disposed in the signal acquisition module 10 to convert the eye diagram data SECD in the form of an analog signal into the first converted data signal SDS in the form of a digital signal. Illustratively, the signal measurement module 40 is an oscilloscope, the oscilloscope measures the differential display signal on the terminal resistor RT through a differential probe, and displays the waveform of the differential display signal on the oscilloscope, the analog-to-digital converter 101 collects the waveform data on the oscilloscope, and converts the waveform data into a first converted data signal SDS in the form of a digital signal, and outputs the first converted data signal SDS to the comparison detection circuit 20, so as to facilitate the comparison detection circuit 20 to process the data information contained in the eye diagram data SECD. The first conversion data signal SDS includes first conversion data, and for example, the first conversion data may include an amplitude of the differential display signal, a time interval between two adjacent intersections, and the like.
Further, on the basis of the above-described embodiment, with continued reference to fig. 4, the contrast detection module 20 includes:
an arithmetic circuit 201, a first input terminal E1 of the arithmetic circuit 201 receives the reference data signal RS, a second input terminal E2 of the arithmetic circuit 201 receives the first converted data signal SDS, and the arithmetic circuit 201 outputs a difference signal DS according to the reference data signal RS and the first converted data signal;
the detection circuit 202 outputs a data CODE signal CODE matched with the difference signal DS according to the mapping relationship between the difference signal DS and the data CODE by the detection circuit 202.
Specifically, the reference data signal RS may be directly written into the contrast detection module 20, the operation circuit 201 may directly read the reference data signal RS, and the first converted data signal SDS is generated by the signal acquisition module 10. The arithmetic circuit 201 performs difference processing on the received reference data signal RS and the first converted data signal SDS to generate a difference signal DS, and outputs the difference signal DS to the detection circuit 202. The detection circuit 202 stores the mapping relationship between the relevant difference signal and the data CODE, and the detection circuit 202 compares and detects the received difference signal DS and the mapping relationship inside itself and outputs the data CODE signal CODE matched with the received difference signal DS. The adjusting module 30 adjusts the resistance-capacitance parameters of the relevant adjusting branch between the signal source 300 and the source driving circuit 200 according to the data CODE signal CODE output by the detecting circuit 202. And the detection circuit can also determine whether the adjustment module 30 needs to adjust the resistance-capacitance parameters on the corresponding adjustment branch according to the preset detection condition, and if the acquired eye diagram data meets the preset detection condition, the data code at this time is stored in the storage module 50, so that the subsequent adjustment module can directly read the corresponding data code, and the adjustment time can be shortened.
Specifically, fig. 5 is a waveform diagram of a display signal provided by an embodiment of the present invention, referring to fig. 4 and 5, a specific working principle of the suppression signal reflection circuit 100 provided by an embodiment of the present invention is as follows:
the power module 60 provides power signals for each device inside the signal reflection suppression circuit 100, the signal measurement module 40 measures eye diagram data of the data receiving end of the source driving circuit 200, and the signal acquisition module 10 converts the eye diagram data into first conversion data, where the first conversion data includes amplitudes Vn (Ta, Tb) and Vp (Ta, Tb) of display signals in a point a and a point b time periods. The comparison detection module 20 is provided with a preset detection condition, the operation circuit 201 in the comparison detection module 20 operates the reference value of the display signal and the first conversion data to obtain a difference value between the reference value and the first conversion data, and the detection circuit 202 compares the relationship between the difference value and the preset detection condition to determine whether the adjustment module 30 is required to adjust the resistance-capacitance parameters on the corresponding adjustment branch. The preset detection condition may be standard values corresponding to specification requirements, such as standard amplitudes Vp0 and Vn0 of the display signal, and time differences T10 at points a and b and time differences T20 at points c and d.
Illustratively, the preset detection condition is: | Vp0| ≧ 150mV, | Vn0| ≧ 150mV, T1 ═ 2.2ns, and T2 | -0.4 ns. The detection circuit 202 detects that Vn (Ta, Tb) and Vp (Ta, Tb) satisfy | Vn (Ta, Tb) | ≧ | Vn0|, and | Vp (Ta, Tb) | ≧ | Vp0|, when Vn (Ta, Tb) and Vp (Ta, Tb) satisfy the preset detection condition, the relationship between the difference Tb-Ta between the time of point b and the time of point a is detected, if Tb-Ta-T1 is equal to 0 or approaches 0, the time from point a to point b in the eye diagram data approaches 2.2ns, the adjustment module does not need to adjust the resistance-capacitance parameter, the acquisition module continues to acquire the amplitudes Vn (Tc, Td) and Vp (Tc, Td) of point c and point d, where Tc is (Tb-Ta)/2-TSW/2, Td is (Tb-Ta)/2+ w/2, TSW is the time from point a to point c or the time from point b to point d, and detects the time (Tc, tsn) and the TSW is detected, td) and Vp (Tc, Td) meet a preset detection condition, if | Vn (Tc, Td) | ≧ Vn0|, and | Vp (Tc, Td) | ≧ Vp0|, the detection is stopped and the current data code is recorded, the signal acquisition module continues to acquire Vn (Tc, Td), Vp (Tc, Td) and T2 under the current data code for multiple times, the comparison detection module 20 detects whether the acquired data all meet the preset detection condition, if Td-Tc-T2 is equal to 0 or approaches to 0, the current data code is taken as the optimal data code, the storage module 50 stores the current data code, so that when the resistance-capacitance parameters are subsequently adjusted, the adjustment module 30 can directly read the optimal data code.
If the detection circuit 202 detects that Vn (Ta, Tb) and Vp (Ta, Tb) do not satisfy the preset detection condition, the comparison detection module outputs the current data code according to the mapping relationship between the difference and the data code, and records the current data code, and the data code is not adopted in the subsequent adjustment process. And adding 1 to the data code to form a new data code, outputting the new data code to the adjusting module 30, adjusting the resistance-capacitance parameters by the adjusting module 30 according to the new data code, and performing acquisition and detection again until the acquired eye diagram data meets the preset detection condition.
The embodiment of the utility model provides a through setting up suppression signal reflection circuit 100 in display device, adjust resistance value and capacitance value between signal source 300 and the source drive circuit 200 when lighting display device, make the signal eye diagram that shows the signal satisfy the specification requirement, solved because impedance mismatch leads to showing the problem of signal distortion. The embodiment of the present invention provides a technical solution, the signal acquisition module 10 acquires the eye pattern data of the display signal of the display device, and outputs the first converted data signal according to the received eye pattern data, the contrast detection module 20 outputs the data code signal according to the first converted data signal, the adjustment module adjusts the resistance-capacitance parameter between the signal source 300 and the source driving circuit 200 according to the received data code signal, and ensures that the display signal is not distorted by adjusting the resistance-capacitance parameter, therefore, compared with the prior art, the signal reflection suppressing circuit 100 provided by the embodiment of the present invention automatically adjusts the resistance-capacitance parameter, so that the output impedance of the data transmitting end of the signal source 300 is equal to the input impedance of the data receiving end of the source driving circuit 200, thereby matching the impedance of the display signal between the signal source 300 and the source driving circuit 200, the voltage and the current of the display signal between the data sending end of the signal source 300 and the data receiving end of the source electrode driving circuit 200 are continuous, the reflection of the display signal is reduced, the signal distortion caused by the reflection of the display signal is restrained, the eye diagram of the display signal meets the requirement of specification, the problem that the display signal is distorted due to reflection is solved, and the phenomenon that image flaws easily appear on a display device after a display panel is lightened is avoided. In addition, the embodiment of the present invention provides a suppressing signal reflection circuit 100, which can shorten the time for subsequent adjustment by directly reading the data code in the storage module 50, and the suppressing signal reflection circuit 100 has high integration level, which is favorable for reducing the number of components, so as to save the space of the PCB board.
Further, fig. 6 is the utility model provides a display device's schematic structure diagram, as shown in fig. 6, the embodiment of the utility model provides a display device is still provided, this display device for example can liquid crystal display device, and this display device specifically can be computer, panel computer, cell-phone, intelligent wearing equipment or information inquiry machine etc.. This display device includes the suppression signal reflection circuit that display device and above-mentioned embodiment provided, and display device's non-display area is provided with source drive circuit, and source drive circuit is used for providing data signal to the pixel cell in display device display area, and suppression signal reflection circuit is connected with source drive circuit electricity, and the resistance capacitance parameter between the data sending end of suppression signal reflection circuit according to received eye pattern data adjustment signal source and source drive circuit's the data receiving terminal, consequently the utility model discloses the display device who provides also possesses the beneficial effect that describes in above-mentioned embodiment, and it is no longer repeated here.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (10)
1. A signal reflection suppressing circuit provided in a display device, the display device further including a source driver circuit, the signal reflection suppressing circuit comprising:
the signal acquisition module receives eye pattern data of a high-speed signal and outputs a first conversion data signal according to the eye pattern data;
a comparison detection module that outputs a data code signal according to the received first converted data signal;
and the adjusting module adjusts the resistance-capacitance parameters between the data sending end of the signal source and the data receiving end of the source electrode driving circuit according to the received data code signal.
2. The circuit of claim 1, wherein the adjusting module comprises a plurality of adjusting branches, a first end of each of the adjusting branches is electrically connected to the corresponding data transmitting end, and a second end of each of the adjusting branches is electrically connected to the corresponding data receiving end.
3. The circuit for suppressing signal reflections according to claim 2, wherein each of said adjusting branches comprises:
a first end of each resistor is electrically connected with the corresponding data transmitting end, and a second end of each resistor is electrically connected with the corresponding data receiving end;
and the first end of the capacitor is electrically connected with the second end of the resistor, and the second end of the capacitor is connected with a set signal.
4. The circuit for suppressing signal reflections according to claim 1, further comprising:
the first measuring end of the signal measuring module is electrically connected with the first end of the corresponding terminal resistor, the second measuring end of the signal measuring module is electrically connected with the second end of the corresponding terminal resistor, and the signal measuring module outputs the eye pattern data to the signal acquisition module according to input signals of the first measuring end and the second measuring end.
5. The circuit of claim 4, wherein the signal measurement module comprises an oscilloscope.
6. The signal reflection suppression circuit of claim 1, wherein the signal acquisition module comprises:
and the analog-to-digital converter receives the eye pattern data of the high-speed signal, converts the eye pattern data in the form of an analog signal into a first converted data signal in the form of a digital signal and outputs the first converted data signal.
7. The signal reflection suppression circuit of claim 1, wherein the contrast detection module comprises:
an arithmetic circuit, a first input terminal of the arithmetic circuit receiving a reference data signal, a second input terminal of the arithmetic circuit receiving the first converted data signal, the arithmetic circuit outputting a difference signal according to the reference data signal and the first converted data signal;
and the detection circuit outputs a data code signal matched with the difference signal according to the mapping relation between the difference signal and the data code.
8. The circuit for suppressing signal reflections according to claim 1, further comprising:
the storage module is respectively electrically connected with the comparison detection module and the adjustment module, and is used for storing the data code signal and outputting the data code to the adjustment module.
9. The circuit of claim 1, further comprising a power module configured to provide a power signal.
10. A display device, comprising a display device and the reflection suppressing circuit according to any one of claims 1 to 9, wherein the source driving circuit is disposed in a non-display region of the display device, the source driving circuit is configured to provide data signals to pixel units in a display region of the display device, the reflection suppressing circuit is electrically connected to the source driving circuit, and the reflection suppressing circuit adjusts a resistance-capacitance parameter between a data transmitting end of a signal source and a data receiving end of the source driving circuit according to the received eye diagram data.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113092867A (en) * | 2021-03-29 | 2021-07-09 | 上海橙科微电子科技有限公司 | Method, system and medium for testing continuity of impedance of light module transmission system through square wave |
| CN115547248A (en) * | 2022-01-18 | 2022-12-30 | 荣耀终端有限公司 | Display driving chip, impedance matching method and terminal |
| CN117375551A (en) * | 2023-10-13 | 2024-01-09 | 苏州异格技术有限公司 | Frequency compensation system, method, device, equipment and medium for sharing IO pins |
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2019
- 2019-12-16 CN CN201922258392.2U patent/CN210639963U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113092867A (en) * | 2021-03-29 | 2021-07-09 | 上海橙科微电子科技有限公司 | Method, system and medium for testing continuity of impedance of light module transmission system through square wave |
| CN115547248A (en) * | 2022-01-18 | 2022-12-30 | 荣耀终端有限公司 | Display driving chip, impedance matching method and terminal |
| CN115547248B (en) * | 2022-01-18 | 2023-09-26 | 荣耀终端有限公司 | Display driving chip, impedance matching method and terminal |
| CN117375551A (en) * | 2023-10-13 | 2024-01-09 | 苏州异格技术有限公司 | Frequency compensation system, method, device, equipment and medium for sharing IO pins |
| CN117375551B (en) * | 2023-10-13 | 2024-04-26 | 苏州异格技术有限公司 | Frequency compensation system, method, device, equipment and medium for sharing IO pins |
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