CN115547248A

CN115547248A - Display driving chip, impedance matching method and terminal

Info

Publication number: CN115547248A
Application number: CN202210054618.0A
Authority: CN
Inventors: 董帅帅; 杨曦; 刘奕
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2022-12-30
Anticipated expiration: 2042-01-18
Also published as: CN115547248B

Abstract

The embodiment of the application provides a display driving chip, an impedance matching method and a terminal, relates to the technical field of communication, and can realize fine and continuous adjustment of resistance impedance of the terminal. The display driving chip comprises a signal receiving circuit, a timing controller, a source electrode driving circuit and a grid electrode driving circuit; the signal receiving circuit comprises a display signal receiving end and an impedance matching module; the impedance matching module comprises a switch signal receiving end and a switch tube, wherein the display signal receiving end is electrically connected with the wiring and used for receiving a display driving signal transmitted by the wiring; the switch signal receiving end sends the received switch signal to the control end of the switch tube, and adjusts the resistance value of the switch tube working in the linear region, so that the impedance of the display signal receiving end is matched with the impedance of the wiring; the display signal receiving end is also used for transmitting the display driving signal to the timing controller, so that the timing controller controls the source electrode driving circuit and the grid electrode driving circuit to send the display signal to the display screen according to the display driving signal.

Description

Display driving chip, impedance matching method and terminal

Technical Field

The present application relates to the field of communications technologies, and in particular, to a display driver chip, an impedance matching method, and a terminal.

Background

With the rapid development of terminal technology, terminals have become an essential tool in people's life, and bring great convenience to the life and work of users.

Be provided with a plurality of components and parts in the terminal, can carry out the transmission of signal between each components and parts to realize the corresponding function in terminal. The signals include high-speed signals. For example, the display driving signal sent by the processor of the terminal to the display driving chip is a high-speed signal. In order to prevent signal reflection caused by uneven impedance distribution of high-speed signals during transmission from influencing signal integrity, impedance matching is required to be carried out at a signal receiving end. However, the existing impedance matching scheme cannot realize the fine and continuous adjustment of impedance, and the impedance matching precision is influenced, so that the signal quality is influenced.

Disclosure of Invention

In order to solve the above technical problem, the present application provides a display driving chip, an impedance matching method and a terminal. The impedance of the terminal resistor can be finely and continuously adjusted, better impedance continuity is realized, and the signal quality is improved.

In a first aspect, an embodiment of the present application provides a display driving chip, including: the circuit comprises a signal receiving circuit, a timing controller, a source electrode driving circuit and a grid electrode driving circuit; the signal receiving circuit comprises a display signal receiving end and an impedance matching module; the impedance matching module comprises a switching signal receiving end and a switching tube, and the switching signal receiving end is electrically connected with the control end of the switching tube; wherein, the switch tube is a metal oxide semiconductor tube; the display signal receiving end, the switch tube and the timing controller are coupled; the timing controller is electrically connected with the source electrode driving circuit and the grid electrode driving circuit respectively; the display signal receiving end is also electrically connected with the wires and used for receiving display driving signals transmitted by the wires; the switch signal receiving end is used for sending the received switch signal to the control end of the switch tube so as to adjust the resistance value of the switch tube working in a linear region and change the impedance of the impedance matching module, so that the impedance of the display signal receiving end is matched with the impedance of the wiring; the display signal receiving end is also used for transmitting the display driving signal to the timing controller, so that the timing controller controls the source electrode driving circuit and the grid electrode driving circuit to send the display signal to the display screen according to the display driving signal.

The impedance matching module realizes continuous and fine adjustment of the impedance of the terminal resistor by utilizing the characteristic that the resistance of a switching tube (such as an MOS tube) is variable when the switching tube works in a linear region, and the effective matching of the impedance is completed. In addition, the impedance adjustment is completed by utilizing the characteristic that the resistance is variable when the switching tube works in a linear area, a plurality of resistors connected in parallel are not required to be arranged, the structure is simple, the occupied area is small, the occupied area of a signal receiving circuit is reduced, and the miniaturization design of a display driving chip is facilitated.

In some possible implementations, the display drive signals include single-ended signals; the signal receiving circuit comprises a display signal receiving end; the impedance matching module comprises a switch tube; the display signal receiving end, the timing controller and the first end of the switch tube are coupled; the second end of the switch tube is grounded. When the display driving signal is a single-ended signal, the impedance of the terminal resistor is continuously and finely adjusted by utilizing the characteristic that the resistor is variable when the switching tube works in a linear region, so that the effective matching of the impedance is completed, the impedance of the display driving signal is distributed more uniformly in the transmission process, the integrity of the signal is better, and the quality of the display driving signal is better.

In some possible implementations, the display drive signals include differential signals; the signal receiving circuit comprises two display signal receiving ends, and the two display signal receiving ends comprise a first display signal receiving end and a second display signal receiving end; the impedance matching module comprises two switching tubes; the impedance matching module also comprises an operational amplifier; the two switching tubes comprise a first switching tube and a second switching tube; the wires comprise a first differential wire and a second differential wire; the first display signal receiving end is electrically connected with the first differential wires, and the second display signal receiving end is electrically connected with the second differential wires; the first display signal receiving end, the non-inverting input end of the operational amplifier and the first end of the first switching tube are coupled to a first node; the second display signal receiving end, the inverting input end of the operational amplifier and the first end of the second switching tube are coupled to a second node; the second end of the first switch tube and the second end of the second switch tube are grounded; the output end of the operational amplifier is electrically connected with the timing controller. When the display driving signal is a differential signal, the same switch tube is arranged on the path corresponding to each differential wire, and the impedance of the terminal resistor is continuously and finely adjusted by utilizing the characteristic that the resistance of the switch tube is variable when the switch tube works in a linear region, so that the differential impedance of the first differential wire and the second differential wire is equal to the impedance of the display signal receiving end directly and electrically connected with the first differential wire and the second differential wire in size and same in phase. Therefore, the impedance distribution of the display driving signals in the transmission process is uniform, the signal integrity is good, and the quality of the display driving signals is good.

In some possible implementations, the differential signal includes a mobile industry processor interface differential signal based on the display driving signal including a differential signal; the signal receiving circuit includes a mobile industry processor interface. Of course, the display driving signals are not limited to the MIDI differential signals, and the signal receiving circuit is not limited to the MIDI.

In some possible implementations, the impedance matching module further includes a first resistor; a first resistor is arranged between the switch tube and the display signal receiving end. Since part of the impedance can be provided by the first resistor, the impedance provided by the first switch tube and the second switch tube can be reduced. When the impedance of the first switch tube and the second switch tube is small, the voltage value of the switch signal of the control end of the first switch tube and the second switch tube is large. Therefore, an MOS tube with smaller threshold voltage does not need to be selected, and the selection range of the MOS tube is expanded. In addition, when the voltage value of the switching signal is large, the ripple of the switching signal has a small influence on the impedance of the impedance matching module, so that the stability of the impedance matching module can be improved.

In some possible implementation manners, on the basis that the impedance matching module further includes a first resistor, when the display driving signal is a single-ended signal, an impedance value of the first resistor and the trace satisfy: 80% of Z ₀ ≤Z ₁ ≤100％Z ₀ Wherein Z is ₁ Is the impedance value of the first resistor, Z ₀ Is the impedance value of the trace; when the display driving signal is a differential signal, the wires comprise a first differential wire and a second differential wire, and the impedance value of the first resistor, the first differential wire and the second differential wire meet the following requirements: 80% of Z ₀ ≤Z ₁ ≤100％Z ₀ Wherein Z is ₁ Is the impedance value of the first resistor, Z ₀ The single-ended impedance values of the first differential wire and the second differential wire are obtained. The MOS transistor selection device has the advantages that the MOS transistor selection is not greatly limited due to the fact that the resistance value of the first resistor is too small, the stability of the impedance matching module is poor, and impedance matching cannot be performed due to the fact that the resistance value of the first resistor is too large.

In some possible implementations, the impedance matching module further includes a second resistor; one end of the second resistor is electrically connected with the first end of the switch tube, and the other end of the second resistor is electrically connected with the second end of the switch tube. The second resistor and the switch tube are arranged in parallel, the second resistor and the switch tube are connected in parallel, fine adjustment of an impedance value can be achieved, and meanwhile due to the fact that the sensitivity of the impedance matching module to voltage change of the control end of the switch tube is reduced, the impedance of the impedance matching module due to voltage change of the control end of the switch tube caused by noise and the like can be prevented from being greatly influenced.

In some possible implementation manners, the impedance matching module further includes a filtering unit for filtering interference of the interference signal to the display driving signal.

In some possible implementations, on the basis that the impedance matching module includes a filtering unit, the filtering unit includes a capacitor. The effect of filtering interference signals to display driving signals can be achieved through the capacitor, a complex circuit structure is not required to be arranged, the structure is simple, and cost is low.

In some possible implementation manners, the display driving chip further includes a control module, and the switch signal receiving end is electrically connected with the control module; the control module is used for sending a switching signal to the switching signal receiving end.

In some possible implementations, the switch signal receiving end is electrically connected to a processor of the terminal, and the processor is configured to send the switch signal to the switch signal receiving end. When the switch signal is provided by the existing processor in the terminal, a control module for providing the switch signal is not required to be independently arranged, so that the cost is reduced, and an area is not required to be independently reserved for the control module in the display driving chip, thereby being beneficial to the miniaturization design of the display driving chip.

In some possible implementation manners, the switch signal receiving end is electrically connected with a power management chip of the terminal, and the power management chip is used for sending the switch signal to the switch signal receiving end. When the switch signal is provided by the existing power management chip in the terminal, a control module for providing the switch signal is not required to be independently arranged, so that the cost is reduced, and an area for the control module is not required to be independently reserved in the display driving chip, thereby being beneficial to the miniaturization design of the display driving chip.

In a second aspect, an embodiment of the present application provides a terminal, including the display driver chip of the first aspect, which can achieve all effects of the display driver chip.

In a third aspect, an embodiment of the present application provides an impedance matching method, which is applied to the display driver chip according to the first aspect, and the impedance matching method includes: collecting a display driving signal at a display signal receiving end; generating a signal eye diagram based on the display drive signal; judging whether the comparison of the signal eye pattern and the standard eye pattern is in an error range; if the comparison of the signal eye pattern and the standard eye pattern is out of the error range, the switching signal output to the switching tube is adjusted, so that the comparison of the signal eye pattern and the standard eye pattern is within the error range.

Namely, whether the impedance of the wire and the display signal receiving end is matched is determined based on the eye pattern signal. Before the mobile phone leaves a factory, a switching signal is output to a control end of a switching tube through a detection device, then a display driving signal at a display signal receiving end is collected, an eye pattern signal is generated, the eye pattern signal is compared with a standard eye pattern stored in the eye pattern signal, whether the comparison between the signal eye pattern and the standard eye pattern is within an error range or not is judged, if the comparison between the signal eye pattern and the standard eye pattern is outside the error range, the switching signal output to the switching tube is adjusted until the comparison between the signal eye pattern and the standard eye pattern is within the error range, and the switching signal output to the control end of the switching tube by the detection device is determined at the moment. And writing the switching signal into a power management chip or a processor, and when the mobile phone leaves a factory, continuously providing the switching signal for the switching tube through the power management chip or the processor. The method is simple.

Of course, whether the impedance of the trace is matched with the impedance of the display signal receiving end can be determined by means of respectively collecting the impedance of the trace and the impedance of the impedance matching module.

Drawings

FIG. 1 is an output characteristic curve of an NMOS transistor;

fig. 2 is a schematic structural diagram of a terminal according to an embodiment of the present application;

fig. 3 is a schematic partial structural diagram of a terminal according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a display driver chip according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another display driver chip provided in the embodiment of the present application;

FIG. 6 is a schematic diagram of an impedance matching module;

fig. 7 is a schematic structural diagram of an impedance matching module according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another impedance matching module according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another impedance matching module according to an embodiment of the present application;

fig. 10 is a schematic view of an eye diagram provided in an embodiment of the present application;

fig. 11 is a schematic structural diagram of another impedance matching module according to an embodiment of the present disclosure;

FIG. 12 is a schematic view of yet another eye diagram provided in accordance with an embodiment of the present application;

FIG. 13 is a schematic diagram illustrating a structure of another display driver chip according to an embodiment of the present disclosure;

fig. 14 is a schematic partial structural diagram of a terminal according to an embodiment of the present application;

fig. 15 is a schematic partial structure diagram of another terminal according to an embodiment of the present application;

fig. 16 is a flowchart of an impedance matching method according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The terms "first" and "second," and the like, in the description and in the claims of the embodiments of the present application are used for distinguishing between different objects and not for describing a particular order of the objects. For example, the first target object and the second target object, etc. are specific sequences for distinguishing different target objects, rather than describing target objects.

In the embodiments of the present application, the words "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the description of the embodiments of the present application, the meaning of "a plurality" means two or more unless otherwise specified. For example, a plurality of processing units refers to two or more processing units; the plurality of systems refers to two or more systems.

For convenience of description, the following description is provided to describe the concept of the switching tube operating in the linear region and the saturation region according to the embodiments of the present application:

before the description, it should be noted that the switching tube according to the embodiment of the present application is a Metal Oxide Semiconductor (MOS) tube. When the switching tube is an MOS tube, the switching tube can be an NMOS tube or a PMOS tube. The following description takes the NMOS transistor as an example, and the embodiments of the present application all take the NMOS transistor as an example for explanation:

FIG. 1 is an output characteristic curve of an NMOS transistor, wherein a horizontal axis V _DS Is the drain-source voltage, ordinate I _D Is drain current, V _GS Is the gate-source voltage. Referring to fig. 1, the output characteristics of the mos transistor can be divided into three regions: a cut-off region (also a turn-off region), a constant current region (also a saturation region), and a variable resistance region (also a linear region). When V is _GS ＞V _th (threshold voltage of MOS transistor), I _D With V _DS The lifting of (2) will first show a linear increase and then tend to be gentle. The stage of linear growth is referred to as the variable resistance region. In this stage, the MOS transistor is equivalent to a resistor, and the resistance value is the inverse of the slope. As can be seen from FIG. 1, in the variable resistance region, V can be raised when the current is constant, for example, when the current is 3.5mA _GS So that I _D Equal to 3.5mA, with different V _DS And the slope follows V _GS Increased by increasing resistance with V _GS And is lifted and lowered. That is, in the variable resistance region, when V is _GS When different, the resistance of the resistor is different, namely the MOS tube in the area is equivalent to a MOS tube composed of V _GS The controlled variable resistance is that when the grid voltage of the MOS tube is adjusted, the MOS tube can be adjusted to be variableThe resistance value of the resistance region (also a linear region) is smaller when the gate voltage of the MOS transistor is larger.

For convenience of description, the following describes the concepts of impedance matching and high-speed signals related to the embodiments of the present application:

impedance matching: in order to prevent signal reflection caused by uneven impedance distribution of high-speed signals during transmission from affecting signal integrity, it is necessary that the internal resistance of a signal source is equal to the characteristic impedance of a connected transmission line in magnitude and phase, or the characteristic impedance of the transmission line is equal to the characteristic impedance of a connected load in magnitude and phase. The impedance matching according to the embodiment of the present application is that the characteristic impedance of the transmission line is equal to the magnitude and the same phase of the connected load impedance, that is, the impedance at the display signal receiving end in the trace connecting the processor and the signal receiving circuit directly electrically connected to the trace are equal to each other and the same phase.

High-speed signals: the time for a signal edge to rise from 10% to 90% is less than or equal to 4 to 6 times of the transmission delay of the signal on the trace, and the signal is called a high-speed signal.

The embodiment of the application provides a terminal, which can be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA for short), a vehicle-mounted computer, a television, an intelligent wearable device, an intelligent home device and the like, and the embodiment of the application does not specially limit the specific form of the terminal. For convenience of description, the following description will be given taking a mobile phone as an example of the terminal.

As shown in fig. 2, fig. 2 shows a schematic structural diagram of a mobile phone provided in this embodiment of the present application, where the mobile phone includes a processor 10, a display driver chip 20, a display screen 30, an external interface 40, a charging management module 50, a power management chip 60, a battery 70, and the like.

The external interface 40 may be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The external interface 40 may be used to connect a power adapter to charge a mobile phone, or may be used to transmit data between the mobile phone and a peripheral device.

The charging management module 50 may receive a charging input of the power adapter through the external interface 40. The charging management module 50 can also supply power to the processor 10, the display driving chip 20, the display screen 30 and other components in the mobile phone through the power management chip 60 while charging the battery 70.

The power management chip 60 is electrically connected to the battery 70. The power management chip 60 receives the input of the battery 142 and/or the charging management module 50, and supplies power to the processor 10, the display driver chip 20, the display screen 30, and the like.

Referring to fig. 3, the display driving chip 20 includes a signal receiving circuit 21, a timing controller 22, a source driving circuit 23, and a gate driving circuit 24. The signal receiving circuit 21 is electrically connected to the processor 10 through the wiring 80. The signal receiving circuit 21 is also electrically connected to the timing controller 22. The timing controller 22 is electrically connected to the source drive circuit 23 and the gate drive circuit 24, respectively.

The processor 10 sends the display driving signal to the signal receiving circuit 21 through the trace 80. The signal receiving circuit 21 sends the received display driving signal to the timing controller 22. The timing controller 22 controls the source driving circuit 23 and the gate driving circuit 24 to send display signals to the display panel 10 according to the display driving signals, so that the display panel 10 realizes color display. The Display screen 30 includes, for example, a Liquid Crystal Display (LCD) panel, an Organic Light Emitting Diode (OLED) Display panel, an LED Display panel, and the like, wherein the LED Display panel includes, for example, a Micro-LED Display panel, a Mini-LED Display panel, and the like. The embodiment of the present application does not limit the type of the display screen 30.

For the display driving signal, in some possible implementations, the display driving signal is a high-speed single-ended signal. When the display driving signal is a high-speed single-ended signal, referring to fig. 3 and 4, the signal receiving circuit 21 includes a display signal receiving terminal 211 and an impedance matching block 212. The display signal receiving end 211 is electrically connected to the trace 80 and the impedance matching module 212, respectively. The impedance matching module 212 is disposed such that the impedances at the trace 80 and the display signal receiving end 211 directly electrically connected to the trace 80 are equal in magnitude and same in phase. Therefore, the impedance distribution of the display driving signals in the transmission process is uniform, the signal integrity is good, and the quality of the display driving signals is good.

In some possible implementation manners, the display driving signal is a high-speed differential signal, which is, for example, a Mobile Industry Processor Interface (MIPI) differential signal, the Interface protocol of the Processor 10 and the display driving chip 20 is an MIPI protocol, and the signal receiving circuit 21 is an MIPI Interface.

When the display driving signal is a high-speed differential signal, the traces 80 include a first differential trace and a second differential trace (not shown in the figure) for transmitting the high-speed differential signal to the signal receiving circuit 21. Referring to fig. 5, the signal receiving circuit 21 includes a display signal receiving terminal 211, an impedance matching module 212, and an operational amplifier 213. The display signal receiving end 211 includes a first display signal receiving end 2111 and a second display signal receiving end 2112. The first display signal receiving terminal 2111 is electrically connected to the first differential trace, and the second display signal receiving terminal 2112 is electrically connected to the second differential trace. First display signal receiving terminal 2111 and non-inverting input terminal V of operational amplifier 213 _p And the impedance matching module 212 is coupled to the first node N1. The second display signal receiving terminal 2112 and the inverting input terminal V of the operational amplifier 213 _n And impedance matching module 212 is coupled to second node N2. The impedance matching module 212 is configured to enable the differential impedance of the first differential trace and the second differential trace to be equal to the impedance at the display signal receiving end 211 directly electrically connected to the first differential trace and the second differential trace (the sum of the impedance at the first display signal receiving end 2111 and the impedance at the second display signal receiving end 2112) and have the same phase. Therefore, the impedance distribution of the display driving signals in the transmission process is uniform, the signal integrity is good, and the quality of the display driving signals is good.

It should be noted that, in the above example, the differential signal is only an MIPI differential signal, the interface protocol of the processor 10 and the display driver chip 20 is an MIPI protocol, and the signal receiving circuit 21 is an MIPI interface, which is not limited to this application. The interface protocol of the processor 10 and the display driver chip 20 may also be other high-speed serial interface protocols. For example, the USB3.0 protocol, the Embedded Display Port (EDP) protocol, and the like may be used. In the following embodiments, it is also assumed that the display driving signal is a high-speed differential signal, the interface protocol of the display driving chip 20 of the processor 10 is the MIPI protocol, and the signal receiving circuit 21 is the MIPI interface, which is not described again in the following examples.

It is considered that although the design requires that the impedances at the trace 80 and the MIPI interface directly electrically connected to the trace 80 are equal in magnitude and in phase. However, in the actual manufacturing process, due to the influence of process and design, the impedance of the trace 80 may fluctuate somewhat, and therefore the impedance at the MIPI interface is also required to be adjusted within a certain range, so as to achieve the effect of matching with the impedance of the trace, and alleviate the signal quality problem caused by signal reflection. Illustratively, the MIPI protocol requires that the impedance of the trace 80 is 80-120 Ω, for example, the impedance of the trace 80 is 100 Ω. When the impedance (designed value) of the trace 80 is 100 Ω, the impedance at the MIPI interface to which the trace 80 is directly electrically connected should also be 100 Ω at the time of design. However, due to the influence of the process and design, the actual impedance of the prepared trace 80 is 110 Ω. At this time, the impedance at the MIPI interface also needs to be adjusted to 110 Ω, so as to achieve the effect of impedance matching with the routing 80, and alleviate the signal quality problem caused by signal reflection.

Based on this, fig. 6 is a schematic structural diagram of an impedance matching module, and referring to fig. 6, the impedance matching module 212 includes a first resistor group 2121 and a second resistor group 2122 arranged in parallel on two differential lines (corresponding to the first differential line and the second differential line). Each of the first resistor group 2121 and the second resistor group 2122 includes four switch units K1 and resistors R0 connected in parallel. The first resistor group 2121 and the second resistor group 2122 change the number of the parallel resistors R0 by adjusting the on state of the switching unit K1, thereby achieving the adjustment of the impedance.

It should be noted that, since the two differential lines transmit differential signals, the devices on the paths corresponding to the first differential line and the second differential line are required to be the same and symmetrically arranged. That is, the number of resistors and the resistance of the resistors of the first resistor group 2121 and the second resistor group 2122 are required to be identical. When the first resistor group 2121 and the second resistor group 2122 change the number of the parallel resistors R0 by adjusting the on-state of the switch unit K1 to realize the impedance adjustment, the number of the switch units K1 turned on by each resistor group is the same, and the positions are the same.

However, this scheme can only achieve impedance adjustment of a limited number of gears, and cannot achieve impedance matching well, so that impedances at the trace 80 and the display signal receiving end 211 directly electrically connected to the trace 80 cannot be equal, that is, effective impedance matching cannot be performed in some cases.

Illustratively, when the four switch units K1 in the first resistor group 2121 and the four switch units K1 in the second resistor group 2122 are all turned on, one differential impedance value, i.e., Z, is corresponded _{0 total} ＝2*[1/(1/Z ₀₁ +1/Z ₀₂ +1/Z ₀₃ +1/Z ₀₄ ) Wherein, Z ₀₁ Is the resistance value of one of the resistors R0, Z ₀₂ Is the impedance value of a further resistor R0, Z ₀₃ Is the impedance value of a further resistor R0, Z ₀₄ Is the impedance value of yet another resistor R0, Z _{0 total} To show the impedance value at the signal receiving end 211.

When the three switch units K1 in the first resistor group 2121 and the three switch units K1 in the second resistor group 2122 are all turned on, four differential impedance values, i.e., Z _{0 total} ＝2*[1/(1/Z ₀₁ +1/Z ₀₂ +1/Z ₀₃ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₁ +1/Z ₀₂ +1/Z ₀₄ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₁ +1/Z ₀₃ +1/Z ₀₄ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₂ +1/Z ₀₃ +1/Z ₀₄ )。

When the two switch units K1 in the first resistor group 2121 and the two switch units K1 in the second resistor group 2122 are both turned on, six differential impedance values, i.e., Z _{0 total} ＝2*[1/(1/Z ₀₁ +1/Z ₀₂ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₁ +1/Z ₀₃ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₁ +1/Z ₀₄ ) (ii) a Or the like, or a combination thereof,Z _{0 total} ＝2*[1/(1/Z ₀₂ +1/Z ₀₃ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₂ +1/Z ₀₄ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₃ +1/Z ₀₄ )。

When one switch unit K1 in the first resistor group 2121 and one switch unit K1 in the second resistor group 2122 are both turned on, four differential impedance values, i.e., Z _{0 total} ＝2*[1/(1/Z ₀₁ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₂ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₃ ) (ii) a Or, Z _{0 total} ＝2*[1/(1/Z ₀₄ )。

That is to say, when four resistors R0 are provided for each resistor group, and the resistances of the four resistors R0 are different, adjustment of 15 gears, that is, 15 impedance values, is achieved at most. If the actual differential impedance of the trace 80 is different from 15 steps, impedance matching cannot be achieved. To realize adjustment of more gears, each resistor group needs to be connected with more resistors R0 in parallel, which results in a very large area occupied by the impedance adjusting module 212, and is not favorable for the miniaturization design of the display driving chip.

Therefore, the scheme of fig. 6 can only realize the impedance adjustment of a limited number of gears, the impedance adjustment cannot be refined and continuous, the impedance adjustment has great limitation, and effective impedance matching cannot be performed.

Based on this, the embodiment of the present application provides an impedance matching module, which utilizes the characteristic that the resistance of a switching tube (for example, a MOS tube) is variable when the switching tube operates in a linear region to achieve continuous and fine adjustment of impedance, thereby achieving effective matching of impedance. In addition, the impedance adjustment is completed by utilizing the characteristic that the resistance is variable when the switching tube works in a linear region, a plurality of resistors connected in parallel are not required to be arranged, the structure is simple, the occupied area is small, the occupied area of the signal receiving circuit 21 is reduced, and the miniaturization design of a display driving chip is facilitated.

The specific structure of the impedance matching module will be described in detail below with reference to the terminal.

As shown in fig. 7, the impedance matching module 212 includes a switching signal receiving terminal Con, a first switch tube 2123 and a second switch tube2124. The first switch tube 2123 and the second switch tube 2124 are MOS tubes. The first switch tube 2123 and the second switch tube 2124 each include a first terminal, a second terminal, and a control terminal (i.e., a gate of the MOS transistor). A first end of the first switch tube 2123, a first display signal receiving end 2111, and a non-inverting input end V of the operational amplifier 213 _p Coupled to the first node N1. A first terminal of the second switch tube 2124, a second display signal receiving terminal 2112, and an inverting input terminal V of the operational amplifier 213 _n Coupled to a second node N2. The second end of the first switch tube 2123 and the second end of the second switch tube 2124 are grounded. The control end of the first switch tube 2123 and the control end of the second switch tube 2124 are both electrically connected to the switch signal receiving end Con. The switching signal receiving terminal Con is configured to receive a switching signal, which can control the first switching tube 2123 and the second switching tube 2124 to operate at a node of the linear region.

It can be understood that, since the two differential lines transmit differential signals, the MOS transistors on the paths corresponding to the first differential line and the second differential line are required to have the same structure. And the control terminals of the first switch tube 2123 and the second switch tube 2124 receive the same switching signal and the resistance values of the first switch tube 2123 and the second switch tube 2124 are the same.

When the switching signal changes, the first switching tube 2123 and the second switching tube 2124 operate at different nodes in the linear region. When the nodes of the linear region are different, the resistances of the first switch tube 2123 and the second switch tube 2124 are different, that is, when the voltage of the control terminal of the switch tube changes, the resistance of the switch tube in the linear region also changes, and the larger the voltage is, the smaller the resistance is. Thus, when different switching signals are applied to the control terminals of the first switch tube 2123 and the second switch tube 2124, the impedance of the impedance matching module 212 changes. With reference to fig. 1, when the first switch tube 2123 and the second switch tube 2124 work in the linear region, the curve of the linear region is continuous, so that the resistance of the first switch tube 2123 and the resistance of the second switch tube 2124 can be continuously changed by finely adjusting the switching signal, so that the impedance at the MIPI interface is matched with the impedance of the first differential trace and the second differential trace.

Illustratively, the MIPI protocol requires that the differential impedance of the first differential trace and the second differential trace be 100 Ω. In consideration of actual manufacturing, the differential impedance of the first differential trace and the second differential trace may have some deviation, for example, may be greater than 100 Ω, or less than 100 Ω. Therefore, the first switch 2123 and the second switch 2124 may be selected to have a resistance value between 45 and 55 when the variable resistance region is operated. After the preparation is completed, the actual differential impedance of the first differential trace and the second differential trace is, for example, 102 Ω. By adjusting the switching signal of the switching signal receiving terminal Con, the differential impedance of the impedance matching module 212 is 102 Ω (the impedances of the first switch tube 2123 and the second switch tube 2124 are both 51 Ω), which is consistent with the differential impedance of the first differential trace and the second differential trace, and thus signal reflection is eliminated. The continuous change of the impedance is realized by finely regulating and controlling the switching signal.

It can be understood that the MOS transistors with different types have different corresponding impedance variation ranges. The skilled person can select the type according to the actual situation. For example, when the impedance at the MIPI interface needs a larger adjustment range, an MOS transistor with a wider resistance value variation range may be selected. When the impedance at the MIPI interface needs a smaller adjusting range, an MOS tube with a small resistance value change range can be selected.

In addition, it is considered that some ac interference signals such as rf signals may interfere with the display driving signals. Therefore, with continued reference to fig. 7, a filtering unit 2125 is further disposed between the second ends of the first switch tube 2123 and the second switch tube 2124 and the ground. The filtering unit 2125 filters ac interference signals such as radio frequency signals in the terminal, and further improves signal quality.

As for the type of the filter unit 2125, the type of the filter unit 2125 is not limited in the embodiment of the present application as long as the effect of filtering is achieved. Illustratively, with continuing reference to fig. 7, the filtering unit 2125 may be, for example, a capacitor, wherein a first end of the capacitor is electrically connected to the second end of the first switch tube 2123 and the second end of the second switch tube 2124, respectively, and a second end of the capacitor is grounded.

As can be seen from the foregoing (FIG. 1), when the current is constant (e.g., is3.5 mA), V can be increased _GS So that I _D Equal to 3.5mA, with different V _DS And the slope (i.e. the inverse of the resistance) is dependent on V _GS The resistance value of the switch tube is increased along with V _GS And is lifted and lowered. That is to say, when the resistance value of the switching tube is large, the voltage value of the corresponding switching signal is small, and thus, an MOS tube with a small threshold voltage needs to be selected. However, MOS transistors with lower threshold voltages have higher requirements for process design. Therefore, there is a relatively large limitation in selecting MOS transistors. In order to enlarge the model selection range of the MOS tube. Referring to fig. 8, the impedance matching circuit 212 further includes two first resistors R1. One of the first resistors R1 is connected in series with the first switch tube 2123, and the other first resistor R1 is connected in series with the second switch tube 2124. Since most of the matched impedance is provided by the first resistor R1, only a small portion of the impedance is provided by the first switch 2123 and the second switch 2124. When the impedances of the first switch tube 2123 and the second switch tube 2124 are low, the voltage values of the switching signals at the control terminals of the first switch tube 2123 and the second switch tube 2124 are high. Therefore, an MOS tube with smaller threshold voltage does not need to be selected, and the selection range of the MOS tube is expanded. In addition, when the voltage value of the switching signal is large, the ripple of the switching signal has a small influence on the impedance of the impedance matching module 212, so that the stability of the impedance matching module 212 can be improved.

Illustratively, the MIPI protocol requires that the differential impedance of the first differential trace and the second differential trace be 100 Ω. In consideration of actual manufacturing, the differential impedance of the first differential trace and the second differential trace may have some deviation, for example, may be greater than 100 Ω, or, alternatively, less than 100 Ω. Therefore, one of the first resistors R1 and the first switch tube 2123 are connected in series on the first differential trace, and the other one of the first resistors R1 and the second switch tube 2124 are connected in series on the second differential trace, wherein the resistance value of the first resistor R1 is, for example, 40 Ω, and the first switch tube 2123 and the second switch tube 2124 having a resistance value between 5 Ω and 15 Ω are selected when the variable resistor region operates, so that the differential impedance actually obtained by the impedance matching module 212 is 90 Ω (40 Ω +40 Ω +5 Ω +5 Ω) to 110 Ω (40 Ω +40 Ω +15 Ω +15 Ω). After the first differential trace and the second differential trace are prepared, the actual differential impedance of the first differential trace and the second differential trace is, for example, 102 Ω. By adjusting the switch signal of the switch signal receiving terminal Con, the differential impedance of the impedance matching module 212 is 102 Ω (the impedance of the first resistor R1 is 40 Ω, and the impedances of the first switch tube 2123 and the second switch tube 2124 are both 11 Ω), which is consistent with the differential impedance of the first differential trace and the second differential trace, so that signal reflection can be eliminated. In addition, since the resistances provided by the first switch tube 2123 and the second switch tube 2124 are small and 11 Ω, and compared with the resistances provided by the first switch tube 2123 and the second switch tube 2124 which are both 51 Ω, the voltage values of the switching signals at the control ends of the first switch tube 2123 and the second switch tube 2124 are increased, for example, from 0.15V to 1.9V, so that it is not necessary to select the MOS transistor with small threshold voltage, and the selection range of the MOS transistor is expanded. In addition, the ripple of the switching signal has a small influence on the impedance of the impedance matching module 212, and the stability of the impedance matching module 212 is improved. .

Optionally, 80% Z ₀ ≤Z ₁ ≤100％Z ₀ Wherein Z is ₁ Is the impedance value of the first resistor R1, Z ₀ The single-ended impedance values of the first differential trace and the second differential trace are obtained. The reason for this is: after the manufacturing, the actual differential impedance values of the first differential trace and the second differential trace may be greater than the design value, and may also be smaller than the design value. If the resistance value of the selected first resistor R1 is exactly equal to the designed value of the single-ended impedance value of the first differential trace and the second differential trace. When the actual differential impedance value of the first differential trace and the second differential trace is smaller than the designed value due to process errors, the differential impedance (impedance value is 2R) of the impedance matching module 212 is obtained ₁ ) The impedance of the first differential trace and the second differential trace is necessarily greater than the differential impedance of the first differential trace and the second differential trace, that is, impedance matching cannot be performed. Therefore, the resistance value of the first resistor R1 needs to be smaller than the single-ended impedance value (design value) of the first differential trace and the second differential trace. In addition, considering that if the resistance of the first resistor R1 is too small, the resistors provided by the first switch tube 2123 and the second switch tube 2124 are required to be larger, and accordingly, the voltage value of the switch signal at the control terminal of the switch tube is smaller. Thus, the MOS transistor is selectedThe impedance matching module 212 has poor stability and is relatively limited. Therefore, the resistance value of the first resistor R1 selected in the embodiment of the present application is eighty percent to one hundred percent of the single-ended impedance value of the first differential trace and the second differential trace, so that the MOS transistor is not greatly limited when being selected because the resistance value of the first resistor R1 is too small, and the stability of the impedance matching module 212 is poor, and the impedance matching cannot be performed because the resistance value of the first resistor R1 is too large.

In addition, considering that the first switch tube 2123 and the second switch tube 2124 are active devices, capacitive reactance and inductive reactance introduced by the first switch tube and the second switch tube may affect the display driving signal. Thus, a simulation was made of the scheme shown in fig. 9, where the differential impedance of the first differential trace and the second differential trace is about 110 Ω.

The simulation result of the eye diagram is shown in fig. 10, wherein the abscissa in fig. 10 is time in ns, the ordinate is the voltage value of the display driving signal in mV, and Z represents the differential impedance of the impedance matching module 212. Referring to fig. 10, when the differential impedance Z =70 Ω of the impedance matching module 212, the high-speed signal has a reflection problem of the model, and the eye height is low, and as the differential impedance Z gradually increases, the signal reflection problem is gradually alleviated, and when Z =110 Ω, the MIPI interface impedance is well matched with the differential impedance of the first differential routing and the second differential routing, and at this time, the eye height is significantly increased and the signal is smooth, and there are no significant overshoot and back-hooking phenomena; however, as the differential impedance Z of the impedance matching module 212 is further improved, when the differential impedance Z of the impedance matching module 212 is greater than the differential impedance 110 Ω of the first differential trace and the second differential trace, the signal quality gradually deteriorates. When Z =150 Ω, the high and low levels are split into two levels, and the signal quality is poor. The above result shows that by adjusting the MOS transistor impedance, the differential impedance Z of the impedance matching module 212 is equal to the differential impedance Z of the first differential trace and the second differential trace, so as to achieve better impedance matching, improve the signal quality, and optimize the signal receiving capability of the display driver chip 20; meanwhile, the MOS tube is used as an active device, and the capacitance reactance and inductance reactance problems introduced by the MOS tube do not have obvious negative influence on the signal quality in the scheme.

In order to achieve finer adjustment of the differential impedance of the impedance matching module 212, the impedance matching circuit 212 further includes two second resistors R2, see fig. 11. One of the second resistors R2 is connected in parallel with the first switch tube 2123, and the other second resistor R2 is connected in parallel with the second switch tube 2124.

Since the resistance of the switching tube is reduced after the switching tube is connected in parallel with the second resistor R2, the switching tube needs to have a larger V to obtain the same resistance value as that when the second resistor R2 is not arranged _GS The change, correspondingly, the switch signal received by the control terminal needs to be changed more. For example, when the voltage at the control terminal of the switching tube changes by 1V, the resistance of the switching tube changes by 1 Ω. When the switch tube is connected in parallel with a second resistor R2, and the voltage of the control end of the switch tube changes by 5V, the impedance value can change by 1 omega only after the switch tube and the second resistor R2 are connected in parallel.

Thus, even if the voltage at the control end of the switching tube fluctuates due to some influences, the influence on the impedance is reduced compared with the situation that the second resistor R2 is not arranged; and can realize more meticulous regulation, for example, when the voltage of switch tube control end changed 1V originally, the resistance of switch tube changed 1 omega, and when the voltage of this scheme switch tube control end changed 1V, the impedance value can only change 0.2 omega after switch tube and second resistance R2 connect in parallel. That is to say, by connecting the second resistor R2 in parallel with the switch tube, it is possible to achieve finer adjustment of the impedance value, and at the same time, since the sensitivity of the impedance matching module 212 to the voltage change at the control end of the switch tube is reduced, it is possible to prevent the voltage change at the control end of the switch tube from having a larger influence on the impedance of the impedance matching module 212 due to noise and the like. Thus, the display driver chip 20 can more accurately analyze the differential signal transmitted from the processor 10 through the wire 80, thereby reducing the error probability of the MIPI protocol, improving the signal quality, and reducing the abnormal probability of the picture.

Furthermore, a simulation is performed on the scheme shown in fig. 11, in which the resistance of the first resistor R1 is 50 Ω, the resistance of the second resistor R2 is 10 Ω, the first switch 2123 and the second switch 2124 are MOS transistors, and the gate voltage of the MOS transistors is 2V, so that the resistances of the first switch 2123 and the second switch 2124 are 10 Ω, and at this time, the single-ended impedance of the impedance matching module 212 is 55 Ω, and the differential impedance is 110 Ω. The differential impedance of the first differential trace and the second differential trace is about 110 Ω. The simulation result of the eye diagram at the output of the operational amplifier 213 is shown in fig. 12.

Eye diagram simulation results show that the scheme shown in fig. 12 can also achieve better impedance matching, improve signal quality, and optimize the signal receiving capability of the display driver chip 20; meanwhile, the capacitance and the inductance of the MOS tube connected in the circuit in parallel still do not have obvious negative influence on the signal.

As can be seen from the foregoing, the switching signal receiving terminal Con is used for receiving a switching signal. The switching signal may be provided by a separate control module, i.e. the display driver chip 20 further comprises a control module 25, see fig. 13. The switch signal receiving terminal Con is electrically connected to the control module 25, and the control module 25 sends the switch signal to the control terminal of the switch tube through the switch signal receiving terminal Con, so that the differential impedance value of the impedance matching module 212 is equal to the differential impedance value of the first differential trace and the second differential trace, thereby completing the impedance matching.

Of course, the switching signal may also be provided by an existing structure within the handset, for example, see fig. 14, provided by the power management chip 60 described above. That is, the switch signal receiving terminal Con is electrically connected to the power management chip 60, and the power management chip 60 not only implements the corresponding power management function, but also needs to provide a switch signal to the switch signal receiving terminal Con. Alternatively, referring to fig. 15, the switching signal is provided by the processor 10. That is, the switching signal receiving terminal Con is electrically connected to the processor 10, and the processor 10 not only implements its corresponding functions (sending display driving signals, etc.), but also needs to provide a switching signal to the switching signal receiving terminal Con. When the switching signal is provided by the existing structure in the mobile phone, a control module for providing the switching signal is not required to be separately arranged, so that the cost is reduced, and a region for separately reserving the control module is not required in the display driving chip 20, thereby being beneficial to the miniaturization design of the display driving chip 20.

It should be noted that there are various methods for determining that the differential impedance of the first differential trace and the second differential trace matches with the impedance at the MIPI interface. The following description is presented in a possible manner and should not be taken as limiting the scope of the application.

The embodiments of the present application further provide an impedance matching method, which may be applied to the terminal in the present embodiment, for example, and have the same beneficial effects.

The impedance matching method will be described below with reference to the impedance matching block shown in fig. 11. As shown in fig. 16, the impedance matching method can be implemented by the following steps:

and S1601, collecting a display driving signal at a display signal receiving end.

Before the mobile phone leaves the factory, it is necessary to test whether the differential impedance of the first differential wire and the second differential wire in the mobile phone is matched with the impedance at the MIPI interface. The impedance mismatching between the differential impedance of the first differential routing and the second differential routing and the impedance at the MIPI interface caused by the fact that the actual differential impedance of the first differential routing and the second differential routing deviates from the design value due to process fluctuation and the like is prevented.

Illustratively, the design value of the differential impedance of the first differential trace and the second differential bus is 100 Ω. Correspondingly, the resistance of the first resistor R1 is 50 Ω, the resistance of the second resistor R2 is 10 Ω, the first switch 2123 and the second switch 2124 are in saturation conduction, and at this time, the impedance value of the impedance matching module 212 is 100 Ω, which is the same as the design value of the differential impedance of the first differential trace and the second differential bus. Then, the processor 10 sends a display driving signal to the display driving chip 20 through the first differential wiring and the second differential wiring. The display driving signal sent by the processor 10 is a display driving signal (also referred to as a preset display driving signal) required by the display screen 30. However, due to process fluctuation and other reasons, there may be a situation that the actual differential impedance of the first differential trace and the second differential trace impedance deviates from the designed value, so that the actual differential impedance of the first differential trace and the second differential trace impedance is not matched with the impedance at the MIPI interface. Therefore, the display driving signal at the display signal receiving end of the MIPI can be collected and subjected to an eye diagram test to determine whether the quality of the display driving signal is in problem.

S1602, generating a signal eye pattern based on the display driving signal.

Eye diagram analysis is the core of signal integrity analysis for high speed interconnect systems. Accordingly, it is possible to determine whether or not there is a quality problem with the display drive signal based on the eye pattern of the display drive signal at the display signal receiving terminal.

For example, the display driving signal may be collected by a device such as an oscilloscope, and a signal eye diagram corresponding to the display driving signal may be generated based on the display driving signal.

S1603, judging whether the comparison between the signal eye diagram and the standard eye diagram is in an error range.

If the differential impedance of the impedances of the first differential trace and the second differential trace is not matched with the impedance (the impedance value after the two first resistors R1 are connected in series) of the impedance matching module 212 at the MIPI interface, there is a signal reflection problem, which is reflected in that there are problems that the eye height is not within a preset range, the eye width is not within a preset range, overshooting, ringing and the like on the eye diagram, that is, the signal eye diagram corresponding to the display driving signal is compared with the standard eye diagram outside the error range.

If the differential impedance of the impedances of the first differential routing and the second differential routing is matched with the impedance of the impedance matching module 212 at the MIPI interface, it is indicated that the signal quality is good, and there is no signal reflection problem, and there are no problems on the eye diagram, such as the eye height being out of the preset range, the eye width being out of the preset range, overshoot, ringing, etc., that is, the signal eye diagram corresponding to the display driving signal is compared with the standard eye diagram within an error range.

And S1604, if the comparison between the signal eye pattern and the standard eye pattern is out of the error range, adjusting the switching signals output to the first switching tube and the second switching tube so as to enable the signal eye pattern corresponding to the display driving signal to be within the error range.

If the signal eye diagram is compared with the standard eye diagram, and is outside the preset range, the impedance of the impedance matching module 212 at the MIPI interface needs to be adjusted, so that the differential impedance of the impedances of the first differential trace and the second differential trace matches with the impedance (the impedance value after the two first resistors R1 are connected in series) of the impedance matching module 212 at the MIPI interface. Thereby making the signal eye diagram within the error range (good signal quality) compared with the standard eye diagram.

Illustratively, the voltage of the switching signal is adjusted to 2V, for example, so that the first switch tube 2123 and the second switch tube 2124 change from a saturated conducting state to a linear region, and the resistance value when operating in the linear region is 10 Ω, where the single-ended impedance of the impedance matching module 212 is 55 Ω and the differential impedance is 110 Ω. If the comparison of the signal eye diagram and the standard eye diagram is within the error range at the moment, the signal quality is good. Accordingly, the differential impedance of the impedances of the first differential trace and the second differential trace matches the impedance (110 Ω) of the impedance matching module 212 at the MIPI interface.

Therefore, even if the differential impedance of the first differential trace and the second differential trace deviates from the design value due to process errors, when the subsequent mobile phone leaves the factory, the power management chip 60 or the processor 10 can continuously provide 2V voltage to the first switch tube 2123 and the second switch tube 2124, so as to ensure that the differential impedance of the first differential trace and the second differential trace is always in a matching state with the impedance of the impedance matching module 212 at the MIPI interface during the use of the mobile phone, prevent the reflection of signals, improve the integrity of signals, enable the display driving chip 20 to accurately analyze the differential signals transmitted by the processor 10 through the first differential trace and the second differential trace, reduce the probability of errors occurring in the MIPI protocol, improve the quality of signals, and reduce the abnormal probability of pictures.

It should be noted that, except for the MIPI interface, other scenarios that are applied to high-speed signals and require impedance matching can be continuously adjusted by using the scheme.

It should be noted that, in the embodiment of the present application, impedance matching is performed on impedances of various stages in the display driving signal path transmitted between the processor 10 and the display driving chip 20 as an example. Of course, the impedance matching module and the impedance matching method provided by the embodiment of the present application can be used in other situations in which impedance matching is required in a mobile phone. For example, when the image pickup signal that the processor drives the camera to realize the image pickup function is transmitted to the camera, the signal receiving circuit at the camera may be set as the impedance matching module in the embodiment of the present application and perform impedance matching by using the impedance matching method in the embodiment of the present application. For another example, when the processor drives the touch driving chip to implement the touch signal of the touch function and transmits the touch signal to the touch driving chip, the signal receiving circuit at the touch driving chip may be configured as the impedance matching module in the embodiment of the present application and perform impedance matching by using the impedance matching method in the embodiment of the present application.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display driver chip, comprising: the circuit comprises a signal receiving circuit, a timing controller, a source electrode driving circuit and a grid electrode driving circuit;

the signal receiving circuit comprises a display signal receiving end and an impedance matching module; the impedance matching module comprises a switching signal receiving end and a switching tube, and the switching signal receiving end is electrically connected with the control end of the switching tube; the switch tube is a metal oxide semiconductor tube;

the display signal receiving end, the switch tube and the timing controller are coupled; the timing controller is electrically connected with the source electrode driving circuit and the grid electrode driving circuit respectively;

the display signal receiving end is also electrically connected with the wires and used for receiving display driving signals transmitted by the wires;

the switch signal receiving end is used for sending the received switch signal to the control end of the switch tube so as to adjust the resistance value of the switch tube working in a linear region and change the impedance of the impedance matching module, so that the impedance of the display signal receiving end is matched with the impedance of the wiring;

the display signal receiving end is further used for transmitting the display driving signal to the timing controller, so that the timing controller controls the source electrode driving circuit and the grid electrode driving circuit to send the display signal to the display screen according to the display driving signal.

2. The display driver chip of claim 1, wherein the display driver signals comprise single-ended signals;

the signal receiving circuit comprises a display signal receiving end; the impedance matching module comprises a switch tube;

the display signal receiving end, the timing controller and the first end of the switch tube are coupled; the second end of the switch tube is grounded.

3. The display driver chip of claim 1, wherein the display driver signals comprise differential signals;

the signal receiving circuit comprises two display signal receiving ends, and the two display signal receiving ends comprise a first display signal receiving end and a second display signal receiving end;

the impedance matching module comprises two switching tubes; the impedance matching module further comprises an operational amplifier; the two switching tubes comprise a first switching tube and a second switching tube; the traces include a first differential trace and a second differential trace; the first display signal receiving end is electrically connected with the first differential wiring, and the second display signal receiving end is electrically connected with the second differential wiring;

the first display signal receiving end, the non-inverting input end of the operational amplifier and the first end of the first switch tube are coupled to a first node;

the second display signal receiving end, the inverting input end of the operational amplifier and the first end of the second switching tube are coupled to a second node;

the second end of the first switch tube and the second end of the second switch tube are grounded;

and the output end of the operational amplifier is electrically connected with the timing controller.

4. The display driver chip of claim 3, wherein the differential signal comprises a Moveindustry processor interface differential signal; the signal receiving circuit includes a mobile industry processor interface.

5. The display driver chip of claim 1, wherein the impedance matching module further comprises a first resistor;

the first resistor is arranged between the switch tube and the display signal receiving end.

6. The display driving chip according to claim 5, wherein when the display driving signal is a single-ended signal, the impedance value of the first resistor and the trace satisfy: 80% of Z ₀ ≤Z ₁ ≤100％Z ₀ Wherein Z is ₁ Is the impedance value of the first resistor, Z ₀ The impedance value of the routing is taken as the impedance value of the routing;

when the display driving signal is a differential signal, the wires include a first differential wire and a second differential wire, and the impedance value of the first resistor and the first differential wire and the second differential wire satisfy: 80% of Z ₀ ≤Z ₁ ≤100％Z ₀ Wherein, Z ₁ Is the impedance value of the first resistor, Z ₀ And the single-ended impedance values of the first differential routing and the second differential routing are obtained.

7. The display driver chip of claim 1, wherein the impedance matching module further comprises a second resistor;

one end of the second resistor is electrically connected with the first end of the switch tube, and the other end of the second resistor is electrically connected with the second end of the switch tube.

8. The display driver chip of claim 1, wherein the impedance matching module further comprises a filtering unit for filtering interference of an interference signal to the display driver signal.

9. The display driver chip of claim 8, wherein the filter unit comprises a capacitor.

10. The display driver chip according to claim 1, wherein the display driver chip further comprises a control module, and the switch signal receiving terminal is electrically connected to the control module;

the control module is used for sending the switching signal to the switching signal receiving end.

11. The display driver chip according to claim 1, wherein the switch signal receiving terminal is electrically connected to a processor of a terminal, and the processor is configured to send the switch signal to the switch signal receiving terminal.

12. The display driving chip according to claim 1, wherein the switching signal receiving terminal is electrically connected to a power management chip of a terminal, and the power management chip is configured to send the switching signal to the switching signal receiving terminal.

13. A terminal comprising the display driver chip of any one of claims 1-12.

14. An impedance matching method applied to the display driver chip according to any one of claims 1 to 12, the impedance matching method comprising:

collecting a display driving signal at a display signal receiving end;

generating a signal eye diagram based on the display drive signal;

judging whether the comparison of the signal eye pattern and the standard eye pattern is in an error range;

and if the comparison of the signal eye pattern and the standard eye pattern is out of the error range, adjusting the switching signal output to the switching tube so as to enable the comparison of the signal eye pattern and the standard eye pattern to be within the error range.