CN210609167U - Communication switching circuit and communication switching device - Google Patents
Communication switching circuit and communication switching device Download PDFInfo
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- CN210609167U CN210609167U CN201922190438.1U CN201922190438U CN210609167U CN 210609167 U CN210609167 U CN 210609167U CN 201922190438 U CN201922190438 U CN 201922190438U CN 210609167 U CN210609167 U CN 210609167U
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Abstract
The utility model belongs to the technical field of communication switching, a communication switching circuit and communication switching device are provided, the signal of the signal transmission end output of main control chip through the phase inverter unit carries out the opposition and handles, and control the output signal of trigger unit through the energy storage unit, make the transceiver chip all be in the transmitting state in the predetermined time quantum of initiating bit, and automatic switch over after predetermined time quantum is the receiving state, it needs software control or relies on the pull-up and pull-down resistance of bus to drive to have solved current communication switching circuit, there is the loaded down with trivial details problem of switching process.
Description
Technical Field
The present application relates to a communication switching circuit and a communication switching device.
Background
RS485 is a standard for defining electrical characteristics of a driver and a receiver in a balanced digital multipoint system, which is defined by the association of the telecommunication industry and the electronic industry alliance, and a digital communication network using the standard can effectively transmit signals under a long-distance condition and in an environment with large electronic noise, so that the standard can be widely applied to the related fields of industrial control, intelligent instruments and the like. The industrial control MCU generally has at least one UART interface, but in order to realize RS485 bus communication, a universal RS485 transceiver chip is needed to convert UART TTL level into RS485 level. In order to meet the requirement of half-duplex communication of a bus, a GPIO interface is usually additionally allocated to the MCU for RS485 transceiving control, when data needs to be transmitted to the bus, the DIR of the MCU must output a high level, and when data needs to be received, the DIR of the MCU needs to output a low level.
However, the conventional communication switching circuit needs software control or depends on a pull-up and pull-down resistor of a bus to drive, and has the problem of complicated switching process.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a communication switching circuit and a communication switching device, and aims to solve the problem that the existing communication switching circuit needs software control or is driven by a pull-up resistor and a pull-down resistor of a bus, and the switching process is complex.
In order to solve the above problem, the present application provides a communication switching circuit, which is respectively connected to a main control chip, a transceiver chip and a working power supply, and the communication switching circuit includes: the circuit comprises a first resistance unit, a second resistance unit, an inverter unit for performing inversion processing on an input signal, an energy storage unit for storing energy according to the input signal and a trigger unit for outputting a high-level signal when the stored energy of the input signal reaches a preset threshold voltage;
the signal receiving end of the main control chip and the signal output end of the transceiver chip are connected to the first end of the first resistance unit, and the second end of the first resistance unit is connected with the working power supply;
the signal transmitting end of the main control chip, the signal input end of the transceiver chip and the input end of the phase inverter unit are connected to the first end of the second resistance unit in a shared mode, and the second end of the second resistance unit is connected with the working power supply;
the output end of the phase inverter unit is connected with the first end of the energy storage unit, the second end of the energy storage unit is connected with the input end of the trigger unit, and the output end of the trigger unit is connected with the enabling signal end of the transceiver chip.
Optionally, the first resistance unit is formed by connecting a plurality of resistors in series or connecting a plurality of resistors in parallel.
Optionally, the second resistance unit is formed by connecting a plurality of resistors in series or connecting a plurality of resistors in parallel.
Optionally, the phase inverter unit includes a phase inverter, an input end of the phase inverter is connected to the signal transmitting end of the main control chip, and an output end of the phase inverter is connected to the energy storage unit.
Optionally, the energy storage unit includes a discharge resistor, an energy storage capacitor, and a first diode;
the first end of the discharge resistor and the anode of the first diode are connected to the output end of the phase inverter unit in a sharing mode, the second end of the discharge resistor, the cathode of the first diode and the first end of the energy storage capacitor are connected to the input end of the trigger unit in a sharing mode, and the second end of the energy storage capacitor is grounded.
Optionally, the energy storage capacitor is a variable capacitor.
Optionally, the trigger unit includes a schmitt trigger, an input end of the schmitt trigger is connected to the energy storage unit, and an output end of the schmitt trigger is connected to an enable signal end of the transceiver chip.
An embodiment of the present application further provides a communication switching apparatus, including:
a main control chip;
a transceiver chip;
a working power supply port; and
the communication switching circuit according to any one of the above claims, wherein the communication switching circuit is connected to the main control chip, the transceiver chip and the working power port respectively.
Optionally, the transceiver chip is an RS485 transceiver chip.
The utility model provides a communication switching circuit and communication auto-change over device, carry out the opposition through the signal of phase inverter unit to the signal transmission end output of main control chip and handle, and control the output signal of trigger unit through the energy storage unit, make the transceiver chip all be in the transmitting state in the predetermined time quantum of initiating bit, and automatic switch over after predetermined time quantum is the receiving state, solved current communication switching circuit and needed software control or relied on the bus pull-up and pull-down resistance to drive, there is the loaded down with trivial details problem of switching process.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a communication switching circuit according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a communication switching circuit according to another embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.
In order to explain the technical solutions of the present application, the following detailed descriptions are made with reference to specific drawings and examples.
The present application will now be described in detail with reference to the drawings and specific examples.
In order to solve the above problem, an embodiment of the present application provides a communication switching circuit, which is respectively connected to a main control chip 11, a transceiver chip 12, and an operating power supply 13, wherein the communication switching circuit includes: the circuit comprises a first resistance unit 21, a second resistance unit 22, an inverter unit 23 for performing inversion processing on an input signal, an energy storage unit 24 for storing energy according to the input signal, and a trigger unit 25 for outputting a high-level signal when the stored energy of the input signal reaches a preset threshold voltage; specifically, a signal receiving end of the main control chip 11 and a signal output end of the transceiver chip 12 are commonly connected to a first end of the first resistance unit 21, and a second end of the first resistance unit 21 is connected to the working power supply 13; the signal transmitting end of the main control chip 11, the signal input end of the transceiver chip 12, and the input end of the inverter unit 23 are commonly connected to the first end of the second resistance unit 22, and the second end of the second resistance unit 22 is connected to the working power supply 13; the output end of the phase inverter unit 23 is connected to the first end of the energy storage unit 24, the second end of the energy storage unit 24 is connected to the input end of the trigger unit 25, and the output end of the trigger unit 25 is connected to the enable signal end of the transceiver chip 12.
In this embodiment, the signal transmitting terminal of the main control chip 11 is connected to the signal receiving terminal of the transceiver chip 12, the signal receiving terminal of the main control chip 11 is connected to the signal transmitting terminal of the transceiver chip 12, when the main control chip 11 needs to transmit data to the bus, according to the data format of UART, a low level start bit signal is transmitted through the signal transmitting terminal of the main control chip 11, the low level start bit signal is processed by the inverter unit 23 and outputs a short-duration high level signal, the high level signal charges and stores energy in the energy storage unit 24, the energy storage unit 24 provides a capacitance level signal to the trigger unit 25, the capacitance level signal enables the trigger unit 25 to generate a high level signal when the capacitance level signal is greater than a preset threshold voltage, the enable signal terminal of the transceiver chip 12 receives the high level signal to enable the transceiver chip 12 to be in a transmitting state, thereby transmitting data to the bus through the transceiver chip 12. If the signals output by the signal transmitting terminal of the main control chip 11 are all high level signals in a preset time period after the low level start bit signal, the high level signals are subjected to phase inversion processing by the phase inverter unit 23 and then output low level signals, at this time, the energy storage unit 24 starts to discharge, as long as the capacitance level signal provided by the energy storage unit 24 in the preset time period is greater than a preset threshold voltage, the trigger unit 25 can generate a high level signal, and at this time, the transceiver chip 12 is still in a transmitting state. After the transmission is completed, the signal of the signal transmitting end of the main control chip 11 defaults to a high level for a long time period, and after a preset time period, the trigger unit 25 outputs a low level signal, and at this time, the transceiver chip 12 is automatically switched to a receiving state.
In one embodiment, the first resistance unit 21 is formed by connecting a plurality of resistors in series or connecting a plurality of resistors in parallel. In this embodiment, the first resistance unit 21 is disposed between the transmitting signal terminal of the main control chip 11 and the working power supply 13, and is used for providing an input impedance for a signal provided by the signal receiving terminal of the main control chip 11.
In one embodiment, referring to fig. 2, the first resistor unit 21 includes a first resistor R1, a first end of the first resistor R1 is connected to the transmission signal terminal RXD of the main control chip 11, and a second end of the first resistor R1 is connected to the operating power supply 13.
In one embodiment, the second resistance unit 22 is formed by a plurality of resistors connected in series or a plurality of resistors connected in parallel. In the present embodiment, the first resistance unit 21 is disposed between the signal receiving terminal of the main control chip 11 and the operating power supply 13.
In one embodiment, referring to fig. 2, the first resistor unit 21 includes a first resistor R1, a first end of the first resistor R1 is connected to the transmission signal terminal RXD of the main control chip 11, and a second end of the first resistor R1 is connected to the operating power supply 13.
In one embodiment, referring to fig. 2, the inverter unit 23 includes an inverter INV, an input end of the inverter INV is connected to the signal transmitting end of the main control chip 11, and an output end of the inverter INV is connected to the energy storage unit 24.
In this embodiment, the inverter may invert the input low-level signal to output a high-level signal, and invert the input high-level signal to output a low-level signal. The inverter chip used for the inverter INV may be 74 series, for example, 7404, 7406.
In one embodiment, referring to fig. 2, the energy storage unit includes a discharge resistor R0, an energy storage capacitor C0, and a first diode D1; a first end of the discharge resistor R0 and an anode of the first diode D1 are commonly connected to the output end of the inverter unit 23, a second end of the discharge resistor R0, a cathode of the first diode D1 and a first end of the energy storage capacitor C0 are commonly connected to the input end of the flip-flop unit 25, and a second end of the energy storage capacitor C0 is grounded.
In this embodiment, when the main control chip 11 needs to send data to the bus, according to the data format of the UART, the signal transmitting terminal TXD of the main control chip 11 transmits a low-level start bit signal, the low-level start bit signal is processed by the inverter unit 23 and then outputs a short-duration high-level signal, the high-level signal charges the energy storage capacitor C0 through the first diode D1 to store energy, the energy storage capacitor C0 provides a capacitor level signal to the trigger unit 25, the capacitor level signal enables the trigger unit 25 to generate a high-level signal when the capacitor level signal is greater than a preset threshold voltage, and the enable signal terminals (DE and RE) of the transceiver chip 12 receive the high-level signal to enable the transceiver chip 12 to be in a sending state, so as to send data to the bus through the transceiver chip 12. If the signals output by the signal transmitting terminal RXD of the main control chip 11 are all high level signals within a preset time period after the low level start bit signal, the high level signals are high level signalsThe level signal is inverted by the inverter unit 23 and then outputs a low level signal, for example, the preset time period is 10 bits (8Date bit +1Parity bit +1Stop bit), at this time, the energy storage capacitor C0 starts to discharge through the discharge resistor R0, as long as the capacitor level signal provided by the energy storage capacitor C0 in the 10bit time period is greater than the preset threshold voltage (V) of the capacitor level signal (V0)T-) The flip-flop unit 25 may be caused to generate a high signal while the transceiver chip 12 is still in a transmitting state. Specifically, by setting appropriate values of R0 and C0, the size of the preset time period can be determined, after the transmission is completed, the signal at the signal transmitting end of the main control chip 11 defaults to a high level for a long time period, and after the preset time period, the trigger unit 25 outputs a low level signal, and at this time, the transceiver chip 12 is automatically switched to the receiving state.
In one embodiment, the discharge resistor R0 may be an adjustable resistor, the energy storage capacitor C0 may be an adjustable capacitor, and a user may adjust the resistance value of the discharge resistor R0 and the capacitance value of the energy storage capacitor C0 to provide a capacitor level signal to the energy storage capacitor C0 greater than a predetermined threshold voltage (V)T-) Is adjusted.
In one embodiment, the energy storage capacitor C0 is a variable capacitor.
In one embodiment, the trigger unit 25 includes a schmitt trigger STR, an input terminal of which is connected to the energy storage unit 24, and an output terminal of which is connected to the enable signal terminals (RE and DE) of the transceiver chip 12.
In one embodiment, referring to fig. 2, the operating power supply 13 is connected to the power supply terminals of the main control chip 11 and the transceiver chip 12 respectively to supply power to the main control chip 11 and the transceiver chip 12, and the signal transmitting terminal TXD of the main control chip 11 is connected to the enable signal terminal of the transceiver chip 12 through the inverter unit 23, the energy storage unit 24, and the trigger unit 25. The enable signal terminal of the transceiver chip 12, as an enable control pin, can control the signal transmission state thereof, and when the signal of the enable signal terminal is at a low level, the transceiver chip is in a receiving state, and when the signal of the enable signal terminal is at a high level, the transceiver chip is in a transmitting state. Through the communication switching circuit in the embodiment, the bus output end a and the bus output end B of the transceiver chip 12 can completely synchronize data output by the signal transmitting end TXD of the main control chip 11, and the UART TTL level to the RS485 level of the main control chip 11 are converted through the transceiver chip 12, so that the communication switching circuit is suitable for multi-node bus communication, and the application range of the communication switching circuit is enlarged.
An embodiment of the present application further provides a communication switching apparatus, including: a main control chip; a transceiver chip; a working power supply port; and the communication switching circuit according to any one of the above embodiments, wherein the communication switching circuit is respectively connected with the main control chip, the transceiver chip and the working power port.
In one embodiment, the transceiver chip is an RS485 transceiver chip.
The utility model provides a communication switching circuit and communication auto-change over device, carry out the opposition through the signal of phase inverter unit to the signal transmission end output of main control chip and handle, and control the output signal of trigger unit through the energy storage unit, make the transceiver chip all be in the transmitting state in the predetermined time quantum of initiating bit, and automatic switch over after predetermined time quantum is the receiving state, solved current communication switching circuit and needed software control or relied on the bus pull-up and pull-down resistance to drive, there is the loaded down with trivial details problem of switching process.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (9)
1. A communication switching circuit is respectively connected with a main control chip, a transceiver chip and a working power supply, and is characterized by comprising: the circuit comprises a first resistance unit, a second resistance unit, an inverter unit for performing inversion processing on an input signal, an energy storage unit for storing energy according to the input signal and a trigger unit for outputting a high-level signal when the stored energy of the input signal reaches a preset threshold voltage;
the signal receiving end of the main control chip and the signal output end of the transceiver chip are connected to the first end of the first resistance unit, and the second end of the first resistance unit is connected with the working power supply;
the signal transmitting end of the main control chip, the signal input end of the transceiver chip and the input end of the phase inverter unit are connected to the first end of the second resistance unit in a shared mode, and the second end of the second resistance unit is connected with the working power supply;
the output end of the phase inverter unit is connected with the first end of the energy storage unit, the second end of the energy storage unit is connected with the input end of the trigger unit, and the output end of the trigger unit is connected with the enabling signal end of the transceiver chip.
2. The communication switching circuit according to claim 1, wherein the first resistance unit is formed by connecting a plurality of resistances in series or connecting a plurality of resistances in parallel.
3. The communication switching circuit according to claim 1, wherein the second resistance unit is formed by connecting a plurality of resistances in series or connecting a plurality of resistances in parallel.
4. The communication switching circuit according to claim 1, wherein the inverter unit includes an inverter, an input terminal of the inverter is connected to the signal transmitting terminal of the main control chip, and an output terminal of the inverter is connected to the energy storage unit.
5. The communication switching circuit of claim 1, wherein the energy storage unit comprises a discharge resistor, an energy storage capacitor, and a first diode;
the first end of the discharge resistor and the anode of the first diode are connected to the output end of the phase inverter unit in a sharing mode, the second end of the discharge resistor, the cathode of the first diode and the first end of the energy storage capacitor are connected to the input end of the trigger unit in a sharing mode, and the second end of the energy storage capacitor is grounded.
6. The communication switching circuit of claim 5, wherein the energy storage capacitance is a variable capacitor.
7. The communication switching circuit of claim 1, wherein the trigger unit comprises a schmitt trigger, an input of the schmitt trigger is connected to the energy storage unit, and an output of the schmitt trigger is connected to an enable signal terminal of the transceiver chip.
8. A communication switching apparatus, comprising:
a main control chip;
a transceiver chip;
a working power supply port; and
the communication switching circuit of any one of claims 1-7 connected to a master control chip, a transceiver chip, and an operational power port, respectively.
9. The communication switching apparatus of claim 8 wherein said transceiver chip is an RS485 transceiver chip.
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|---|---|---|---|
| CN201922190438.1U CN210609167U (en) | 2019-12-09 | 2019-12-09 | Communication switching circuit and communication switching device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922190438.1U CN210609167U (en) | 2019-12-09 | 2019-12-09 | Communication switching circuit and communication switching device |
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| CN210609167U true CN210609167U (en) | 2020-05-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112838972A (en) * | 2020-12-31 | 2021-05-25 | 广州航天海特系统工程有限公司 | Enabling control method, device and equipment based on RS-485 transceiver and storage medium |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112838972A (en) * | 2020-12-31 | 2021-05-25 | 广州航天海特系统工程有限公司 | Enabling control method, device and equipment based on RS-485 transceiver and storage medium |
| CN112838972B (en) * | 2020-12-31 | 2022-05-27 | 广州航天海特系统工程有限公司 | Enabling control method, device and equipment based on RS-485 transceiver and storage medium |
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Effective date of registration: 20231208 Address after: Room 601, 6th Floor, Building 13, No. 3 Jinghai Fifth Road, Beijing Economic and Technological Development Zone (Tongzhou), Tongzhou District, Beijing, 100176 Patentee after: Beijing Youbixuan Intelligent Robot Co.,Ltd. Address before: 518000 16th and 22nd Floors, C1 Building, Nanshan Zhiyuan, 1001 Xueyuan Avenue, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Youbixuan Technology Co.,Ltd. |