CN211349345U - Full-duplex communication circuit and full-duplex communication device - Google Patents
Full-duplex communication circuit and full-duplex communication device Download PDFInfo
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- CN211349345U CN211349345U CN201922354726.6U CN201922354726U CN211349345U CN 211349345 U CN211349345 U CN 211349345U CN 201922354726 U CN201922354726 U CN 201922354726U CN 211349345 U CN211349345 U CN 211349345U
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Abstract
The utility model belongs to the technical field of communication, a full duplex communication circuit and full duplex communication device are provided, through set up first transceiver module and second transceiver module between host system's signal output part and the signal input part of controlled module, set up third transceiver module and fourth transceiver module between host system's signal input part and the signal output part of controlled module, thereby set up two way 485 communication links between host system and controlled module, it can only adopt half duplex mode to have solved current general asynchronous transceiver transmitter to change RS485, can't realize the problem of simultaneous communication.
Description
Technical Field
The present application relates to communications technologies, and in particular, to a full duplex communication circuit and a full duplex communication apparatus.
Background
RS485 is a standard for defining electrical characteristics of a driver and a receiver in a balanced digital multipoint system, which is defined by the association of the telecommunication industry and the electronic industry alliance, and a digital communication network using the standard can effectively transmit signals under a long-distance condition and in an environment with large electronic noise, so that the standard can be widely applied to the related fields of industrial control, intelligent instruments and the like. RS485 adopts the balanced transmission and the differential receiving mode to realize communication: the transmitting end converts TTL level signals of the serial port into differential signals A and B for output, and the differential signals are restored into the TTL level signals at the receiving end after cable transmission. The transmission line usually uses twisted pair lines and is differential transmission, so that the transmission line has extremely strong common mode interference resistance, and has the advantages of long transmission distance and capability of realizing multipoint transmission.
However, the conventional Universal Asynchronous Receiver Transmitter (UART) to RS485 converter can only adopt a half-duplex mode, and cannot realize simultaneous communication.
SUMMERY OF THE UTILITY MODEL
An object of the application is to provide a full-duplex communication circuit and a full-duplex communication device, and aims to solve the problem that the existing universal asynchronous receiving and transmitting transmitter (RS 485) can only adopt a half-duplex mode and cannot realize simultaneous communication.
In order to solve the above problem, the present application provides a full duplex communication circuit, including: the system comprises a main control module, a first controlled module, a first transceiver module, a second transceiver module, a third transceiver module and a fourth transceiver module;
the first transceiver module and the third transceiver module are used for receiving logic level signals and converting the logic level signals into differential signals;
the signal input end of the first transceiver module is connected with the signal output end of the main control module, and the signal input end of the third transceiver module is connected with the signal output end of the first controlled module;
the second transceiver module and the fourth transceiver module are used for receiving differential signals and converting the differential signals into logic level signals;
the first signal input end of the second transceiver module is connected with the first signal output end of the first transceiver module, the second signal input end of the second transceiver module is connected with the second signal output end of the first transceiver module, the signal output end of the second transceiver module is connected with the signal input end of the first controlled module, the first signal input end of the fourth transceiver module is connected with the first signal output end of the third transceiver module, the second signal input end of the fourth transceiver module is connected with the second signal output end of the third transceiver module, and the signal output end of the fourth transceiver module is connected with the signal input end of the main control module.
Optionally, the full-duplex communication circuit further includes a plurality of controlled units, each controlled unit includes a second controlled module, and a second transceiver module and a third transceiver module corresponding to the second controlled module; wherein a first signal input end of the second transceiver module corresponding to the second controlled module is connected to a first signal output end of the first transceiver module, a second signal input end of the second transceiver module corresponding to the second controlled module is connected to a second signal output end of the first transceiver module, a signal output end of the second transceiver module corresponding to the second controlled module is connected to a signal input end of the second controlled module, a first signal input end of the fourth transceiver module is connected to a first signal output end of the third transceiver module corresponding to the second controlled module, a second signal input end of the fourth transceiver module is connected to a second signal output end of the third transceiver module corresponding to the second controlled module, and a signal output end of the fourth transceiver module is connected to a signal input end of the main control module, and the signal input end of a third transceiver module corresponding to the second controlled module is connected with the output end of the second controlled module.
Optionally, the first transceiver module includes: the transceiver comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor and a first transceiver chip;
the first end of the first resistor is connected with the signal output end of the main control module, the second end of the first resistor, the driver input end of the first transceiver chip and the first end of the third resistor are connected in common, the first end of the fourth resistor, the driver output enable end of the first transceiver chip and the receiver output enable end of the first transceiver chip are connected in common, the first end of the second resistor is connected with the receiver output end of the first transceiver chip, the second end of the second resistor, the second end of the third resistor and the second end of the fourth resistor are connected in common at the power supply end, the power supply end of the first transceiver chip, the first end of the first capacitor and the first end of the sixth resistor are connected in common at the power supply end, the second end of the first capacitor is connected to ground, and the first differential signal end of the first transceiver chip, The first end of the seventh resistor and the first end of the eighth resistor are commonly connected to the first input end of the second transceiver module, the second differential signal end of the first transceiver chip, the second end of the seventh resistor and the second end of the sixth resistor are commonly connected to the second input end of the second transceiver module, the grounding end of the first transceiver chip is grounded, and the second end of the eighth resistor is grounded.
Optionally, the model of the first transceiver chip is MAX 3485.
Optionally, the second transceiver module includes: a ninth resistor, a tenth resistor, an eleventh resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a second capacitor and a second transceiver chip;
a first differential signal terminal of the second transceiver chip, a first terminal of the fourteenth resistor, and a first terminal of the sixteenth resistor are commonly connected as a first input terminal of the second transceiver module, a second differential signal terminal of the second transceiver chip, a second terminal of the fourteenth resistor, and a first terminal of the fifteenth resistor are commonly connected as a second input terminal of the second transceiver module, a power supply of the second transceiver chip, a first terminal of the second capacitor, and a second terminal of the fifteenth resistor are commonly connected to a power supply terminal, a second terminal of the second capacitor is grounded, a ground terminal of the second transceiver chip is grounded, a driver output enable terminal of the second transceiver chip, a receiver output enable terminal of the second transceiver chip, and a first terminal of the thirteenth resistor are commonly connected, and a second terminal of the thirteenth resistor is grounded, the input end of the driver of the second transceiver chip is connected with the first end of the eleventh resistor, the output end of the receiver of the second transceiver chip and the first end of the tenth resistor are connected in common, the second end of the tenth resistor and the second end of the eleventh resistor are connected in common at the power supply end, and the second end of the ninth resistor is connected with the signal input end of the first controlled module.
Optionally, an interface conversion module is further disposed between the first transceiver module and the second transceiver module, and the first transceiver module and the second transceiver module perform signal transmission through the interface conversion module.
Optionally, the interface conversion module includes an interface seat, a first voltage stabilizing chip, and a second voltage stabilizing chip; the first end of the interface seat and the first end of the first voltage stabilizing chip are connected to a first signal output end of the first transceiver module, the second end of the interface seat and the second end of the first voltage stabilizing chip are connected to a second signal output end of the first transceiver module, and the third end of the first voltage stabilizing chip is grounded; the third end of the interface seat and the first end of the second voltage stabilizing chip are connected to the first signal input end of the second transceiver module in a shared mode, the fourth end of the interface seat and the second end of the second voltage stabilizing chip are connected to the second signal input end of the second transceiver module in a shared mode, and the third end of the second voltage stabilizing chip is grounded.
Optionally, the third transceiver module has a structure identical to that of the first transceiver module, and the fourth transceiver module has a structure identical to that of the second transceiver module.
Optionally, the first controlled module is a motor.
An embodiment of the present application further provides a full duplex communication apparatus, including the full duplex communication circuit described in any of the above.
The application provides a full duplex communication circuit and full duplex communication device, through set up first transceiver module and second transceiver module between host system's signal output part and the signal input part of controlled module, set up third transceiver module and fourth transceiver module between host system's signal input part and the signal output part of controlled module, thereby set up two way 485 communication links between host system and controlled module, it can only adopt half duplex mode to have solved current universal asynchronous transceiver transmitter to RS485, can't realize the problem of simultaneous communication.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a full-duplex communication circuit provided by an embodiment of the present application;
fig. 2 is a schematic structural diagram of a full-duplex communication circuit provided in another embodiment of the present application;
fig. 3 is a schematic circuit diagram of a first transceiver module according to an embodiment of the present application;
fig. 4 is a schematic circuit diagram of a second transceiver module according to an embodiment of the present application;
fig. 5 is a schematic circuit structure diagram of an interface conversion module according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.
In order to explain the technical solutions of the present application, the following detailed descriptions are made with reference to specific drawings and examples.
The present application will now be described in detail with reference to the drawings and specific examples.
Fig. 1 is a schematic structural diagram of a full-duplex communication circuit provided in an embodiment of the present application, and referring to fig. 1, the full-duplex communication circuit in the embodiment includes: the master control module 11, the first controlled module 12, the first transceiver module 21, the second transceiver module 22, the third transceiver module 23, and the fourth transceiver module 24, wherein the first transceiver module 21 and the third transceiver module 23 are configured to receive a logic level signal and convert the logic level signal into a differential signal; a signal input end of the first transceiver module 21 is connected with a signal output end of the main control module 11, and a signal input end of the third transceiver module 23 is connected with a signal output end of the first controlled module 12; the second transceiver module 22 and the fourth transceiver module 24 are configured to receive differential signals and convert the differential signals into logic level signals; the first signal input end of the second transceiver module 22 is connected to the first signal output end of the first transceiver module 21, the second signal input end of the second transceiver module 22 is connected to the second signal output end of the first transceiver module 21, the signal output end of the second transceiver module 22 is connected to the signal input end of the first controlled module 12, the first signal input end of the fourth transceiver module 24 is connected to the first signal output end of the third transceiver module 23, the second signal input end of the fourth transceiver module 24 is connected to the second signal output end of the third transceiver module 23, and the signal output end of the fourth transceiver module 24 is connected to the signal input end of the main control module 11.
In this embodiment, the first transceiver module 21 and the second transceiver module 22 form a first 485 communication link, the logic level signal output by the main control module 11 is sent to the first controlled module 12, the third transceiver module 23 and the fourth transceiver module 24 form a second 485 communication link, the logic level signal output by the first controlled module 12 is sent to the main control module 11, the first 485 communication link and the second 485 communication link can perform parallel bidirectional transmission, an asynchronous transceiving mechanism of UART is fully utilized, a phase-change full-duplex function is realized, and communication efficiency is greatly improved.
In one embodiment, referring to fig. 2, the full-duplex communication circuit in this embodiment further includes a plurality of controlled units 13, each of the controlled units 13 includes a second controlled module 131, and a second transceiver module 22 and a third transceiver module 23 corresponding to the second controlled module; a first signal input end of the second transceiver module 22 is connected to a first signal output end of the first transceiver module 21, a second signal input end of the second transceiver module 22 is connected to a second signal output end of the first transceiver module 21, a signal output end of the second transceiver module 22 is connected to a signal input end of the second controlled module 131, a first signal input end of the fourth transceiver module 24 is connected to a first signal output end of the third transceiver module 23, a second signal input end of the fourth transceiver module 24 is connected to a second signal output end of the third transceiver module 23, and a signal output end of the fourth transceiver module 24 is connected to a signal input end of the main control module 11.
In this embodiment, the first transceiver module 21 and the third transceiver module 23 are configured to receive a logic level signal and convert the logic level signal into a differential signal; the second transceiver module 22 and the fourth transceiver module 24 are configured to receive differential signals and convert the differential signals into logic level signals. The two output ports of the first transceiver module 21 correspond to the two input ports of the controlled unit 13 one to one, respectively, to output the differential signals into the controlled unit 13, and the two input ports of the fourth transceiver module 24 correspond to the two output ports of the controlled unit 13 one to one, respectively, to receive the differential signals output by the controlled unit 13. In this embodiment, by providing a plurality of controlled units 13 connected to the first transceiver module 21 and the fourth transceiver module 24, respectively, point-to-multipoint transmission can be achieved, and the same main control module 11 is used to control a plurality of controlled modules simultaneously.
In one embodiment, the first transceiver module 21 has the same circuit structure as the third transceiver module 23, and the fourth transceiver module 24 has the same circuit structure as the second transceiver module 22. Specifically, the principle of signal transmission between the third transceiver module 23 and the fourth transceiver module 24 is the same as the principle of signal transmission between the first transceiver module 21 and the second transceiver module 22.
In one embodiment, referring to fig. 3, the first transceiver module 21 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first capacitor C1 and a first transceiver chip U1; specifically, a first end of the first resistor R1 is connected to the signal output terminal RS _ TX of the main control module, a second end of the first resistor R1, the driver input terminal D1 of the first transceiver chip U1, and a first end of the third resistor R3 are connected in common, and a first end of the fourth resistor R4 and a driver output enable terminal of the first transceiver chip U1 are connected in common
And a stationA receiver output enable terminal DE of the first transceiver chip U1 is commonly connected, a first terminal of the second resistor R2 is commonly connected to a receiver output terminal RO of the first transceiver chip U1, a second terminal of the second resistor R2, a second terminal of the third resistor R3 and a second terminal of the fourth resistor R4 are commonly connected to a power supply terminal, a power terminal of the first transceiver chip U1, a first terminal of the first capacitor C1 and a first terminal of the sixth resistor R6 are commonly connected to a power supply terminal VCC, a second terminal of the first capacitor C1 is grounded, a first differential signal terminal a of the first transceiver chip U1, a first terminal of the seventh resistor R7 and a first terminal of the eighth resistor R8 are commonly connected to a first input terminal RS _ B + of the second transceiver module 22, a second differential signal terminal B of the first transceiver chip U1, a second terminal of the seventh resistor R7 and a first terminal of the sixth resistor R8 are commonly connected to a second terminal of the second transceiver module 22 The input terminal RS _ B-, the ground terminal GND of the first transceiver chip U1 is grounded, and the second terminal of the eighth resistor R8 is grounded.
In the present embodiment, the driver output enable terminal in the first transceiver chip U1 is enabled
And the receiver output enable terminal DE is pulled up to the power supply terminal through the fourth resistor R4, so that the first transceiver chip U1 receives the TTL logic level signals and converts the TTL logic level signals into corresponding differential signals. And output to the second transceiver module 22 through the first output terminal a and the second output terminal B.
In one embodiment, the first transceiver chip U1 has a model MAX 3485.
In one embodiment, the second transceiver module 22 comprises: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a second capacitor C2 and a second transceiver chip U2; a first differential signal terminal A of the second transceiver chip U2, a first terminal of the fourteenth resistor R14 and a first terminal of the sixteenth resistor R16A first output terminal RS _ a + commonly connected to the first transceiver module 21, a second differential signal terminal B of the second transceiver chip U2, a second terminal of the fourteenth resistor R14, and a first terminal of the fifteenth resistor R15 are commonly connected to a second output terminal RS _ a "of the first transceiver module 21, a power supply of the second transceiver chip U2, a first terminal of the second capacitor C2, and a second terminal of the fifteenth resistor R15 are commonly connected to a power supply terminal VCC, a second terminal of the second capacitor C2 is grounded, a ground terminal GND of the second transceiver chip U2 is grounded, and an enable terminal of a driver of the second transceiver chip U2 is enabled
The receiver output enable terminal DE of the second transceiver chip U2 and the first terminal of the thirteenth resistor R13 are connected in common, the second terminal of the thirteenth resistor R13 is grounded, the driver input terminal D1 of the second transceiver chip U2 is connected to the first terminal of the eleventh resistor R11, the receiver output terminal of the second transceiver chip U2, the first terminal of the ninth resistor R9 and the first terminal of the tenth resistor R10 are connected in common, the second terminal of the tenth resistor R10 and the second terminal of the eleventh resistor R11 are connected to the power supply terminal VCC in common, and the second terminal of the ninth resistor R9 is connected to the signal input terminal RS _ RX of the first controlled module 12.
In the present embodiment, the driver output enable terminal in the second transceiver chip U2 is enabled
And the receiver output enable terminal DE is pulled down to the ground through the thirteenth resistor R13, so that the second transceiver chip U2 converts the received differential signal into a TTL logic level signal and outputs the TTL logic level signal to the signal input terminal RS _ RX of the first controlled module 12.
In one embodiment, an interface conversion module is further disposed between the first transceiver module 21 and the second transceiver module 22, and the first transceiver module 21 and the second transceiver module 22 perform signal transmission through the interface conversion module.
In one embodiment, referring to fig. 2, the interface conversion module includes an interface socket J1, a first voltage stabilization chip D1, and a second voltage stabilization chip D2; wherein the first end of the interface socket J1 and the first end 1 of the first voltage-stabilizing chip D1 are connected to the first signal output end RS _ a + of the first transceiver module 21, the second end 2 of the interface socket J1 and the second end of the first voltage-stabilizing chip D1 are connected to the second signal output end RS _ a "of the first transceiver module 21, and the third end of the first voltage-stabilizing chip D1 is grounded; the third end 3 of the interface socket J1 and the first end of the second voltage-stabilizing chip D2 are commonly connected to the first signal input end RS _ B + of the second transceiver module 22, the fourth end 4 of the interface socket J1 and the second end of the second voltage-stabilizing chip D2 are commonly connected to the second signal input end RS _ B-of the second transceiver module 22, and the third end of the second voltage-stabilizing chip D2 is grounded.
In one embodiment, the first controlled module 12 is an electric motor.
An embodiment of the present application further provides a full duplex communication apparatus, including the full duplex communication circuit described in any of the above.
The application provides a full duplex communication circuit and full duplex communication device, through set up first transceiver module and second transceiver module between host system's signal output part and the signal input part of controlled module, set up third transceiver module and fourth transceiver module between host system's signal input part and the signal output part of controlled module, thereby set up two way 485 communication links between host system and controlled module, it can only adopt half duplex mode to have solved current universal asynchronous transceiver transmitter to RS485, can't realize the problem of simultaneous communication.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. A full-duplex communication circuit, comprising: the system comprises a main control module, a first controlled module, a first transceiver module, a second transceiver module, a third transceiver module and a fourth transceiver module;
the first transceiver module and the third transceiver module are used for receiving logic level signals and converting the logic level signals into differential signals;
the signal input end of the first transceiver module is connected with the signal output end of the main control module, and the signal input end of the third transceiver module is connected with the signal output end of the first controlled module;
the second transceiver module and the fourth transceiver module are used for receiving differential signals and converting the differential signals into logic level signals;
the first signal input end of the second transceiver module is connected with the first signal output end of the first transceiver module, the second signal input end of the second transceiver module is connected with the second signal output end of the first transceiver module, the signal output end of the second transceiver module is connected with the signal input end of the first controlled module, the first signal input end of the fourth transceiver module is connected with the first signal output end of the third transceiver module, the second signal input end of the fourth transceiver module is connected with the second signal output end of the third transceiver module, and the signal output end of the fourth transceiver module is connected with the signal input end of the main control module.
2. The full-duplex communications circuit according to claim 1, further comprising a plurality of controlled units, each controlled unit comprising a second controlled module and second and third transceiver modules corresponding to the second controlled module; wherein a first signal input end of the second transceiver module corresponding to the second controlled module is connected to a first signal output end of the first transceiver module, a second signal input end of the second transceiver module corresponding to the second controlled module is connected to a second signal output end of the first transceiver module, a signal output end of the second transceiver module corresponding to the second controlled module is connected to a signal input end of the second controlled module, a first signal input end of the fourth transceiver module is connected to a first signal output end of the third transceiver module corresponding to the second controlled module, a second signal input end of the fourth transceiver module is connected to a second signal output end of the third transceiver module corresponding to the second controlled module, and a signal output end of the fourth transceiver module is connected to a signal input end of the main control module, and the signal input end of a third transceiver module corresponding to the second controlled module is connected with the output end of the second controlled module.
3. The full-duplex communications circuit of claim 1, wherein the first transceiver module comprises: the transceiver comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first capacitor and a first transceiver chip;
the first end of the first resistor is connected with the signal output end of the main control module, the second end of the first resistor, the driver input end of the first transceiver chip and the first end of the third resistor are connected in common, the first end of the fourth resistor, the driver output enable end of the first transceiver chip and the receiver output enable end of the first transceiver chip are connected in common, the first end of the second resistor is connected with the receiver output end of the first transceiver chip, the second end of the second resistor, the second end of the third resistor and the second end of the fourth resistor are connected in common at the power supply end, the power supply end of the first transceiver chip, the first end of the first capacitor and the first end of the sixth resistor are connected in common at the power supply end, the second end of the first capacitor is connected to ground, and the first differential signal end of the first transceiver chip, The first end of the seventh resistor and the first end of the eighth resistor are commonly connected to the first input end of the second transceiver module, the second differential signal end of the first transceiver chip, the second end of the seventh resistor and the second end of the sixth resistor are commonly connected to the second input end of the second transceiver module, the grounding end of the first transceiver chip is grounded, and the second end of the eighth resistor is grounded.
4. The full-duplex communications circuit according to claim 3, wherein the first transceiver chip has a model of MAX 3485.
5. The full-duplex communications circuit according to claim 1, wherein the second transceiver module comprises: a ninth resistor, a tenth resistor, an eleventh resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a second capacitor and a second transceiver chip;
a first differential signal terminal of the second transceiver chip, a first terminal of the fourteenth resistor, and a first terminal of the sixteenth resistor are commonly connected to a first output terminal of the first transceiver module, a second differential signal terminal of the second transceiver chip, a second terminal of the fourteenth resistor, and a first terminal of the fifteenth resistor are commonly connected to a second output terminal of the first transceiver module, a power supply of the second transceiver chip, a first terminal of the second capacitor, and a second terminal of the fifteenth resistor are commonly connected to a power supply terminal, a second terminal of the second capacitor is grounded, a ground terminal of the second transceiver chip is grounded, a driver output enable terminal of the second transceiver chip, a receiver output enable terminal of the second transceiver chip, and a first terminal of the thirteenth resistor are commonly connected, and a second terminal of the thirteenth resistor is grounded, the driver input end of the second transceiver chip is connected with the first end of the eleventh resistor, the receiver output end of the second transceiver chip, the first end of the ninth resistor and the first end of the tenth resistor are connected in common, the second end of the tenth resistor and the second end of the eleventh resistor are connected in common at a power supply end, and the second end of the ninth resistor is connected with the first controlled module.
6. The full-duplex communication circuit according to claim 1, wherein an interface conversion module is further disposed between the first transceiver module and the second transceiver module, and the first transceiver module and the second transceiver module perform signal transmission through the interface conversion module.
7. The full-duplex communications circuit according to claim 6, wherein the interface conversion module includes an interface socket, a first voltage regulation chip, and a second voltage regulation chip; the first end of the interface seat and the first end of the first voltage stabilizing chip are connected to a first signal output end of the first transceiver module, the second end of the interface seat and the second end of the first voltage stabilizing chip are connected to a second signal output end of the first transceiver module, and the third end of the first voltage stabilizing chip is grounded; the third end of the interface seat and the first end of the second voltage stabilizing chip are connected to the first signal input end of the second transceiver module in a shared mode, the fourth end of the interface seat and the second end of the second voltage stabilizing chip are connected to the second signal input end of the second transceiver module in a shared mode, and the third end of the second voltage stabilizing chip is grounded.
8. The full-duplex communications circuit according to claim 1, wherein the third transceiver module has a structure that is the same as the first transceiver module, and wherein the fourth transceiver module has a structure that is the same as the second transceiver module.
9. The full-duplex communications circuit of claim 1, wherein the first controlled module is a motor.
10. A full duplex communication apparatus comprising the full duplex communication circuit of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201922354726.6U CN211349345U (en) | 2019-12-24 | 2019-12-24 | Full-duplex communication circuit and full-duplex communication device |
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| CN201922354726.6U CN211349345U (en) | 2019-12-24 | 2019-12-24 | Full-duplex communication circuit and full-duplex communication device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115296783A (en) * | 2022-08-08 | 2022-11-04 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115296783A (en) * | 2022-08-08 | 2022-11-04 | 慷智集成电路(上海)有限公司 | Full-duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
| CN115296783B (en) * | 2022-08-08 | 2023-07-21 | 慷智集成电路(上海)有限公司 | Full duplex transmitting and receiving circuit, deserializing circuit chip, electronic equipment and vehicle |
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