CN220754974U - 485 bidirectional communication sensor circuit based on cmos high-speed NOT gate - Google Patents
485 bidirectional communication sensor circuit based on cmos high-speed NOT gate Download PDFInfo
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Abstract
The utility model discloses a 485 bidirectional communication sensor circuit based on a cmos high-speed NOT gate, which comprises a data receiver, wherein a first junction box is electrically connected to the data receiver, a second junction box is electrically connected to the first junction box, a repeater A and a repeater B are arranged in the first junction box and the second junction box, the repeater A and the repeater B in the first junction box are electrically connected to the data receiver, the repeater A and the repeater B in the second junction box are electrically connected to the repeater B in the first junction box, and a first sensor and a second sensor are respectively electrically connected to the repeater A in the first junction box and the second junction box; the utility model adopts different components to form a low-capacitance communication circuit, designs at high speed and in a long distance, and scientifically matches impedance to ensure that the transmission line obtains maximum power, thereby effectively realizing the long-distance transmission of the information source without distortion.
Description
Technical Field
The utility model relates to the technical field of communication, in particular to a 485 bidirectional communication sensor circuit based on a cmos high-speed NOT gate.
Background
In an RS485 communication network, a 485 transceiver is typically used to convert the TTL level and the RS485 level. The serial port controller in the node is connected to the 485 transceiver using RX and TX signal lines, while the transceiver is connected to the network bus by differential lines. TTL signal transmission is generally used between the serial port controller and the transceiver, and differential signal transmission is used between the transceiver and the bus. When transmitting data, the TX signal of the port controller is converted into a differential signal by the transceiver and transmitted to the bus. When receiving data, the transceiver converts the differential signals on the bus into TTL numbers and transmits the TTL numbers to the serial port controller through RX bow pins.
Referring to the prior art with publication number CN105160795A, it discloses a fire detection communication circuit, including gas sensor circuit and singlechip control circuit, the output signal of gas sensor circuit is carried to singlechip control circuit through AD data conversion circuit, singlechip control circuit's output signal sends to RS485 communication interface circuit, when gas reaches certain concentration, after judging through singlechip control circuit, through RS485 communication interface output standard protocol signal, can connect various system hosts, have advantages such as compatible strong, with low costs, the practicality is strong. However, the above-mentioned technology still has some drawbacks, such as: in the process of debugging 485 buses, the problems that waveform quality is reduced, communication with a terminal fails and the like are found when a certain amount of sensors are mounted on the buses.
Disclosure of Invention
In view of the problems mentioned in the background art, it is an object of the present utility model to provide a cmos high speed not gate based 485 bi-directional communication sensor circuit to solve the problems mentioned in the background art.
The technical aim of the utility model is realized by the following technical scheme:
the utility model provides a 485 two-way communication sensor circuit based on high-speed NOT gate of cmos, includes the data receiver, electric connection has first terminal box on the data receiver, electric connection has the second terminal box on the first terminal box, first terminal box with the inside repeater A and the repeater B of all being equipped with of second terminal box, in the first terminal box repeater A with repeater B all with data receiver electric connection, in the second terminal box repeater A with repeater B in the first terminal box electric connection, first sensor and second sensor have respectively electric connection on the repeater A in the first terminal box with in the second terminal box.
By adopting the technical scheme, the low-capacitance communication circuit is formed by adopting different components, the high-speed long-distance design is realized, the transmission line obtains the maximum power through scientific impedance matching, the long-distance transmission of the information source is effectively realized without distortion, and the excellent lightning surge protection performance is realized, namely, the components are adopted to form the energy release circuit, so that the surge voltage is effectively released to the ground; and support multiple nodes, typically up to 32 nodes; the transmission distance is far, and the furthest communication distance can reach 1200 meters; the anti-interference capability is strong, and differential signals are transmitted; the connection is simple, and normal communication can be carried out only by two signal wires (A+ and B-); the junction boxes are connected in series through the T-shaped bus scheme, the use of multiple nodes is completed, the influence of signal waveforms is effectively reduced, the inverter structure is realized by adopting a high-speed NOT gate of a CMOS technology, and the control and adjustment of signals are effectively realized.
Preferably, the first junction box and the second junction box are used for forming an X channel for receiving data, the repeater B is used for forming a Y channel for outputting data information, and the repeater a is used for forming a Z channel for transmitting data information to the first sensor or the second sensor.
Through adopting above-mentioned technical scheme, through the setting of X passageway, Y passageway and Z passageway, realize separating the circuit of system, effectual reduction signal waveform influences fewly.
Preferably, the first junction box and the second junction box include four circuits, and the four circuits are respectively used for realizing communication transmission of an X channel, a Y channel and a Z channel.
Through adopting above-mentioned technical scheme, X passageway, Y passageway and Z passageway are connected through the circuit respectively, and X passageway is realized connecting Y passageway and Z passageway respectively, accomplishes control regulation, and effectual reduction signal waveform influences is little.
Preferably, each of the four circuits includes a nand gate and a transceiver, the nand gate adopts a SN74AHC1GU04SN74 chip, the transceiver adopts a MAX3485 chip, and the MAX3485 chip is a half-duplex low-power-consumption transceiver.
Through adopting above-mentioned technical scheme, realize controlling the regulation to the signal through the NAND gate, realize the inverter structure, realize receiving and sending the signal through the transceiver to half duplex can realize effectual communication and reduce the installation of device.
Preferably, the VCC pin of the SN74AHC1GU04SN74 chip is electrically connected to a 3.3V input power supply, and the YOUT pin of the SN74AHC1GU04SN74 chip in the four circuits is electrically connected to a grounded capacitor C1, a grounded capacitor C2, a grounded capacitor C3 and a grounded capacitor C4, respectively.
Through adopting above-mentioned technical scheme, realize supplying power to the system through input power to realize node safety protection through electric capacity C1, electric capacity C2, electric capacity C3 and electric capacity C4, and can realize letting out the thunderbolt electric current, improve the security.
Preferably, the AIN pin of the SN74AHC1GU04SN74 chip is electrically connected with the RO pin of the MAX3485 chip, and a resistor R1, a resistor R2, a resistor R3 and a resistor R4 are respectively and electrically connected between the AIN pin of the SN74AHC1GU04SN74 chip and the RO pin of the MAX3485 chip in the four circuits, and the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are respectively and electrically connected with an input power supply of 3.3V.
Through adopting above-mentioned technical scheme, realize controlling the regulation through SN74AHC1GU04SN74 chip inverter structure, then realize the signal and export and receive through MAX3485 chip, and resistance R1, resistance R2, resistance R3 and resistance R4 are pull-up resistance, realize controlling the on-state of MAX3485 chip.
Preferably, the VCC pin of the MAX3485 chip is electrically connected with a 3.3V input power supply, and the RE pin and the DE pin of the MAX3485 chip are electrically connected with each other, and the RE pin is used for implementing connection of the X channel and the Y channel, and connection of the X channel and the Z channel.
By adopting the technical scheme, the input power supply is used for realizing power supply operation, and realizing connection among the X channel, the Y channel and the Z channel, so as to complete communication processing.
Preferably, the a pin and the B pin of the MAX3485 chip are respectively electrically connected with a resistor, wherein the resistor on the a pin is electrically connected with a 3.3V input power supply, and the resistor on the B pin is electrically grounded.
By adopting the technical scheme, the resistors of buses on two sides of the MAX3485 chip are used for realizing the clamping control of the high level at the pin A and the low level at the pin B.
In summary, the utility model has the following advantages:
the utility model adopts different components to form a low-capacitance communication circuit, high-speed long-distance design and scientific impedance matching to ensure that the transmission line obtains maximum power, thereby effectively realizing the long-distance transmission of an information source without distortion and excellent lightning surge protection performance, namely adopting the components to form an energy release circuit and effectively releasing surge voltage to the ground; and support multiple nodes, typically up to 32 nodes; the transmission distance is far, and the furthest communication distance can reach 1200 meters; the anti-interference capability is strong, and differential signals are transmitted; the connection is simple, and normal communication can be carried out only by two signal wires (A+ and B-); the junction boxes are connected in series through the T-shaped bus scheme, the use of multiple nodes is completed, the influence of signal waveforms is effectively reduced, the inverter structure is realized by adopting a high-speed NOT gate of a CMOS technology, and the control and adjustment of signals are effectively realized.
Drawings
FIG. 1 is a schematic diagram of the system architecture of the present utility model;
fig. 2 is a schematic circuit configuration of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Examples
Referring to fig. 1-2, a 485 bidirectional communication sensor circuit based on a cmos high-speed NOT gate comprises a data receiver, wherein a first junction box is electrically connected to the data receiver, a second junction box is electrically connected to the first junction box, a relay a and a relay B are arranged inside the first junction box and the second junction box, the relay a and the relay B in the first junction box are electrically connected to the data receiver, the relay a and the relay B in the second junction box are electrically connected to the relay B in the first junction box, and a first sensor and a second sensor are respectively electrically connected to the relay a in the first junction box and the second junction box.
The utility model adopts different components to form a low-capacitance communication circuit, high-speed long-distance design and scientific impedance matching to ensure that the transmission line obtains maximum power, thereby effectively realizing the long-distance transmission of an information source without distortion and excellent lightning surge protection performance, namely adopting the components to form an energy release circuit and effectively releasing surge voltage to the ground; and support multiple nodes, typically up to 32 nodes; the transmission distance is far, and the furthest communication distance can reach 1200 meters; the anti-interference capability is strong, and differential signals are transmitted; the connection is simple, and normal communication can be carried out only by two signal wires (A+ and B-); the junction boxes are connected in series through the T-shaped bus scheme, the use of multiple nodes is completed, the influence of signal waveforms is effectively reduced, the inverter structure is realized by adopting a high-speed NOT gate of a CMOS technology, and the control and adjustment of signals are effectively realized.
Specifically, the data receiver is electrically connected with a first junction box, the first junction box is electrically connected with a second junction box, and the second junction box can be sequentially and electrically connected with the junction boxes, so that multiple nodes are supported, and 32 nodes are supported at maximum generally; the transmission distance is far, the furthest communication distance can reach 1200 meters, a repeater A and a repeater B are arranged in the first junction box and the second junction box, the repeater A and the repeater B in the first junction box are electrically connected with the data receiver, the repeater A and the repeater B in the second junction box are electrically connected with the repeater B in the first junction box, and the repeater A in the first junction box and the repeater A in the second junction box are respectively electrically connected with a first sensor and a second sensor, so that strong anti-interference capability and differential signal transmission are realized through different wiring paths; the connection is simple, and normal communication can be carried out only by two signal wires (A+ and B-); the junction boxes are connected in series through a T-shaped bus scheme, so that the use of multiple nodes is completed, the influence of signal waveforms is effectively reduced, a high-speed NOT gate of a CMOS technology is adopted to realize an inverter structure, and the control and adjustment of signals are effectively realized; in order to improve anti-interference performance, the first junction box and the second junction box are used for forming an X channel for receiving data, the repeater B is used for forming a Y channel for outputting data information, the repeater A is used for forming a Z channel for transmitting the data information to the first sensor or the second sensor, and the separation of circuits of a system is realized through the setting of the X channel, the Y channel and the Z channel, so that the influence of signal waveforms is effectively reduced;
the first junction box and the second junction box are internally provided with four circuits which are respectively used for realizing communication transmission of an X channel, a Y channel and a Z channel, the X channel, the Y channel and the Z channel are respectively connected through the circuits, the X channel is respectively connected with the Y channel and the Z channel to complete control and regulation, the influence of effective signal waveform reduction is small, the four circuits are respectively provided with a NAND gate and a transceiver, the NAND gate adopts a SN74AHC1GU04SN74 chip, the transceiver adopts a MAX3485 chip, the MAX3485 chip is a half-duplex low-power transceiver, the control and regulation of signals are realized through the NAND gate, an inverter structure is realized, the receiving and transmitting of signals are realized through the transceiver, the half-duplex can realize effective communication and the installation of reduction devices, the VCC pin of the SN74AHC1GU04SN74 chip is electrically connected with an input power supply of 3.3V, the Y OUT pin of the SN74AHC1GU04SN74 chip in the four circuits is electrically connected with a grounded capacitor C1, a grounded capacitor C2, a grounded capacitor C3 and a grounded capacitor C4 respectively, the system is powered by an input power supply, the node safety protection is realized through the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4, lightning stroke current can be discharged, the safety is improved, the AIN pin of the SN74AHC1GU04SN74 chip is electrically connected with the RO pin of the MAX3485 chip, the AIN pin of the SN74AHC1GU04SN74 chip in the four circuits is electrically connected with a resistor R1, a resistor R2, a resistor R3 and a resistor R4 respectively, the resistor R2, the resistor R3 and the resistor R4 are electrically connected with an input power supply of 3.3V respectively, the input power supply is realized through the structure of the SN74AHC1GU04SN74 chip inverter, and then the output signal 3485 is realized through the control of the control chip, and resistance R1, resistance R2, resistance R3 and resistance R4 are pull-up resistor, realize controlling the on-state of MAX3485 chip, electric connection has 3.3V's input power supply on the VCC pin of MAX3485 chip, electric connection each other between RE pin and the DE pin of MAX3485 chip, RE pin is used for realizing right X passageway with Y passageway is connected, and X passageway with Z passageway is connected, and input power supply is used for realizing running to the power supply, and realizes connecting between X passageway, Y passageway and the Z passageway, accomplishes communication processing, electric connection has a resistance on the A pin and the B pin of MAX3485 chip respectively, electric connection has 3.3V's input power supply on the resistance on the A pin, electric connection ground on the B pin, the resistance of MAX3485 chip both sides bus is used for realizing that clamp control A pin department is high level, and B pin department is low level.
The bidirectional 485 bus repeater effectively solves the problems that the waveform quality of a bus in the prior art is reduced when a certain amount of sensors are mounted, communication with a terminal fails, and the like, and can still obtain good waveforms when the waveform quality of the bus is reduced, so that the communication distance of the bus and the number of mounted sensors are prolonged.
Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. 485 two-way communication sensor circuit based on cmos high-speed NOT gate, including data receiver, its characterized in that: the data receiver is electrically connected with a first junction box, the first junction box is electrically connected with a second junction box, a repeater A and a repeater B are arranged inside the first junction box and the second junction box, the repeater A and the repeater B in the first junction box are electrically connected with the data receiver, the repeater A and the repeater B in the second junction box are electrically connected with the repeater B in the first junction box, and the first junction box and the second junction box are electrically connected with a first sensor and a second sensor respectively on the repeater A.
2. The cmos high speed not gate based 485 bi-directional communication sensor circuit according to claim 1, wherein: the first junction box and the second junction box are used for forming an X channel for receiving data, the repeater B is used for forming a Y channel for outputting data information, and the repeater A is used for forming a Z channel for transmitting the data information to the first sensor or the second sensor.
3. The cmos high speed not gate based 485 bi-directional communication sensor circuit according to claim 2, wherein: the first junction box and the second junction box are internally provided with four circuits which are respectively used for realizing communication transmission of an X channel, a Y channel and a Z channel.
4. A cmos high speed not gate based 485 bi-directional communication sensor circuit according to claim 3, wherein: the four circuits comprise a NAND gate and a transceiver, wherein the NAND gate adopts an SN74AHC1GU04SN74 chip, the transceiver adopts a MAX3485 chip, and the MAX3485 chip is a half-duplex low-power-consumption transceiver.
5. The cmos high speed not gate based 485 bi-directional communication sensor circuit according to claim 4, wherein: the VCC pin of the SN74AHC1GU04SN74 chip is electrically connected with an input power supply of 3.3V, and the Yout pin of the SN74AHC1GU04SN74 chip in the four circuits is electrically connected with a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4 which are grounded respectively.
6. The cmos high speed not gate based 485 bi-directional communication sensor circuit according to claim 5, wherein: the AIN pin of the SN74AHC1GU04SN74 chip is electrically connected with the RO pin of the MAX3485 chip, a resistor R1, a resistor R2, a resistor R3 and a resistor R4 are respectively and electrically connected between the AIN pin of the SN74AHC1GU04SN74 chip and the RO pin of the MAX3485 chip in four circuits, and the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are respectively and electrically connected with 3.3V input power supplies.
7. The cmos high speed not gate based 485 bi-directional communication sensor circuit according to claim 6, wherein: the VCC pin of MAX3485 chip is last electric connection has 3.3V's input power supply, electric connection each other between RE pin and the DE pin of MAX3485 chip, RE pin is used for realizing to X passageway with Y passageway is connected, and X passageway with Z passageway is connected.
8. The cmos high speed not gate based 485 bi-directional communication sensor circuit according to claim 7, wherein: and the pin A and the pin B of the MAX3485 chip are respectively and electrically connected with a resistor, wherein the resistor on the pin A is electrically connected with an input power supply of 3.3V, and the resistor on the pin B is electrically grounded.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322473565.9U CN220754974U (en) | 2023-09-12 | 2023-09-12 | 485 bidirectional communication sensor circuit based on cmos high-speed NOT gate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322473565.9U CN220754974U (en) | 2023-09-12 | 2023-09-12 | 485 bidirectional communication sensor circuit based on cmos high-speed NOT gate |
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| CN220754974U true CN220754974U (en) | 2024-04-09 |
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| CN202322473565.9U Active CN220754974U (en) | 2023-09-12 | 2023-09-12 | 485 bidirectional communication sensor circuit based on cmos high-speed NOT gate |
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