CN210573749U

CN210573749U - LED control card interface testing arrangement

Info

Publication number: CN210573749U
Application number: CN201921644542.7U
Authority: CN
Inventors: 叶金湖; 欧阳其平
Original assignee: Shenzhen Huidu Technology Co ltd
Current assignee: Shenzhen Huidu Technology Co ltd
Priority date: 2019-09-29
Filing date: 2019-09-29
Publication date: 2020-05-19
Anticipated expiration: 2029-09-29

Abstract

The utility model discloses a LED control joint interface testing arrangement. The device includes: the LED control card comprises a first FPGA control unit and a first flat cable interface, the test module comprises a second FPGA control unit, a second flat cable interface and an indicator light unit, the first flat cable interface is connected with the second flat cable interface, and the first FPGA control unit is used for sending a first detection signal according to a preset rule; the first flat cable interface is used for receiving the first detection signal and outputting a second detection signal through the second flat cable interface; the second FPGA control unit is used for judging whether the second detection signal is the same as the first detection signal or not and outputting a judgment result; and the indicator light unit is used for displaying according to the judgment result. The technical scheme of the utility model the effect of simple and convenient testing process and energy saving has been realized.

Description

LED control card interface testing arrangement

Technical Field

The embodiment of the utility model provides a relate to the LED display screen field, especially relate to a LED control card interface testing arrangement.

Background

The existing display screen with more than small and medium size has large loading area and more scanning points, and basically, the display screen is driven by using an FPGA and a decoder. The FPGA needs a large number of exclusion wires and electronic components connected with the flat cable base due to a plurality of pins. In actual production, due to the defect rate of components and parts and the defects (such as insufficient soldering) of the processing technology, the probability that the connectivity between a certain pin and a flat cable base is poor is caused, so that the problem that the display effect of an actual LED display screen is poor is caused. In the production test, the LED control card is connected with the LED display screen through the flat cable, and after the screen is adjusted, actual display on the display screen is observed to see whether abnormal display exists. The whole process is complex and tedious and is easy to make mistakes.

SUMMERY OF THE UTILITY MODEL

The utility model provides a LED control card interface testing arrangement to realize simple and convenient test procedure and energy saving's effect.

In a first aspect, an embodiment of the present invention provides a LED control card interface testing apparatus, include: the LED control card comprises a first FPGA control unit and a first bus interface, the test module comprises a second FPGA control unit, a second bus interface and an indicator light unit, the first bus interface is connected with the second bus interface,

the first FPGA control unit is used for sending out a first detection signal according to a preset rule;

the first flat cable interface is used for receiving the first detection signal and outputting a second detection signal through the second flat cable interface;

the second FPGA control unit is used for judging whether the second detection signal is the same as the first detection signal or not and outputting a judgment result;

and the indicator light unit is used for displaying according to the judgment result.

Optionally, the LED control card further includes a first storage unit, the test module further includes a second storage unit,

the first storage unit is used for storing the detection data stored by the first FPGA control unit;

the second storage unit is used for storing the judgment data stored by the second FPGA control unit.

Optionally, the first memory unit comprises a RAM1 memory sub-unit and a RAM2 memory sub-unit, the RAM1 memory sub-unit comprises a memory area A and a memory area B,

the storage area A and the storage area B are used for storing detection data stored by a first FPGA control unit;

the RAM2 stores information of a storage area, recorded by the first FPGA control unit, where the last stored detection data is stored.

Optionally, the LED control card further includes a first power supply unit, and the test module further includes a second power supply unit.

Optionally, the first power supply unit includes a first power supply selection subunit and at least two first power supplies.

Optionally, the second power supply unit includes a second power supply selection subunit and at least two second power supplies.

The utility model discloses technical scheme has solved the loaded down with trivial details problem of current LED control card pin and winding displacement base connectivity test process through a LED control joint interface testing arrangement, has reached simple and convenient test procedure and energy saving's effect.

Drawings

Fig. 1 is a schematic structural diagram of a device for testing an interface of an LED control card according to a first embodiment of the present invention.

Fig. 2 is a schematic structural diagram of an LED control card interface testing apparatus according to a second embodiment of the present invention.

Fig. 3 is a schematic structural diagram of an LED control card interface testing apparatus according to a second embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an LED control card interface testing apparatus in the third embodiment of the present invention.

Fig. 5 is a schematic structural diagram of an LED control card interface testing apparatus according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, the first FPGA control unit may be referred to as a second FPGA control unit, and similarly, the second FPGA control unit may be referred to as a first FPGA control unit, without departing from the scope of the present application. Both the first FPGA control unit and the second FPGA control unit are FPGA control units, but they are not the same FPGA control unit. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Example one

Fig. 1 is a schematic structural diagram of a LED control card interface testing device according to an embodiment of the present invention, which is applicable to a LED control card interface test condition in this embodiment, the LED control card interface testing device includes a LED control card 1 and a testing module 2, the LED control card 1 includes a first FPGA control unit 11 and a first bus interface 12, the testing module 2 includes a second FPGA control unit 21, a second bus interface 22 and an indicator light unit 23, the first bus interface 12 is connected to the second bus interface 22, and the first FPGA control unit 11 is configured to send a first detection signal according to a preset rule; the first bus bar interface 12 is configured to receive the first detection signal and output a second detection signal through the second bus bar interface 22; the second FPGA control unit 21 is configured to determine whether the second detection signal is the same as the first detection signal and output a determination result; the indicator light unit 23 is configured to display according to the determination result.

In this embodiment, the first FPGA control unit 11 is connected to the first bus interface 12, the second FPGA control unit 21 is connected to the second bus interface 22, and the first bus interface 12 is connected to the second bus interface 22 through a bus. The flat cable is used for data transmission in movable parts and movable areas according to flat cable rules, line sequences, line colors, line numbers and the like specified by the industry specifications, such as data lines of a hard disk and an optical drive connected with a mainboard inside a computer, data lines of a display screen connected with a mainboard of a mobile phone, and data lines connected between devices. The flat cable is a flexible flat cable and mainly comprises two types, namely a two-end round head (R-FFC) for direct welding and a two-end flat head (FFC) for inserting into a socket. A plurality of pins of the first FPGA control unit 11 are welded to the first bus interface 12, and the indicator light unit 23 of the test module 2 has the same number of indicator lights as the pins of the first FPGA control unit 11, and the indicator lights are in one-to-one correspondence with the pins of the first FPGA control unit 11. In the testing process, the first FPGA control unit 11 of the LED control card 1 will continuously change the level of each pin according to a preset rule, and if the pin of the second FPGA control unit 21 of the testing module 2 receives the level changed according to the preset rule at the second flat cable interface 22, the indicator light corresponding to the pin displays green; if the quality of the level signal received by the pin of the second FPGA control unit 21 of the test module 2 is not good, for example, the duration of the high and low levels is not equal, the indicator light corresponding to the pin displays red; if the pin of the second FPGA control unit 21 of the test module 2 does not receive the level signal for a period of time, the indicator light corresponding to the pin is turned off.

Example two

Fig. 2 is a schematic structural diagram of a LED control card interface testing apparatus provided in the second embodiment of the present invention, which is different from the first embodiment in that the embodiment of the present invention further includes a first storage unit 13, the testing module 2 further includes a second storage unit 24, and the first storage unit 13 is used for storing the detection data stored in the first FPGA control unit 11; the second storage unit 24 is used for storing the comparison data stored by the second FPGA control unit 21.

In this embodiment, the first storage unit 13 may be configured to store display data and test data provided by an upper computer. The test data includes a preset pin level variation rule. The first FPGA control unit 11 controls the level change of the pins soldered to the first bus interface 12 according to the pin level change rule in the test data. The second storage unit 24 is configured to store comparison data that is the same as the test data, and the second FPGA control unit 21 detects whether a received pin level change is consistent with a pin level change rule included in the comparison data to control display of the indicator light.

Referring to fig. 3, the first storage unit 13 includes a RAM1 storage sub-unit 131 and a RAM2 storage sub-unit 132, and the RAM1 storage sub-unit 131 includes a storage area a and a storage area B for storing the detection data held by the first FPGA control unit 11; the RAM2 stores information of a storage area of the subunit for storing the last saved detection data recorded by the first FPGA control unit 11.

In this embodiment, the RAM1 storage subunit 131 is used for storing display data provided by an upper computer, and the inside of the RAM1 storage subunit is divided into a storage area a and a storage area B; illustratively, display data sent by the upper computer for the first time is stored in a storage area a of the RAM1 through the first FPGA control unit 11, and then the first FPGA control unit 11 reads the display data from the storage area a and sends the display data to a corresponding LED display board for display; when new display data is input, the first FPGA control unit 11 determines whether the storage area a or the storage area B is currently operated, writes the input display data into the storage area which is not currently operated after the determination result is obtained, and reads out the newly updated display data for display after the input display data is written out, so as to ensure that the problems of screen flashing and error information do not occur on the LED display screen, such as the LED advertisement screen. The RAM2 stores a sub-unit 132 for storing a flag of a storage area in which display data currently being operated is stored and a data output end flag.

The embodiment of the utility model provides a through a LED control joint interface testing arrangement, solved the LED display screen and easily appear the problem of twinkling of a screen and error message, reached the effect of avoiding the LED display screen to twinkle the screen and the wrong demonstration.

EXAMPLE III

Fig. 4 is the third embodiment of the present invention provides a structural schematic diagram of a LED control card interface testing device, which is different from the third embodiment of the present invention in that the embodiment of the present invention is that the control card 1 further includes a first power supply unit 14, and the testing module 2 further includes a second power supply unit 25.

In this embodiment, the first power supply unit 14 and the second power supply unit 25 respectively provide power supplies with constant dc voltages of 5V/3.3V for the first FPGA control unit 11 and the second FPGA control unit 21.

Referring to fig. 5, the first power supply unit 14 includes at least two first power supplies 141 and a first power supply selection subunit 142, and the second power supply unit 25 includes at least two second power supplies 251 and a first power supply selection subunit 252.

In this embodiment, the first power supply unit 14 includes at least two first power supplies 141 and a first power supply selection subunit 142, wherein an input end of the first power supply selection subunit 142 is electrically connected to the at least two first power supplies 141, an output end of the first power supply selection subunit 142 is used for being electrically connected to the first FPGA control unit 11, and the first power supply selection subunit 142 is used for maintaining at least one first power supply 141 to supply power to the first FPGA control unit 11, so that when the currently operating first power supply 141 fails, the first FPGA control unit 11 can still operate normally, interruption of a display signal is avoided, and it is ensured that a display effect of the LED display screen is not affected.

The second power supply unit 25 includes at least two second power supplies 251 and a second power supply selection subunit 252, wherein an input end of the second power supply selection subunit 252 is electrically connected to the at least two second power supplies 251, an output end of the second power supply selection subunit 252 is used for being electrically connected to the second FPGA control unit 21, and the second power supply selection subunit 252 is used for maintaining at least one second power supply 251 to supply power to the second FPGA control unit 21, so that when the currently operating second power supply 251 fails, the second FPGA control unit 21 can still operate normally, and it is ensured that the test function of the test module 2 is not affected.

The embodiment of the utility model provides a through a LED control joint interface testing arrangement, solved the unstable problem of device power supply, reached and avoided the effect that power supply trouble influences the device and use.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims

1. The utility model provides a LED control card interface testing arrangement which characterized in that includes: the LED control card comprises a first FPGA control unit and a first bus interface, the test module comprises a second FPGA control unit, a second bus interface and an indicator light unit, the first bus interface is connected with the second bus interface,

2. The LED control card interface test device of claim 1, wherein the LED control card further comprises a first storage unit, the test module further comprises a second storage unit,

and the second storage unit is used for storing the comparison data stored by the second FPGA control unit.

3. The LED control card interface test apparatus of claim 2, wherein the first storage unit includes a RAM1 storage sub-unit and a RAM2 storage sub-unit, the RAM1 storage sub-unit includes a storage area A and a storage area B,

4. The LED control card interface test device of claim 1, wherein the LED control card further comprises a first power supply unit, and the test module further comprises a second power supply unit.

5. The LED control card interface test device of claim 4, wherein the first power supply unit comprises a first power selection subunit and at least two first power supplies.

6. The LED control card interface test apparatus of claim 4, wherein the second power supply unit comprises a second power selection subunit and at least two second power supplies.