CN210573462U

CN210573462U - Power supply circuit and electric equipment

Info

Publication number: CN210573462U
Application number: CN201921240391.9U
Authority: CN
Inventors: 王小保; 赵卫军; 余冰; 杨红祥; 牟加伟
Original assignee: Shanghai Core Hunting Semiconductor Technology Co ltd
Current assignee: Shanghai Core Hunting Semiconductor Technology Co ltd
Priority date: 2019-05-22
Filing date: 2019-08-01
Publication date: 2020-05-19
Anticipated expiration: 2029-08-01
Also published as: CN110442181A

Abstract

The utility model discloses a power supply circuit and consumer. Wherein, power supply circuit includes: a first current source circuit configured to generate a first current having a positive temperature coefficient; a second current source circuit configured to generate a second current having a negative temperature coefficient; the first input end of the current operation circuit is connected with the output end of the first current source circuit, which outputs the first current, and the second input end of the current operation circuit is connected with the output end of the second current source circuit, which outputs the second current; the current operation circuit is configured to output a difference current of the first current and the second current, wherein a temperature coefficient of the difference current is greater than a positive temperature coefficient or less than a negative temperature coefficient.

Description

Power supply circuit and electric equipment

Technical Field

The utility model relates to a power technical field especially relates to a power supply circuit and consumer.

Background

With the development of scientific technology, electrical equipment is generally applied to various fields, such as daily life or scientific research. Meanwhile, a power circuit for supplying power to an electric device is also widely used.

At present, the current output by the power circuit may be a current with a positive temperature coefficient, a current with a negative temperature coefficient, or a current with a zero temperature coefficient. However, the temperature coefficient of the current output by the power supply circuit is a finite invariant. For example, the concept of a bandgap reference voltage is used to generate a reference current with a positive temperature coefficient that is related only to the thermal voltage, whereas the thermal voltage is usually constant, i.e. the positive temperature coefficient of the reference current is constant. For another example, a negative temperature coefficient of reference current is generated by using the negative temperature characteristic of the diode PN junction voltage, the negative temperature coefficient of reference current is related only to the diode PN junction voltage, and the PN junction voltage is also generally constant, i.e., the negative temperature coefficient of reference current is constant.

Therefore, a power supply circuit capable of exceeding the temperature coefficient of the current output by the conventional power supply circuit is desired to be proposed.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a new power supply circuit scheme.

According to the utility model discloses an aspect provides a power supply circuit, include:

a first current source circuit configured to generate a first current having a positive temperature coefficient;

a second current source circuit configured to generate a second current having a negative temperature coefficient;

a first input terminal of the current operation circuit is connected to an output terminal of the first current source circuit, which outputs the first current, and a second input terminal of the current operation circuit is connected to an output terminal of the second current source circuit, which outputs the second current; the current operation circuit is configured to output a difference current of the first current and the second current, wherein a temperature coefficient of the difference current is greater than the positive temperature coefficient or less than the negative temperature coefficient.

Optionally, the first current source circuit is a bandgap reference current source circuit; and/or the second current source circuit is a diode type current source circuit.

Optionally, the current operation circuit includes a first current mirror circuit, an input end of the first current mirror circuit is used as the second input end, and is connected to an output end of the second current source, which outputs the second current; the output end of the first current mirror circuit is connected to the first input end, so that the flow direction of the first current relative to the first input end is opposite to the flow direction of the mirror image current of the second current relative to the first input end.

Optionally, the current operation circuit includes a second current mirror circuit, and an input end of the second current mirror circuit is used as the first input end to obtain the differential current; and the output end of the second current mirror circuit outputs the mirror current of the difference current.

Optionally, the second current mirror circuit includes a first PMOS transistor and a second PMOS transistor; wherein:

the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are respectively connected to the output end of a first external voltage source;

the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube;

the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the first PMOS tube is used as the input end of the second current mirror circuit;

and the drain electrode of the second PMOS tube is used as the output end of the second current mirror circuit.

Optionally, the second current mirror circuit includes a first NMOS transistor and a second NMOS transistor; wherein:

the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded respectively;

the grid electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube;

the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube, and the drain electrode of the first NMOS tube is used as the input end of the second current mirror circuit;

and the drain electrode of the second NMOS tube is used as the output end of the second current mirror circuit.

Optionally, the first current mirror circuit includes a third NMOS transistor and a fourth NMOS transistor; wherein:

the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded;

the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube;

the drain electrode of the third NMOS tube is connected with the grid electrode of the third NMOS tube, and the drain electrode of the third NMOS tube is used as the input end of the first current mirror circuit;

and the drain electrode of the fourth NMOS tube is used as the output end of the first current mirror circuit.

Optionally, the bandgap reference current source circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first amplifier, a first diode, a second diode, and a first resistor; wherein:

the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are respectively connected to the output end of a second external voltage source;

the grid electrode of the third PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube;

the drain electrode of the fifth PMOS tube is used as the output end of the first current source circuit for outputting the first current;

the anode of the first diode is connected with the drain electrode of the third PMOS tube, and the cathode of the first diode is grounded;

the first resistor is connected between the drain electrode of the fourth PMOS tube and the cathode of the second diode, and the cathode of the second diode is grounded;

the output end of the first amplifier is connected between the grid electrode of the third PMOS tube, the inverting input end of the first amplifier is connected between the drain electrode of the third PMOS tube and the anode of the first diode, and the non-inverting input end of the first amplifier is connected between the drain electrode of the fourth PMOS tube and the first resistor.

Optionally, the diode-type current source circuit includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a second amplifier, a third diode, and a second resistor; wherein:

the source electrode of the sixth PMOS tube, the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube are respectively connected to the output end of a third external voltage source;

the grid electrode of the sixth PMOS tube is respectively connected with the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube;

the drain electrode of the sixth PMOS tube is used as the output end of the second current source circuit for outputting the second current;

the second resistor is connected between the drain electrode of the seventh PMOS tube and the ground;

the anode of the third diode is connected with the drain of the eighth PMOS tube, and the cathode of the third diode is connected with the ground;

the output end of the second amplifier is connected to the grid electrode of the seventh PMOS tube, the inverting input end of the second amplifier is connected between the drain electrode of the eighth PMOS tube and the anode of the third diode, and the non-inverting input end of the second amplifier is connected between the drain electrode of the seventh PMOS tube and the second resistor.

Optionally, the power circuit further includes a current-to-voltage circuit;

the current-to-voltage circuit is configured to: receiving the difference current and outputting a voltage proportional to the difference current.

Optionally, the current conversion circuit converts the difference current into a voltage output through a zero temperature coefficient resistor.

According to a second aspect of the present invention, there is provided an electric consumer comprising a power supply circuit as defined in the first aspect.

In the embodiment of the present invention, the current operation circuit in the power supply circuit is configured to be used for outputting the difference current of the first current and the second current, and the temperature coefficient of the difference current is greater than the positive temperature coefficient of the first current source circuit, or is less than the negative temperature coefficient. The embodiment of the utility model provides a surpass the power supply circuit of the temperature coefficient of first current source circuit or the output current of second current source circuit promptly.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the invention and are therefore not to be considered limiting of its scope. For a person skilled in the art, it is possible to derive other relevant figures from these figures without inventive effort.

Fig. 1 is a first schematic structural diagram of a power circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a bandgap reference current source circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a diode-type current source circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a first current mirror according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a second current mirror according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another second current mirror provided in the embodiment of the present invention;

fig. 7 is a schematic structural diagram ii of a power circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram three of a power supply circuit according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a function relationship between an output current of a power circuit and a temperature variation;

fig. 10 is a schematic diagram illustrating a function of an output current of another power circuit according to an embodiment of the present invention;

fig. 11 is a fourth schematic structural diagram of a power supply circuit according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a power supply circuit according to an embodiment of the present invention;

fig. 13 is a sixth schematic structural diagram of a power supply circuit according to an embodiment of the present invention;

fig. 14 is a seventh schematic structural diagram of a power supply circuit according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram eight of a power supply circuit according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram nine of a power supply circuit according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram ten of a power supply circuit according to an embodiment of the present invention;

fig. 18 is an eleventh schematic structural diagram of a power supply circuit according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless specifically stated otherwise, the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

< Power supply Circuit >

Referring to fig. 1, a power circuit according to an embodiment of the present invention is described. The power supply circuit includes: the circuit comprises a first current source circuit, a second current source circuit and a current operation circuit. Wherein:

a first current source circuit configured to generate a first current having a positive temperature coefficient.

In one example, the first current source circuit is a bandgap reference current source circuit.

In one embodiment, as shown in fig. 2, a bandgap reference current source circuit includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first amplifier OP1, a first diode D1, a second diode D2, and a first resistor R1.

Wherein, the source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4The sources of the fifth PMOS transistor MP5 are respectively connected to the output terminal of the second external voltage source Vdd 2. The gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5, respectively. The drain of the fifth PMOS transistor MP5 is used as the output first current I of the first current source circuit_PTATTo the output terminal of (a). The anode of the first diode D1 is connected to the drain of the third PMOS transistor MP3, and the cathode of the first diode D1 is grounded. The first resistor R1 is connected between the drain of the fourth PMOS transistor MP4 and the anode of the second diode D2, and the cathode of the second diode D2 is grounded. An output terminal of the first amplifier OP1 is connected to the gate of the third PMOS transistor MP3, an inverting input terminal of the first amplifier OP1 is connected between the drain of the third PMOS transistor MP3 and the anode of the first diode D1, and a non-inverting input terminal of the first amplifier OP1 is connected between the drain of the fourth PMOS transistor MP4 and the first resistor R1.

It should be noted that the ratio of the width-to-length ratio of MP3 to the width-to-length ratio of MP4 is 1: 1. Further, the structure of the bandgap reference current source circuit is not limited to the structure shown in fig. 2. Any current source circuit capable of generating a current with a positive temperature coefficient is within the protection scope of the present invention.

In one example, the first current I generated by the first current source circuit_PTATCan be expressed as: i is_PTAT＝m(1+JΔT)I_S1。

Wherein, I_S1The reference current generated by the first current source circuit is shown. When the first current source circuit is as shown in FIG. 2, I_S1Is the drain current of the third PMOS transistor MP 3. m denotes a first current I generated by the first current source circuit_PTATAnd a reference current I generated by the first current source circuit_S1I.e. the current copy ratio of the first current source. When the first current source circuit is as shown in fig. 2, m is a ratio of the drain current of the fifth PMOS transistor MP5 to the drain current of the third PMOS transistor MP 3.Δ T represents the amount of change in the current temperature from room temperature. J denotes a positive temperature coefficient of the first current generated by the first current source circuit, i.e., J is greater than 0.

A second current source circuit configured to generate a second current having a negative temperature coefficient.

In one example, the second current source circuit is a diode-type current source circuit.

In one embodiment, as shown in fig. 3, the diode-type current source circuit includes: a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a second amplifier OP2, a third diode D3, and a second resistor R2.

The source of the sixth PMOS transistor MP6, the source of the seventh PMOS transistor MP7, and the source of the eighth PMOS transistor MP8 are respectively connected to the output terminal of the third external voltage source Vdd 3. The gate of the sixth PMOS transistor MP6 is connected to the gates of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, respectively. The drain of the sixth PMOS transistor MP6 is used as the output second current I of the second current source circuit_CTATTo the output terminal of (a). The second resistor R2 is connected between the drain of the seventh PMOS transistor MP7 and ground. An anode of the third diode D3 is connected to the drain of the eighth PMOS transistor MP8, and a cathode of the third diode D3 is connected to ground. An output end of the second amplifier OP2 is connected to the gate of the seventh PMOS transistor MP7, an inverting input end of the second amplifier OP2 is connected between the drain of the eighth PMOS transistor MP8 and the anode of the third diode D3, and a non-inverting input end of the second amplifier OP2 is connected between the drain of the seventh PMOS transistor MP7 and the second resistor R2.

It should be noted that the ratio of the width-to-length ratio of MP7 to the width-to-length ratio of MP8 is 1: 1. Further, the structure of the diode-type current source circuit is not limited to the structure shown in fig. 3. Any current source circuit capable of generating a current with a negative temperature coefficient is within the scope of the present invention. Meanwhile, the Vdd2 and Vdd3 may be the same or different.

In one example, the second current I generated by the second current source circuit_CTATCan be expressed as: i is_CTAT＝n(1+KΔT)I_S2。

Wherein, I_S2The reference current generated by the second current source circuit is shown. When the second current source circuit is as shown in FIG. 3, I_S2Is the drain current of the eighth PMOS transistor MP 8. n denotes a second current I generated by a second current source circuit_CTATWith reference generated by a second current source circuitCurrent I_S2I.e. the current copy ratio of the first current source. When the second current source circuit is as shown in fig. 3, n is a ratio of the drain current of the eighth PMOS transistor MP8 to the drain current of the sixth PMOS transistor MP 6.Δ T represents the amount of change in the current temperature from room temperature. K denotes a negative temperature coefficient of the second current generated by the second current source circuit, i.e. K is smaller than 0.

The first input end of the current operation circuit is connected with the output end of the first current source circuit, which outputs the first current, and the second input end of the current operation circuit is connected with the output end of the second current source circuit, which outputs the second current; the current operation circuit is configured to output a difference current of the first current and the second current, wherein a temperature coefficient of the difference current is greater than a positive temperature coefficient or less than a negative temperature coefficient.

In one embodiment, the current operational circuit includes a first current mirror circuit. The input end of the first current mirror circuit is used as a second input end and is connected with the output end of the second current source, which outputs the second current; the output end of the first current mirror circuit is connected with the first input end, so that the flow direction of the first current relative to the first input end is opposite to the flow direction of the mirror image current of the second current relative to the first input end.

In one example, the first current mirror may be configured as shown in FIG. 4. Specifically, the first current mirror circuit includes: a third NMOS transistor MN3, a fourth NMOS transistor MN 4; the source electrode of the third NMOS transistor MN3 and the source electrode of the fourth NMOS transistor MN4 are grounded; the grid electrode of the third NMOS transistor MN3 is connected with the grid electrode of the fourth NMOS transistor MN 4; the drain of the third NMOS transistor MN3 is connected to the gate of the third NMOS transistor MN3, and the drain of the third NMOS transistor MN3 serves as the input terminal of the first current mirror circuit; the drain of the fourth NMOS transistor MN4 serves as the output terminal of the first current mirror circuit.

It should be noted that the ratio of the width-to-length ratio of the third NMOS transistor MN3 to the width-to-length ratio of the fourth NMOS transistor MN4 is 1: 1. In addition, the structure of the first current mirror circuit in the embodiment of the present invention is not limited to the structure shown in fig. 4. Any structure that can realize that the flow direction of the first current relative to the first input end is opposite to the flow direction of the mirror image current of the second current relative to the first input end is within the protection scope of the present invention.

In one embodiment, the current operation circuit further includes a second current mirror circuit. The input end of the second current mirror circuit is used as a first input end to obtain a differential current; the output end of the second current mirror circuit outputs the mirror current of the difference current.

In one example, as shown in fig. 5, the second current mirror circuit includes a first PMOS transistor MP1, a second PMOS transistor MP 2; the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are respectively connected to the output terminal of the first external voltage source Vdd 1; the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the second PMOS tube MP 2; the drain of the first PMOS transistor MP1 is connected to the gate of the first PMOS transistor MP1, and the drain of the first PMOS transistor MP1 serves as the input terminal of the second current mirror circuit; the drain of the second PMOS transistor MP2 serves as the output terminal of the second current mirror circuit. In this embodiment, the power circuit provided in the embodiment of the present invention is used as an output type power circuit.

It should be noted that the ratio between the width-to-length ratio of the first PMOS transistor MP1 and the width-to-length ratio of the second PMOS transistor MP2 is 1: 1.

In the structure shown in FIG. 5, the above-mentioned differential current I_outIs a second current I_CTATMinus the first current I_PTAT. In particular, I_out＝I_CTAT-I_PTATFurther, I_out＝I_CTAT-I_PTAT＝n(1+KΔT)I_S2-m(1+JΔT)I_S1. Correspondingly, the difference current I_outTemperature coefficient of

Comprises the following steps:

based on the above equation 7, only nI needs to be set_S2And mI_S1The relative size of alright make the embodiment of the utility model provides a power supply circuit's temperature coefficient is greater than the positive temperature of first current source circuitDegree coefficient, or less than the negative temperature coefficient of the second current source circuit. Specifically, at setting nI_S2Greater than mI_S1When the temperature of the water is higher than the set temperature,

be less than K, promptly the embodiment of the utility model provides a power supply circuit's temperature coefficient is negative temperature coefficient, and is less than second current source circuit's negative temperature coefficient. At setting nI_S2Less than mI_S1When the temperature of the water is higher than the set temperature,

is greater than J. Namely, the embodiment of the utility model provides a power supply circuit's temperature coefficient is positive temperature coefficient, and is greater than first current source circuit's positive temperature coefficient.

In one example, when I_S1Can be combined with I_S2The same is true. Based on this, the above equation 7 may be replaced with the following equation 8:

based on the above equation 8, when n is set to be larger than m,

be less than K, promptly the embodiment of the utility model provides a power supply circuit's temperature coefficient is negative temperature coefficient, and is less than second current source circuit's negative temperature coefficient. When n is set to be smaller than m,

be greater than J, promptly the embodiment of the utility model provides a temperature coefficient that provides power supply circuit is positive temperature coefficient, and is greater than first current source circuit's positive temperature coefficient.

In another example, as shown in fig. 6, the second current mirror circuit includes a first NMOS transistor MN1, a second NMOS transistor; the source electrode of the first NMOS transistor MN1 and the source electrode of the second NMOS transistor MN2 are grounded respectively; the grid electrode of the first NMOS transistor MN1 is connected with the grid electrode of the second NMOS transistor MN 2; the drain electrode of the first NMOS transistor MN1 is connected with the gate electrode of the first NMOS transistor MN1, and the drain electrode of the first NMOS transistor MN1 is used as the input end of the second current mirror circuit; the drain of the second NMOS transistor MN2 serves as the output of the second current mirror circuit. In this embodiment, the power supply circuit provided by the embodiment of the present invention is used as an input type power supply circuit.

In the structure shown in FIG. 6, the above-mentioned differential current I_outIs a first current I_PTATMinus the second current I_CTAT. In particular, I_out＝I_PTAT-I_CTATFurther, I_out＝I_PTAT-I_CTAT＝m(1+JΔT)I_S1-n(1+KΔT)I_S2. Correspondingly, the difference current I_outTemperature coefficient of

Comprises the following steps:

based on the above equation 9, only mI needs to be set_S1And nI_S2The embodiment of the utility model provides a power supply circuit's temperature coefficient be greater than the positive temperature coefficient of first current source circuit, perhaps be less than the negative temperature coefficient of second current source circuit. Specifically, at setting mI_S1Greater than nI_S2When the temperature of the water is higher than the set temperature,

be greater than J, promptly the embodiment of the utility model provides a temperature coefficient that provides power supply circuit is positive temperature coefficient, and is greater than first current source circuit's positive temperature coefficient. At setting mI_S1Less than nI_S2When the temperature of the water is higher than the set temperature,

is less than K. Namely, the embodiment of the utility model provides a power supply circuit's temperature coefficient is negative temperature coefficient, and is less than second current source circuit's negative temperature coefficient

In one embodiment, when I_S1Can be combined with I_S2The same is true. On the basis of this, the method is suitable for the production,the above equation 9 may be replaced with the following equation 10:

based on the above equation 8, when m is set to be larger than n,

be greater than J, promptly the embodiment of the utility model provides a temperature coefficient that provides power supply circuit is positive temperature coefficient, and is greater than first current source circuit's positive temperature coefficient. When m is smaller than n, the ratio of n,

be less than K, promptly the embodiment of the utility model provides a power supply circuit's temperature coefficient is negative temperature coefficient, and is less than second current source circuit's negative temperature coefficient.

When the sizes of m and n are set, the ratio of the width-to-length ratio of the third PMOS transistor to the width-to-length ratio of the fifth PMOS transistor may be set to implement the setting of m. Correspondingly, the setting of n can be realized by setting the ratio of the width-to-length ratio of the eighth PMOS transistor to the width-to-length ratio of the sixth PMOS transistor.

In a specific example, I is shown on the basis of FIG. 2, FIG. 3, FIG. 4 and FIG. 5_S1And I_S2Meanwhile, the structure of the power circuit provided by the embodiment of the present invention can be as shown in fig. 7. Meanwhile, on the basis of the above fig. 2, fig. 3, fig. 4 and fig. 6, the structure of the power circuit provided by the embodiment of the present invention can be as shown in fig. 8.

Further as shown in FIG. 9, I in FIG. 9_PTATThe corresponding line shows the output current of the bandgap reference current source circuit as a function of temperature as shown in figure 2. I in FIG. 9_outThe line corresponding to _1indicates the output current of the power supply circuit as a function of temperature as shown in fig. 7 or 8 when m is 1 and n is 0.5. I in FIG. 9_outThe line corresponding to _2indicates that when m is 2 and n is 1, as shown in fig. 7 or 8The output current of the power supply circuit is a function of the temperature variation. Based on it can be clear that figure 9 shows, the embodiment of the utility model provides a power supply circuit, when m is greater than n, the temperature coefficient of the electric current of output has surpassed the positive temperature coefficient that band gap reference current source circuit's output current corresponds.

Correspondingly, as shown in FIG. 10, I in FIG. 10_CTATThe corresponding line shows the output current of the diode-type current source circuit as shown in fig. 3 as a function of temperature. I in FIG. 10_outThe line corresponding to _1 indicates the output current of the power supply circuit as a function of temperature as shown in fig. 7 or fig. 8 when m is 0.5 and n is 1.5. I in FIG. 10_outThe line corresponding to _2 represents the output current of the power supply circuit as a function of temperature as shown in fig. 7 or 8 when m is 1 and n is 2. Based on it can be clear that figure 10 shows, the embodiment of the utility model provides a power supply circuit, when n is greater than m, the temperature coefficient of the electric current of output has surpassed the negative temperature coefficient that diode type current source circuit's output current corresponds.

In one embodiment, on the basis of the first current source structure and the second current source structure, the current operation circuit may further include: a third amplifier OP3, a fourth resistor R4, a fifth resistor R5, and a first common-gate current mirror circuit. Based on this, the present embodiment provides the following two types of current operation circuits:

the first current operation circuit is the current operation circuit in the power supply circuit shown in fig. 13, specifically, the non-inverting input terminal of the third amplifier OP3 is connected to one end of the fourth resistor R4, the inverting input terminal of the third amplifier OP3 is connected to one end of the fifth resistor R5, and the output terminal of the third amplifier OP3 is connected to the common gate of the first common-gate current mirror circuit. The other end of the fourth resistor R4 and the other end of the fifth resistor R5 are grounded. The output end of the first current source for outputting the first current is respectively connected with the non-inverting input end of the third amplifier OP3 and the input end of the first common-gate current mirror circuit, and the output end of the second current source for outputting the second current is connected with the inverting input end of the third amplifier OP 3. The output end of the first common-gate current mirror circuit is used for outputting a difference current.

It should be noted that, as shown in fig. 13, the structure of the first common-gate current mirror may include: a fifteenth PMOS transistor MP15 and a sixteenth PMOS transistor MP 16. The source of the fifteenth PMOS transistor MP15 and the source of the sixteenth PMOS transistor MP16 are connected to the sixth external voltage source terminal Vdd 6. The gate of the fifteenth PMOS transistor MP15 is connected to the gate of the sixteenth PMOS transistor MP 16. The gate of the fifteenth PMOS transistor MP15 serves as the common gate of the first common-gate current mirror. The drain of the fifteenth PMOS transistor MP15 serves as the input terminal of the first common-gate current mirror circuit, and the drain of the sixteenth PMOS transistor MP16 serves as the output terminal of the first common-gate current mirror circuit. In addition, the resistance values of the fifth resistor R5 and the fourth resistor R4 may be the same or different.

In the current operation circuit shown in fig. 13, the circuit principle of current operation is described by taking the example that the resistance values of the fourth resistor R4 and the fifth resistor R5 are the same. Since the voltage at the non-inverting input terminal of the third amplifier OP3 is the same as the voltage at the inverting input terminal under the action of the third amplifier OP3, the current flowing through the fifth resistor R5 is the second current, and the resistances of the fifth resistor R5 and the fourth resistor R4 are the same, and the current flowing through the fourth resistor R4 is also the second current. Further, in order to maintain the same voltage at the non-inverting input terminal and the inverting input terminal of the third amplifier OP3, the current flowing through the fourth resistor R4 will be kept unchanged by the third amplifier OP3 (i.e. kept unchanged by the current flowing through the fifth resistor R5). When the first current flows into the node of the non-inverting input terminal of the third amplifier OP3, based on the flow direction of the first current and the flow direction of the second current flowing through the fourth resistor R4, the third amplifier OP3 automatically adjusts the gate-source voltages of the fifteenth PMOS transistor MP15 and the sixteenth PMOS transistor MP16 in the first common-gate current mirror, so that the drain current of the fifteenth PMOS transistor MP15 is a difference current of the second current minus the first current, thereby maintaining the current flowing through the fourth resistor R4 as the second current. Under the action of the first common-gate current mirror, the drain current of the sixteenth PMOS transistor MP16 is the difference current of the second current minus the first current.

It should be noted that the first current in the present embodiment may be the first current generated by the bandgap reference current source shown in fig. 2, and the second current in the present embodiment may be the second current generated by the diode-type current source circuit shown in fig. 3. Based on this, the difference current outputted by the drain of the sixteenth PMOS transistor MP16 in the first common-gate current mirror is the second current minus the first current. That is, the differential current and the calculation formula of the temperature coefficient of the differential current of the present embodiment can refer to the above formula (7) and formula (8).

A second current operation circuit is a current operation circuit in the power supply circuit shown in fig. 14, specifically, a non-inverting input terminal of a third amplifier OP3 is connected to one end of a fourth resistor R4, an inverting input terminal of a third amplifier OP3 is connected to one end of a fifth resistor R5, and an output terminal of the third amplifier OP3 is connected to a common gate of the first common-gate current mirror circuit; the other end of the fourth resistor R4 and the other end of the fifth resistor R5 are grounded; the output end of the first current source for outputting the first current is connected with the inverting input end of the third amplifier OP3, and the output end of the second current source for outputting the second current is respectively connected with the non-inverting input end of the third amplifier OP3 and the input end of the first common gate mirror circuit; the output end of the first common-gate current mirror circuit is used for outputting a difference current.

It should be noted that, similar to the schematic illustration of fig. 13, fig. 14 only differs from the schematic illustration of fig. 13 in that the current flowing through the fourth resistor R4 and the fifth resistor R5 in fig. 14 is the first current, and the difference current output by the drain of the sixteenth PMOS transistor MP16 in the first common-gate current mirror is the first current minus the second current. In fig. 13, the current flowing through the fourth resistor R4 and the fifth resistor R5 is the second current, and the difference current outputted by the drain of the sixteenth PMOS transistor MP16 in the first common-gate current mirror is the second current minus the first current. That is, the differential current and the calculation formula of the temperature coefficient of the differential current of the present embodiment may refer to the above formula (9) and formula (10).

In one embodiment, as shown in fig. 15, on the basis of fig. 3, the current operation circuit in the power supply circuit may further include: the fourth amplifier OP4, the first resistor circuit formed by connecting n sixth resistors R6 in parallel, the first diode circuit formed by connecting n fourth diodes D4 in parallel, and the second common-gate current mirror circuit; wherein:

the non-inverting input end of the fourth amplifier OP4 is connected to one end of the first resistor circuit, the output end of the first current source for outputting the first current, and the input end of the second common-gate mirror circuit, respectively, the inverting input end of the fourth amplifier OP4 is connected to the common anode of the first diode circuit, the output end of the second current source for outputting the second current, respectively, and the output end of the fourth amplifier OP4 is connected to the common gate of the second common-gate mirror circuit; the other end of the first resistor circuit is grounded with the common cathode of the first diode circuit; the output end of the second common-gate current mirror circuit is used for outputting differential current; and n is the ratio of the drain current of the sixth PMOS tube to the drain current of the seventh PMOS tube.

It should be noted that the second common-gate current mirror circuit in this embodiment may be the first common-gate current mirror circuit in fig. 13, or may be a current mirror circuit of another type, which is not limited in this embodiment. In fig. 15, the second common-gate current mirror circuit may be the first common-gate current mirror circuit in fig. 13.

It should be noted that, in the embodiment of the present invention, the operation principle of the operation circuit is as follows: in the case where the first current is not introduced, due to the linear resistance-voltage relationship of the first resistance circuit and the power-varying current-voltage relationship of the first diode, in the case where the voltage of the non-inverting input terminal and the voltage of the inverting input terminal of the fourth amplifier OP4 are kept the same, the current flowing through the first diode circuit is the same as the current flowing through the first resistance circuit, that is, the current flowing through the first diode circuit and the current flowing through the first resistance circuit are both the second current. At this time, if the first current is introduced, the fourth amplifier OP4 automatically adjusts the gate-source voltages of the sixteenth PMOS transistor MP16 and the fifteenth PMOS transistor MP15 to keep the voltage of the non-inverting input terminal and the voltage of the inverting input terminal of the fourth amplifier to be the same, so that the current in the first resistor circuit is still the second current. At this time, based on the flow direction of the first current and the flow direction of the second current on the first resistor circuit, the current at the input end of the second common-gate current mirror is the second current minus the first current. That is, the differential current and the calculation formula of the temperature coefficient of the differential current of the present embodiment can refer to the above formula (7) and formula (8).

In one embodiment, as shown in fig. 16, on the basis of fig. 2, the current operation circuit may further include: the third common-gate current mirror circuit comprises a fifth amplifier OP5, a third common-gate current mirror circuit, a second diode circuit formed by connecting m fifth diodes D5 in parallel, a second resistor circuit formed by connecting m seventh resistors R7 in parallel, and a third diode circuit formed by connecting m sixth diodes D6 in parallel; wherein:

the non-inverting input end of the fifth amplifier OP5 is respectively connected to one end of the second resistance circuit, the input end of the third common-gate current mirror circuit, and the output end of the second current output by the second current source; the inverting input end of the fifth amplifier OP5 is respectively connected with the output end of the first current source for outputting the first current and the common anode of the second diode circuit, and the output end of the fifth amplifier OP5 is connected with the common gate of the third common-gate current mirror circuit; the other end of the second resistor circuit is connected with the common anode of the third diode circuit; the common cathode of the second diode circuit and the common cathode of the third diode circuit are grounded; wherein, m is a ratio between the drain current of the fifth PMOS transistor MP5 and the drain current of the fourth PMOS transistor MP 4.

It should be noted that the third common-gate current mirror circuit in this embodiment may be the first common-gate current mirror circuit in fig. 13, or may be a current mirror circuit of another type, which is not limited in this embodiment. In fig. 16, the second common-gate current mirror circuit is shown as the first common-gate current mirror circuit in fig. 13. Meanwhile, in this embodiment, the ratio between the junction area of the first diode and the junction area of the second diode is the same as the ratio between the junction area of the fifth diode and the junction area of the sixth diode.

It should be noted that, the principle of fig. 16 and fig. 15 is similar to that of fig. 15, and the difference between the principle of fig. 16 and that of fig. 15 is only that, in fig. 15, the current flowing through the first resistor circuit and the first diode circuit is the second current, while in fig. 16, the current flowing through the second diode circuit and the current flowing through the second resistor circuit (or the third diode circuit) is the first current, and the difference current output by the drain of the sixteenth PMOS transistor MP16 is the first current minus the second current. That is, the differential current and the calculation formula of the temperature coefficient of the differential current of the present embodiment may refer to the above formula (9) and formula (10).

In one embodiment, as shown in fig. 17, the current operation circuit in the power supply circuit may be further multiplexed with a second current source circuit, which includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a sixth amplifier OP6, a third resistor circuit formed by connecting N eighth resistors R8 in parallel, and a fourth diode circuit formed by connecting N seventh diodes D7 in parallel.

A source electrode of the ninth PMOS transistor MP9, a source electrode of the tenth PMOS transistor MP10, and a source electrode of the eleventh PMOS transistor MP11 are connected to an output terminal of the fourth external voltage source, and a gate electrode of the ninth PMOS transistor MP9, a gate electrode of the tenth PMOS transistor MP10, and a gate electrode of the eleventh PMOS transistor MP11 are connected; the drain of the eleventh PMOS transistor MP11 is used for outputting the difference current. The non-inverting input end of the sixth amplifier OP6 is connected to the drain of the ninth PMOS transistor MP9 and one end of the third resistor circuit, the inverting input end of the sixth amplifier OP6 is connected to the drain of the tenth PMOS transistor MP10 and the common anode of the fourth diode circuit, and the output end of the sixth amplifier OP6 is connected between the gate of the ninth PMOS transistor MP9 and the gate of the tenth PMOS transistor MP 10; the other end of the third resistor circuit is grounded with the common cathode of the fourth diode circuit; the non-inverting input terminal of the sixth amplifier OP6 serves as the first input terminal of the current operation circuit and the second input terminal of the current operation circuit, and the inverting input terminal of the sixth amplifier OP6 serves as the first input terminal of the current operation circuit and the second input terminal of the current operation circuit. The flow direction of the first current with respect to the non-inverting input terminal of the sixth amplifier OP6 is opposite to the flow direction of the second current with respect to the non-inverting input terminal of the sixth amplifier OP 6; the first current flows in a direction opposite to the inverting input terminal of the sixth amplifier OP6 with respect to the second current flow in the inverting input terminal of the sixth amplifier OP 6. Wherein N is a positive integer greater than or equal to 1.

In this embodiment, the first current source circuit that generates the first current may adopt a structure as shown in fig. 2. It should be noted that, since the non-inverting input terminal and the inverting input terminal of the sixth amplifier OP6 both input the first current, based on this, a seventeenth PMOS transistor MP17 needs to be added on the basis of the first current source shown in fig. 2. Specifically, as shown in fig. 17, the source of the seventeenth PMOS transistor MP17 is connected to the output terminal of the second external voltage source Vdd2, the gate of the seventeenth PMOS transistor MP17 is connected to the gate of the third PMOS transistor, and the drain of the seventeenth PMOS transistor MP17 outputs the first current.

The working principle of the current operation circuit in this embodiment is as follows: if the first current is not introduced, due to the linear resistance-voltage relationship of the third resistance circuit and the power-varying current-voltage relationship of the fourth diode circuit, in the case where the voltage at the non-inverting input terminal and the voltage at the inverting input terminal of the sixth amplifier OP6 remain the same, the current flowing through the third resistance circuit is the same as the current flowing through the fourth diode circuit and is the second current generated by the second current source circuit. In the case of introducing the first current, the sixth amplifier OP6, in order to maintain the voltage at the non-inverting input terminal and the voltage at the inverting input terminal to be the same, automatically adjusts the gate-source voltages of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10, so that the current flowing through the third resistor circuit is still the second current, and the current flowing through the fourth diode circuit is also still the second current. At this time, based on the flow direction of the first current, the flow direction of the second current in the third resistance circuit, the flow direction of the first current, and the flow direction of the second current in the fourth resistance circuit, the drain currents of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 in the second current source circuit are both the second current minus the first current. Further, the drain current of the eleventh PMOS transistor MP11 is the second current minus the first current.

Note that, in this embodiment, the second current is represented by I_CTAT＝N(1+KΔT)I_S2. Correspondingly, the differential current is denoted as I_out＝I_CTAT-I_PTAT＝N(1+KΔT)I_S2-m(1+JΔT)I_S1. Correspondingly, the difference current I_outIs expressed as

In addition, for the explanation of the difference current and the temperature coefficient in this embodiment, see the above-described formula (7) and formula (8). Meanwhile, N can be set according to actual requirements.

In the embodiment, the current operation circuit and the second current source circuit are multiplexed, so that the number of components in the current operation circuit can be reduced, the hardware cost is reduced, and the electrical influence among the components is avoided. For example, in comparison with the embodiment shown in fig. 16, the power supply circuit of the present embodiment requires only two amplifiers, and does not require three amplifiers.

In one embodiment, as shown in fig. 18, the current operation circuit in the power supply circuit may be further multiplexed with a first current source circuit, where the first current source circuit includes a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a seventh amplifier OP7, a fourth resistor circuit formed by connecting M ninth resistors R9 in parallel, a fifth diode circuit formed by connecting M ninth diodes D9 in parallel, and a sixth diode circuit formed by connecting M eighth diodes D8 in parallel; a source electrode of the twelfth PMOS tube MP12, a source electrode of the thirteenth PMOS tube MP13 and a source electrode of the fourteenth PMOS tube MP14 are connected to the output end of the fifth external voltage source Vdd5, and a gate electrode of the twelfth PMOS tube MP12, a gate electrode of the thirteenth PMOS tube MP13 and a gate electrode of the fourteenth PMOS tube MP14 are connected; the drain electrode of the twelfth PMOS tube MP12 is used for outputting differential current; an output end of the seventh amplifier OP7 is connected between the gate of the thirteenth PMOS transistor MP13 and the gate of the fourteenth PMOS transistor MP 14; the non-inverting input terminal of the seventh amplifier OP7 is connected to the drain of the fourteenth PMOS transistor MP14 and one end of the fourth resistor circuit, respectively, and the inverting input terminal of the seventh amplifier OP7 is connected to the drain of the thirteenth PMOS transistor MP13 and the common anode of the sixth diode circuit, respectively; the other end of the fourth resistor circuit is connected with the common anode of the fifth diode circuit; the common cathode of the sixth diode circuit and the common cathode of the fifth diode circuit are grounded; the non-inverting input terminal of the seventh amplifier OP7 is used as the first input terminal of the current operation circuit and the second input terminal of the current operation circuit, and the inverting input terminal of the seventh amplifier OP7 is used as the first input terminal of the current operation circuit and the second input terminal of the current operation circuit; the flow direction of the first current with respect to the non-inverting input terminal of the seventh amplifier OP7 is opposite to the flow direction of the second current with respect to the non-inverting input terminal of the seventh amplifier OP 7; the flow direction of the first current with respect to the inverting input terminal of the seventh amplifier OP7 is opposite to the flow direction of the second current with respect to the inverting input terminal of the seventh amplifier OP 7; wherein M is a positive integer greater than or equal to 1.

In this embodiment, the second current source circuit that generates the first current may adopt a structure as shown in fig. 3. It should be noted that, since the non-inverting input terminal and the inverting input terminal of the seventh amplifier OP7 both input the second current, based on this, an eighteenth PMOS transistor MP18 needs to be added on the basis of the second current source shown in fig. 3. Specifically, as shown in fig. 18, the source of the eighteenth PMOS transistor MP18 is connected to the output terminal of the third external voltage source Vdd3, the gate of the eighteenth PMOS transistor MP18 is connected to the gate of the sixth PMOS transistor MP6, and the drain of the eighteenth PMOS transistor MP18 outputs the second current.

It should be noted that fig. 17 is similar to the principle description of fig. 18, and is not repeated here. In addition, in the present embodiment, the first current is represented as I_PTAT＝M(1+JΔT)I_S1While the difference current is the first current minus the second current, i.e. I_out＝I_PTAT-I_CTAT＝M(1+JΔT)I_S1-n(1+KΔT)I_S2. Correspondingly, the difference current I_outThe temperature coefficient of (d) is expressed as:

in addition, M can be set according to actual requirements.

In one embodiment, as shown in fig. 11, the power circuit provided in the embodiment of the present invention further includes a current-to-voltage circuit. The current-to-voltage circuit is configured to: receiving a difference current I_outAnd outputs the difference current I_outProportional voltage V_out。

In one example, the current to voltage circuit passes the difference current I through a zero temperature coefficient resistor R3_outAnd converting into and voltage output.

It should be noted that the current-to-voltage circuit may also replace the zero temperature coefficient resistor by a zero temperature coefficient resistor network, or a zero temperature coefficient complex circuit including a buffer stage or a proportional amplifier.

In one example, based on the above description shown in fig. 7, the power circuit provided by the present invention can also be shown in fig. 12.

In this embodiment, since the mI is set according to_S1And nI_S2Can be of such a relative size that I_outIs larger than the positive temperature coefficient of the first current source circuit or is smaller than the negative temperature coefficient of the second current source circuit. Thus, V as described above_outAlso according to the set mI_S1And nI_S2Relative size of (a) such that V_outThe corresponding temperature coefficient is greater than the positive temperature coefficient of the first current source circuit or less than the negative temperature coefficient of the second current source circuit.

< electric device >

The embodiment of the utility model provides a still provide an electric equipment, this electric equipment includes the power supply circuit that any above-mentioned embodiment provided.

While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.

Claims

1. A power supply circuit, comprising:

2. The power supply circuit according to claim 1, wherein the first current source circuit is a bandgap reference current source circuit; and/or the second current source circuit is a diode type current source circuit.

3. The power supply circuit according to claim 1, wherein the current operation circuit includes a first current mirror circuit, an input terminal of which is the second input terminal, connected to an output terminal of the second current source, which outputs the second current; the output end of the first current mirror circuit is connected to the first input end, so that the flow direction of the first current relative to the first input end is opposite to the flow direction of the mirror image current of the second current relative to the first input end.

4. A power supply circuit according to claim 3, wherein the current operation circuit includes a second current mirror circuit having an input terminal as the first input terminal, the difference current being obtained; and the output end of the second current mirror circuit outputs the mirror current of the difference current.

5. The power supply circuit according to claim 4, wherein the second current mirror circuit comprises a first PMOS transistor, a second PMOS transistor; wherein:

6. The power supply circuit according to claim 4, wherein the second current mirror circuit comprises a first NMOS transistor, a second NMOS transistor; wherein:

7. The power supply circuit according to claim 3, wherein the first current mirror circuit comprises a third NMOS transistor, a fourth NMOS transistor; wherein:

8. The power supply circuit according to claim 2, wherein the bandgap reference current source circuit comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first amplifier, a first diode, a second diode, and a first resistor; wherein:

the first resistor is connected between the drain electrode of the fourth PMOS tube and the anode of the second diode, and the cathode of the second diode is grounded;

9. The power supply circuit according to claim 2, wherein the diode-type current source circuit comprises a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a second amplifier, a third diode, and a second resistor; wherein:

10. The power supply circuit according to claim 1, wherein the current operation circuit comprises: a third amplifier, a fourth resistor, a fifth resistor and a first common gate current mirror circuit; wherein:

the non-inverting input end of the third amplifier is connected with one end of the fourth resistor, the inverting input end of the third amplifier is connected with one end of the fifth resistor, and the output end of the third amplifier is connected with the common gate of the first common-gate current mirror circuit;

the other end of the fourth resistor and the other end of the fifth resistor are grounded;

the output end of the first current source for outputting the first current is respectively connected with the non-inverting input end of the third amplifier and the input end of the first common-gate current mirror circuit, and the output end of the second current source for outputting the second current is connected with the inverting input end of the third amplifier; alternatively, the first and second electrodes may be,

the output end of the first current source for outputting the first current is connected with the inverting input end of the third amplifier, and the output end of the second current source for outputting the second current is respectively connected with the non-inverting input end of the third amplifier and the input end of the first common gate mirror circuit;

the output end of the first common-gate current mirror circuit is used for outputting the difference current.

11. The power supply circuit according to claim 9, wherein the current operation circuit comprises: the fourth amplifier, a first resistor circuit formed by connecting n sixth resistors in parallel, a first diode circuit formed by connecting n fourth diodes in parallel, and a second common-gate current mirror circuit; wherein:

a non-inverting input terminal of the fourth amplifier is connected to one end of the first resistor circuit, an output terminal of the first current source outputting the first current, and an input terminal of the second common-gate current mirror circuit, respectively, an inverting input terminal of the fourth amplifier is connected to a common anode of the first diode circuit, an output terminal of the second current source outputting the second current, respectively, and an output terminal of the fourth amplifier is connected to a common gate of the second common-gate current mirror circuit;

the other end of the first resistor circuit is grounded with the common cathode of the first diode circuit;

the output end of the second common-gate current mirror circuit is used for outputting the difference current;

n is the ratio of the drain current of the sixth PMOS tube to the drain current of the seventh PMOS tube.

12. The power supply circuit according to claim 8, wherein the current operation circuit includes a fifth amplifier, a third common-gate current mirror circuit, a second diode circuit formed by connecting m fifth diodes in parallel, a second resistor circuit formed by connecting m seventh resistors in parallel, and a third diode circuit formed by connecting m sixth diodes in parallel; wherein:

the non-inverting input end of the fifth amplifier is respectively connected with one end of the second resistance circuit, the input end of the third common-gate current mirror circuit and the output end of the second current output by the second current source; the inverting input end of the fifth amplifier is respectively connected with the output end of the first current source for outputting the first current and the common anode of the second diode circuit, and the output end of the fifth amplifier is connected with the common gate of the third common-gate current mirror circuit;

the other end of the second resistor circuit is connected with the common anode of the third diode circuit;

the common cathode of the second diode circuit and the common cathode of the third diode circuit are grounded;

and m is the ratio of the drain current of the fifth PMOS tube to the drain current of the fourth PMOS tube.

13. The power supply circuit according to claim 1, wherein the current operation circuit is multiplexed with the second current source circuit, and the second current source circuit comprises a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a sixth amplifier, a third resistor circuit formed by connecting N eighth resistors in parallel, and a fourth diode circuit formed by connecting N seventh diodes in parallel;

a source electrode of the ninth PMOS tube, a source electrode of the tenth PMOS tube and a source electrode of the eleventh PMOS tube are connected to an output end of a fourth external voltage source, and a grid electrode of the ninth PMOS tube, a grid electrode of the tenth PMOS tube and a grid electrode of the eleventh PMOS tube are connected; the drain electrode of the eleventh PMOS tube is used for outputting the difference current;

the non-inverting input end of the sixth amplifier is connected to the drain of the ninth PMOS transistor and one end of the third resistor circuit, the inverting input end of the sixth amplifier is connected to the drain of the tenth PMOS transistor and the common anode of the fourth diode circuit, and the output end of the sixth amplifier is connected between the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor;

the other end of the third resistor circuit is grounded with the common cathode of the fourth diode circuit;

the non-inverting input terminal of the sixth amplifier serves as the first input terminal of the current operational circuit and the second input terminal of the current operational circuit, and the inverting input terminal of the sixth amplifier serves as the first input terminal of the current operational circuit and the second input terminal of the current operational circuit;

the first current flows in a direction opposite to the direction of the second current with respect to the non-inverting input of the sixth amplifier; the first current flows in a direction opposite to the direction of the second current with respect to the inverting input terminal of the sixth amplifier;

wherein N is a positive integer greater than or equal to 1.

14. The power supply circuit according to claim 1, wherein the current operation circuit is multiplexed with the first current source circuit, and the first current source circuit comprises a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a seventh amplifier, a fourth resistor circuit formed by connecting M ninth resistors in parallel, a fifth diode circuit formed by connecting M ninth diodes in parallel, and a sixth diode circuit formed by connecting M eighth diodes in parallel;

a source electrode of the twelfth PMOS tube, a source electrode of the thirteenth PMOS tube and a source electrode of the fourteenth PMOS tube are connected to an output end of a fifth external voltage source, and a grid electrode of the twelfth PMOS tube, a grid electrode of the thirteenth PMOS tube and a grid electrode of the fourteenth PMOS tube are connected; the drain electrode of the twelfth PMOS tube is used for outputting the difference current;

the output end of the seventh amplifier is connected between the grid electrode of the thirteenth PMOS tube and the grid electrode of the fourteenth PMOS tube; the non-inverting input end of the seventh amplifier is connected to the drain of the fourteenth PMOS tube and one end of the fourth resistor circuit respectively, and the inverting input end of the seventh amplifier is connected to the drain of the thirteenth PMOS tube and the common anode of the sixth diode circuit respectively;

the other end of the fourth resistor circuit is connected with the common anode of the fifth diode circuit;

the common cathode of the sixth diode circuit and the common cathode of the fifth diode circuit are grounded;

the non-inverting input terminal of the seventh amplifier serves as the first input terminal of the current operation circuit and the second input terminal of the current operation circuit, and the inverting input terminal of the seventh amplifier serves as the first input terminal of the current operation circuit and the second input terminal of the current operation circuit;

the first current flows in a direction opposite to the direction of the second current flowing in the non-inverting input of the seventh amplifier; the first current flows in a direction opposite to the direction of the second current with respect to the inverting input terminal of the seventh amplifier;

wherein M is a positive integer greater than or equal to 1.

15. The power supply circuit according to any one of claims 1 to 14, wherein the power supply circuit further comprises a current-to-voltage circuit;

16. The power supply circuit of claim 15, wherein the current to voltage circuit converts the difference current to a voltage output through a zero temperature coefficient resistance.

17. An electrical consumer, characterized in that the electrical consumer comprises a power supply circuit according to any one of claims 1-16.