CN210324185U - Multi-channel signal indicating circuit - Google Patents
Multi-channel signal indicating circuit Download PDFInfo
- Publication number
- CN210324185U CN210324185U CN201921357732.0U CN201921357732U CN210324185U CN 210324185 U CN210324185 U CN 210324185U CN 201921357732 U CN201921357732 U CN 201921357732U CN 210324185 U CN210324185 U CN 210324185U
- Authority
- CN
- China
- Prior art keywords
- multiplexer
- signal
- pin
- flop
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000011664 signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The utility model discloses a multipath signal indicating circuit, which is characterized by comprising a multiplexer, a selection signal generating module and an indicating module; the signal input end of the multiplexer is connected with an indication control signal, and the signal output end of the multiplexer is connected with the input end of the indication module; the selection signal generation module comprises an oscillator, a D-type flip-flop U0 and a D-type flip-flop U1; the output end of the oscillator is connected with the CK end of the D-type flip-flop U0; of U0
End connection D typeThe CK terminal of flip-flop U1; the Q terminal of U0 is connected to the first selection signal input terminal of the multiplexer, and the Q terminal of U1 is connected to the second selection signal input terminal of the multiplexer. The multiplexer selection signal is generated by the oscillator and the serially connected double-D type trigger, so that the use number of the LED indicator lamps is reduced and the occupied space of the panel is saved under the condition that the space of the server panel is limited.
Description
Technical Field
The utility model relates to a server wiring field, concretely relates to multichannel signal indication circuit.
Background
For a network controller in a server, the current connection state and the data transceiving state need to be indicated through an LED indicator lamp. The existing server network controller usually adopts a multi-port network controller, and the current data receiving and transmitting state of each port of the network controller needs to be indicated through different LED indicating lamps, so that a plurality of LED indicating lamps need to be placed on a server panel.
However, the increasing density of server interfaces results in limited server panel space, and therefore, the multiport network controller LED indicator lights can occupy limited server panel space.
Disclosure of Invention
In order to solve the problem, the utility model provides a multichannel signal indication circuit switches input signal through the multiplexer circulation, reduces pilot lamp quantity, has saved server panel occupation space.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a multi-path signal indicating circuit comprises a multiplexer, a selection signal generating module and an indicating module;
the signal input end of the multiplexer is connected with an indication control signal, and the signal output end of the multiplexer is connected with the input end of the indication module;
the selection signal generation module comprises an oscillator, a D-type flip-flop U0 and a D-type flip-flop U1; the output end of the oscillator is connected with the CK end of the D-type flip-flop U0; of U0
The end is connected with the CK end of the D-type trigger U1; the Q terminal of U0 is connected to the first selection signal input terminal of the multiplexer, and the Q terminal of U1 is connected to the second selection signal input terminal of the multiplexer.
Further, the Q end of the D-type flip-flop U0 outputs a clock square wave Q0, the T end of U0 is set to be 1, and the CL end of U0 is grounded;
the Q end of the D-type flip-flop U1 outputs a clock square wave Q1, the T end of U1 is set to be 1, and the CL end of U1 is grounded.
Further, the oscillator outputs a 4Hz clock square wave.
Further, the input end of the indicating module is connected with a light emitting diode through an inverter.
Further, the inverter is NC7WZ 14.
Furthermore, one path of the input end of the indication module is connected with a P3V3_ AUX signal through a resistor R1, one path of the input end of the indication module is connected with an inverter pin 1, an inverter pin 2 is grounded, one path of the inverter pin 5 is connected with a P3V3_ AUX signal, and the other path of the input end of the indication module is grounded through a capacitor C1; the inverter pin 6 is connected to the light emitting diode through a resistor R3, and the inverter pin 1 and the pin 6 are connected through a resistor R2.
Furthermore, the multiplexer is 74HC4052, pins 1Y3, 1Y2, 1Y1 and 1Y0 of the multiplexer are respectively connected to one path of LED control signals, a pin S1 is connected to the clock square wave Q1, a pin S0 is connected to the clock square wave Q0, a pin VCC is connected to the P3V3_ AUX signal, pins VEE, GND and E _ N are grounded, and a pin 1Z is connected to the input end of the indication module.
The utility model has the advantages that:
the utility model provides a multichannel signal indication circuit, through oscillator and the two D type trigger generation multiplexer select signal of establishing ties, after the oscillator starts to vibrate, the instruction module input signal circulates between four LED control signal and switches, reaches the effect of using single LED pilot lamp to instruct network controller four ways port data receiving and dispatching state, under the limited condition in server panel space, has reduced LED pilot lamp and has used quantity, has saved panel occupation space.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a selection signal generation module according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a multiplexer and an indicator block according to an embodiment of the present invention;
fig. 4 is a waveform diagram of a selection signal according to an embodiment of the present invention.
Detailed Description
In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.
As shown in fig. 1, an embodiment of the present invention provides a multi-path signal indicating circuit, which includes a multiplexer, a selection signal generating module and an indicating module; the signal input end of the multiplexer is connected with an indication control signal 1, an indication control signal 2, an indication control signal 3 and an indication control signal 4, and the signal output end of the multiplexer is connected with the input end of the indication module; two output ends of the selection signal generation module are respectively connected with two selection signal input ends of the multiplexer.
As shown in fig. 2, the selection signal generation module includes an oscillator, a D-type flip-flop U0 and a D-type flip-flop U1, wherein the output end of the oscillator outputs a 4Hz clock square wave and is connected to the CK end of the D-type flip-flop U0; of U0
The end is connected with the CK end of the D-type trigger U1; the Q terminal of U0 outputs a 2Hz clock square wave Q0 connected to the first select signal input terminal of the multiplexer, and the Q terminal of U1 outputs a 1Hz clock square wave Q1 connected to the second select signal input terminal of the multiplexer.
The T end of U0 is set to be 1, and the CL end of U0 is grounded; the T end of U1 is set to 1, and the CL end of U1 is grounded.
The input end of an indicating module of the multi-path signal indicating circuit is connected with a light emitting diode through an inverter.
Fig. 3 is a circuit diagram of a multiplexer and an indication module according to an embodiment of the present invention. The multiplexer is 74HC4052 in model, a clock square wave Q0 generated by the selection signal generation module is connected to a pin S0, a clock square wave Q1 is connected to a pin S1, pins 1Y3, 1Y2, 1Y1 and 1Y0 are respectively connected to one path of LED control signals, a VCC pin is connected to a P3V3_ AUX signal, pins VEE, GND and E _ N are grounded, one path of 1Z pin is connected to a P3V3_ AUX signal through a resistor R1, one path of 1Z pin is connected to a pin 1 of an inverter NC7WZ14, an inverter pin 2 is grounded, one path of 5 inverter pin is connected to a P3V3_ AUX signal, and the other path of the inverter pin is grounded through a capacitor C1; the inverter pin 6 is connected to the light emitting diode through a resistor R3, and the inverter pin 1 and the pin 6 are connected through a resistor R2.
When the embodiment is used, the multiplexer path is switched according to the control signal generated by the selection signal generating module, and a signal waveform diagram is shown in fig. 4. The oscillator generates 4Hz counting pulses, frequency division is carried out through two serially connected D-type triggers, 2Hz clock square waves Q0 and 1Hz clock square waves Q1 are obtained, Q0 and Q1 are combined into 2-bit circulating signals after being collocated, after the oscillator starts oscillation, the output pin 1Z of the multiplexer is circularly switched among four LED control signals 1Y 0-1Y 3 at intervals of once per second, and the purpose that a single LED indicator lamp is used for indicating the data receiving and sending state of the four-port network is achieved.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, the scope of the present invention is not limited thereto. Various modifications and alterations will occur to those skilled in the art based on the foregoing description. And are neither required nor exhaustive of all embodiments. On the basis of the technical scheme of the utility model, various modifications or deformations that technical personnel in the field need not pay out creative work and can make still are within the protection scope of the utility model.
Claims (7)
1. A multi-path signal indicating circuit is characterized by comprising a multiplexer, a selection signal generating module and an indicating module;
the signal input end of the multiplexer is connected with an indication control signal, and the signal output end of the multiplexer is connected with the input end of the indication module;
the selection signal generation module comprisesAn oscillator, a D-type flip-flop U0, and a D-type flip-flop U1; the output end of the oscillator is connected with the CK end of the D-type flip-flop U0; of U0
The end is connected with the CK end of the D-type trigger U1; the Q terminal of U0 is connected to the first selection signal input terminal of the multiplexer, and the Q terminal of U1 is connected to the second selection signal input terminal of the multiplexer.
2. The multi-way signal indicating circuit of claim 1, wherein the Q end of the D-type flip-flop U0 outputs a clock square wave Q0, the T end of U0 is set to 1, and the CL end of U0 is grounded;
the Q end of the D-type flip-flop U1 outputs a clock square wave Q1, the T end of U1 is set to be 1, and the CL end of U1 is grounded.
3. The multiple signal indicating circuit of claim 2, wherein said oscillator outputs a 4Hz clock square wave.
4. The multi-signal indicating circuit of claim 3, wherein the input terminal of the indicating module is connected to the light emitting diode through an inverter.
5. The multi-channel signaling circuit of claim 4 wherein said inverter is NC7WZ 14.
6. The multi-channel signal indicating circuit of claim 5, wherein one channel of the input end of the indicating module is connected to the P3V3_ AUX signal through a resistor R1, the other channel is connected to the inverter pin 1, the inverter pin 2 is grounded, the inverter pin 5 is connected to the P3V3_ AUX signal, and the other channel is grounded through a capacitor C1; the inverter pin 6 is connected to the light emitting diode through a resistor R3, and the inverter pin 1 and the pin 6 are connected through a resistor R2.
7. The multi-channel signal indicating circuit of claim 6, wherein the multiplexer is 74HC4052, pins 1Y3, 1Y2, 1Y1 and 1Y0 of the multiplexer are respectively connected with a channel of LED control signals, a pin S1 is connected with a clock square wave Q1, a pin S0 is connected with a clock square wave Q0, a pin VCC is connected with a signal P3V3_ AUX, pins VEE, GND and E _ N are grounded, and a pin 1Z is connected with the input end of the indicating module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921357732.0U CN210324185U (en) | 2019-08-21 | 2019-08-21 | Multi-channel signal indicating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921357732.0U CN210324185U (en) | 2019-08-21 | 2019-08-21 | Multi-channel signal indicating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210324185U true CN210324185U (en) | 2020-04-14 |
Family
ID=70130745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921357732.0U Active CN210324185U (en) | 2019-08-21 | 2019-08-21 | Multi-channel signal indicating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210324185U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114007315A (en) * | 2021-12-31 | 2022-02-01 | 博为科技有限公司 | Ethernet port indicator lamp control circuit and control method |
| CN115129561A (en) * | 2022-07-28 | 2022-09-30 | 苏州浪潮智能科技有限公司 | Server chip state indicating device |
-
2019
- 2019-08-21 CN CN201921357732.0U patent/CN210324185U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114007315A (en) * | 2021-12-31 | 2022-02-01 | 博为科技有限公司 | Ethernet port indicator lamp control circuit and control method |
| CN114007315B (en) * | 2021-12-31 | 2022-05-10 | 博为科技有限公司 | Ethernet port indicator lamp control circuit and control method |
| CN115129561A (en) * | 2022-07-28 | 2022-09-30 | 苏州浪潮智能科技有限公司 | Server chip state indicating device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN210324185U (en) | Multi-channel signal indicating circuit | |
| US10198396B2 (en) | Master control board that switches transmission channel to local commissioning serial port of the master control board | |
| CN110795317A (en) | Method and system for realizing lighting of self-adaptive hard disk backboard by using CPLD (complex programmable logic device) | |
| CN104639375A (en) | Interface management method and network equipment | |
| CN104424154A (en) | Universal Spi (serial Peripheral Interface) | |
| EP3200089B1 (en) | Method, apparatus, communication equipment and storage media for determining link delay | |
| CN208044591U (en) | A kind of switching device and server that SATA and PCIE is shared | |
| CN109116829B (en) | The triggering implementation method and automatic test equipment of automatic test equipment | |
| CN109828872A (en) | Signal-testing apparatus and method | |
| CN111538689A (en) | Multi-channel PCIE (peripheral component interface express) adapter card with two heterogeneous ends | |
| US6215817B1 (en) | Serial interface device | |
| CN105376659A (en) | An optical back board component and a communication apparatus | |
| CN111313869B (en) | Clock switching circuit of gigabit Ethernet transceiver | |
| CN104460857A (en) | Peripheral component interconnect-express card and method and device for using same | |
| CN211149445U (en) | High-speed data processing platform | |
| CN108646172B (en) | Chip testing device | |
| CN110879673A (en) | Infrared touch screen cascade device | |
| CN114168506B (en) | Multi-channel DMA control transmission device | |
| CN211956461U (en) | Serial data communication circuit and system | |
| CN101192848B (en) | Method and system for realizing the master/slave single board dual-host reset and online information | |
| CN109561032A (en) | A kind of switch module and the interchanger including it | |
| CN101738548A (en) | Clock pulse detecting circuit and clock pulse supply device | |
| US6269414B1 (en) | Data rate doubler for electrical backplane | |
| CN208706214U (en) | The indicator light circuit of synchronous serial interface and switch or router comprising this circuit | |
| CN108009113B (en) | Method for realizing debugging serial port in double-master control system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |