CN210075747U - Multilayer substrate - Google Patents
Multilayer substrate Download PDFInfo
- Publication number
- CN210075747U CN210075747U CN201790001317.4U CN201790001317U CN210075747U CN 210075747 U CN210075747 U CN 210075747U CN 201790001317 U CN201790001317 U CN 201790001317U CN 210075747 U CN210075747 U CN 210075747U
- Authority
- CN
- China
- Prior art keywords
- conductor pattern
- base material
- multilayer substrate
- conductor
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 95
- 239000004020 conductor Substances 0.000 claims abstract description 209
- 239000000463 material Substances 0.000 claims abstract description 130
- 238000003825 pressing Methods 0.000 claims abstract description 53
- 238000000576 coating method Methods 0.000 claims abstract description 38
- 239000011248 coating agent Substances 0.000 claims abstract description 34
- 229920005992 thermoplastic resin Polymers 0.000 claims abstract description 25
- 229920005989 resin Polymers 0.000 claims description 46
- 239000011347 resin Substances 0.000 claims description 46
- 238000003475 lamination Methods 0.000 claims description 39
- 229920001187 thermosetting polymer Polymers 0.000 claims description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 239000011889 copper foil Substances 0.000 claims description 16
- 238000004804 winding Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 49
- 238000000034 method Methods 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000009413 insulation Methods 0.000 description 8
- 229920000106 Liquid crystal polymer Polymers 0.000 description 7
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000003638 chemical reducing agent Substances 0.000 description 5
- 238000006073 displacement reaction Methods 0.000 description 5
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 3
- 239000005751 Copper oxide Substances 0.000 description 3
- 229910000431 copper oxide Inorganic materials 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229920006332 epoxy adhesive Polymers 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000002485 formyl group Chemical class [H]C(*)=O 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000003856 thermoforming Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/29—Terminals; Tapping arrangements for signal inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/32—Insulating of coils, windings, or parts thereof
- H01F27/323—Insulation between winding turns, between winding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/041—Printed circuit coils
- H01F41/042—Printed circuit coils by thin film techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
- H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
- H01F41/12—Insulating of windings
- H01F41/122—Insulating between turns or between winding layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2809—Printed windings on stacked layers
Abstract
A multilayer substrate (1) is provided with: the printed circuit board comprises a 1 st base material (11) made of thermoplastic resin, a 1 st conductor pattern (21) formed on the 1 st base material (11), a 2 nd base material (12) made of thermoplastic resin, and a 2 nd conductor pattern (22) formed on the 2 nd base material (12). An insulating coating (31) covering the 1 st conductor pattern (21) is partially disposed between the 1 st base material (11) and the 2 nd base material (12). The insulating film (31) is made of a material having lower fluidity at a predetermined pressing temperature than the 1 st base material (11) and the 2 nd base material (12), and a plurality of base materials including the 1 st base material (11) and the 2 nd base material (12) are stacked and thermally pressed at the pressing temperature.
Description
Technical Field
The present invention relates to a multilayer substrate formed by stacking base materials made of thermoplastic resin.
Background
A multilayer substrate formed by laminating a plurality of resin base materials on which a predetermined conductor pattern is formed is used, for example, as a coil device or an inductor. Patent document 1 discloses a planar inductor formed on such a multilayer substrate. In patent document 1, a multilayer substrate is configured by attaching a copper foil to a polyimide film, etching the copper foil, etc., to form a conductor pattern, and laminating and thermocompression bonding these substrates.
Prior art documents
Patent document
Patent document 1: JP-A4-368105
SUMMERY OF THE UTILITY MODEL
Problem to be solved by utility model
As a method for manufacturing a resin multilayer substrate, a collective lamination method using thermoplastic resin substrates is simple in manufacturing process.
In the above process, the thermoplastic resin base material flows during the thermoforming, and the conductor pattern formed on the thermoplastic resin base material also flows together. Therefore, the conductor patterns are inclined or displaced, and there is a possibility that the adjacent conductor patterns are short-circuited with each other.
On the other hand, if the spacing between adjacent conductor patterns is increased in advance to avoid short-circuiting between the conductor patterns, the element size increases.
Therefore, an object of the present invention is to provide a multilayer substrate in which conductor patterns are densified to avoid an increase in the size of an element and in which short circuits between the conductor patterns are prevented.
Means for solving the problems
(1) The utility model discloses a multilayer substrate's characterized in that possesses:
a 1 st base material made of a thermoplastic resin;
a 1 st conductor pattern formed on the upper surface of the 1 st base material;
a 2 nd base material made of a thermoplastic resin;
a 2 nd conductor pattern formed on the upper surface of the 2 nd base material; and
an insulating coating film made of a material having lower fluidity at a predetermined pressing temperature than the 1 st base material and the 2 nd base material, partially disposed between the 1 st base material and the 2 nd base material, and covering the 1 st conductor pattern,
the 2 nd base material is in contact with the upper surface of the 1 st base material, the 1 st conductor pattern and the 2 nd conductor pattern are conductors closest to each other in the lamination direction,
a plurality of base materials including the 1 st base material and the 2 nd base material are stacked and thermocompression bonded at the pressing temperature.
With the above configuration, even if the 1 st base material and the 2 nd base material soften and flow at the pressing temperature, the insulating coating is less likely to soften and flow, and therefore stable insulating properties can be maintained. Further, since the insulating coating is partially disposed between the 1 st base material and the 2 nd base material, the adhesion between the 1 st base material and the 2 nd base material is not greatly inhibited. Further, since the insulating coating covers the 1 st conductor pattern, that is, since the resin that easily flows is not interposed between the insulating coating and the 1 st conductor pattern, the 1 st conductor pattern is effectively protected by the insulating coating.
(2) The 1 st conductor pattern and the 2 nd conductor pattern may be shifted from each other in a plan view. In this structure, the inclination and displacement of the 1 st conductor pattern and the 2 nd conductor pattern are likely to occur along with the resin flow, but the insulation property can be maintained even in this case.
(3) The 1 st conductor pattern and the 2 nd conductor pattern may partially overlap in a plan view. Thus, the 1 st conductor pattern and the 2 nd conductor pattern can be arranged in the laminate at high density, and the multilayer substrate can be miniaturized. In this structure, the 1 st conductor pattern and the 2 nd conductor pattern are easily accessible due to inclination and displacement of the 1 st conductor pattern and the 2 nd conductor pattern accompanying the resin flow, but the insulation properties can be maintained even in this case.
(4) Preferably, the 1 st conductor pattern and the 2 nd conductor pattern are copper foil patterns. According to this structure, the conductor loss of the conductor pattern is reduced, and the formation of the conductor pattern and the insulating coating film is facilitated.
(5) Preferably, the insulating coating is an oxide film formed on a surface of the copper foil. With this configuration, it is not necessary to newly coat and form a film made of a material different from that of the conductor pattern on the conductor pattern, and the formation of the insulating coating film is facilitated. In addition, a thin insulating film is easily formed.
(6) Further preferably, the insulating coating film is a film of a thermosetting resin that is thermally cured at a temperature lower than the pressing temperature. In this configuration, in particular, the insulating coating film can be formed by attaching a thin film of a thermosetting resin to the 1 st substrate or the 2 nd substrate, and therefore, the formation of the insulating coating film is facilitated. Further, by continuously covering adjacent conductor patterns with a thermosetting resin along the substrate, the relative positional relationship between the 1 st conductor pattern and the 2 nd conductor pattern is easily maintained via the thermosetting film.
(7) The 1 st conductor pattern and the 2 nd conductor pattern are, for example, coil patterns having a winding axis in the direction of the lamination. With this configuration, in the case of obtaining a coil device having a large number of turns while achieving miniaturization, or in the case of obtaining an inductor having a large inductance per unit volume, a structure is provided in which short-circuiting is not easily caused even if the 1 st conductor pattern and the 2 nd conductor pattern are formed at high density.
Effect of the utility model
According to the present invention, a multilayer substrate in which short circuits between conductor patterns are prevented while avoiding an increase in the size of an element by increasing the density of the conductor patterns can be obtained.
Drawings
Fig. 1 is a perspective view of a multilayer substrate 1 according to embodiment 1.
Fig. 2(a) and 2(B) are partial sectional views showing the internal structure of the multilayer substrate 1.
Fig. 3(a) and 3(B) are partial sectional views of the multilayer substrate 2 according to embodiment 2.
Fig. 4(a) and 4(B) are partial sectional views of the multilayer substrate 3 according to embodiment 3.
Fig. 5(a) and 5(B) are partial sectional views of the multilayer substrate 4 according to embodiment 4.
Fig. 6 is an exploded perspective view of the multilayer substrate 5 according to embodiment 5.
Fig. 7 is a flowchart showing a process of manufacturing the multilayer substrate according to embodiment 6.
Fig. 8(a) is a cross-sectional view of the multilayer substrate 6 according to embodiment 6 at a stage before lamination and pressing of a plurality of base materials. Fig. 8(B) is a sectional view after lamination pressing.
Fig. 9(a) is a cross-sectional view of the multilayer substrate 7 according to embodiment 7 at a stage before lamination and pressing of a plurality of base materials. Fig. 9(B) is a sectional view after lamination pressing.
Fig. 10(a) is a cross-sectional view of the multilayer substrate 8 according to embodiment 8 at a stage before lamination and pressing of a plurality of base materials. Fig. 10(B) is a sectional view after lamination pressing.
Fig. 11(a) is a cross-sectional view of the multilayer substrate 9 according to embodiment 9 at a stage before lamination and pressing of a plurality of base materials. Fig. 11(B) is a sectional view at a halfway stage before the lamination pressing. Fig. 11(C) is a sectional view after the lamination pressing.
Detailed Description
Hereinafter, a plurality of modes for carrying out the present invention will be described by referring to specific examples. The same reference numerals are given to the same parts in the drawings. In view of ease of explanation or understanding of the points, the embodiments are shown separately for the sake of convenience, but partial replacement or combination of the structures shown in different embodiments is possible. In embodiment 2 and thereafter, descriptions of common matters with embodiment 1 are omitted, and only differences will be described. In particular, the same operational effects produced by the same structure will not be mentioned in each embodiment.
EXAMPLE 1 embodiment
Fig. 1 is a perspective view of a multilayer substrate 1 according to embodiment 1. Fig. 2(a) and 2(B) are partial sectional views showing the internal structure of the multilayer substrate 1. Fig. 2(a) is a sectional view in a stage before lamination pressing of a plurality of base materials. Fig. 2(B) is a cross-sectional view after lamination pressing, which is a cross-sectional view of a portion a-a in fig. 1.
The multilayer substrate 1 has a rectangular parallelepiped appearance. The multilayer board 1 is formed by stacking a 2 nd base material 12 and a 3 rd base material 13 in this order with a 1 st base material 11 as the lowermost layer. The 1 st base material 11, the 2 nd base material 12, and the 3 rd base material 13 are made of thermoplastic resin. In the present embodiment, the number of stacked substrates is reduced in consideration of the clarity of the drawings and the ease of description.
In the direction shown in fig. 2(a), a 1 st conductive pattern 21 is formed on the upper surface of the 1 st base material 11, and a 2 nd conductive pattern 22 is formed on the upper surface of the 2 nd base material 12. Further, an insulating coating 31 is formed on the surface of the 1 st conductor pattern 21. Similarly, an insulating coating 32 is formed on the surface of the 2 nd conductor pattern 22.
As described above, the multilayer substrate 1 of the present embodiment includes: the 1 st conductor pattern 21; a 1 st base material 11 formed with the 1 st conductor pattern and made of a thermoplastic resin; the 2 nd conductor pattern 22; a 2 nd base material 12 formed with the 2 nd conductor pattern and made of a thermoplastic resin; and an insulating coating 31 that is partially disposed between the 1 st base material 11 and the 2 nd base material 12 and covers the 1 st conductor pattern 21.
Each of the substrates 11, 12, 13 is a thermoplastic resin such as a Liquid Crystal Polymer (LCP). The conductor patterns 21 and 22 are formed by patterning copper foils, and the insulating coatings 31 and 32 are electrically insulating copper oxide films formed on the surfaces of the copper foils in the present embodiment.
As shown in fig. 2(a), the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are in a positional relationship of being shifted from each other in a plan view in the lamination direction. In particular, in the present embodiment, the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are arranged with a shift of half pitch, and the other conductor pattern is overlapped between the lines of the one conductor pattern. That is, the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are close to each other in the X direction.
By laminating the substrates 11, 12, and 13 from the state shown in fig. 2(a) and heating and pressing them, the laminate 10 in which the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are embedded in a thermoplastic resin is configured as shown in fig. 2 (B). During the heating and pressing, the resin of the base materials 11, 12, and 13 flows, and the conductor patterns 21 and 22 also flow, and are inclined or displaced. As a result, the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 may come closer to each other. However, at the pressing temperature in the heating and pressing, the copper oxide film does not flow. Therefore, even if the 1 st conductor pattern 21 flows, the insulating coating 31 is coated on the surface thereof, and therefore, even if the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are in contact, short-circuiting does not occur.
When the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are located at positions shifted from each other in a plan view as in the present embodiment, inclination and displacement of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are likely to occur along with the resin flow, but even in this case, short-circuiting can be prevented as described above.
Since there is no other conductor pattern on the 2 nd conductor pattern 22, the insulating coating 32 may not be present on the 2 nd conductor pattern 22.
EXAMPLE 2 EXAMPLE
Fig. 3(a) and 3(B) are partial sectional views of the multilayer substrate 2 according to embodiment 2. Fig. 3(a) is a sectional view in a stage before lamination pressing of a plurality of base materials. Fig. 3(B) is a cross-sectional view after lamination pressing. These drawings are cross-sectional views at positions corresponding to fig. 2(a) and 2(B) shown in embodiment 1.
The multilayer board 2 is formed by stacking a 2 nd base material 12 and a 3 rd base material 13 in this order with the 1 st base material 11 as the lowermost layer. The 1 st base material 11, the 2 nd base material 12, and the 3 rd base material 13 are made of thermoplastic resin.
In the direction shown in fig. 3(a), a 1 st conductive pattern 21 is formed on the upper surface of the 1 st base material 11, and a 2 nd conductive pattern 22 is formed on the upper surface of the 2 nd base material 12. Further, an insulating coating 31 is formed on the surface of the 1 st conductor pattern 21. Similarly, an insulating coating 32 is formed on the surface of the 2 nd conductor pattern 22. The positional relationship between the 1 st conductor pattern and the 2 nd conductor pattern is different from the examples shown in fig. 2(a) and 2 (B). The other basic structure is as shown in embodiment 1.
As shown in fig. 3(a), the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are in a positional relationship of being shifted from each other in a plan view in the lamination direction. In the present embodiment, one of the conductor patterns of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 in the line width direction overlaps in a lower part in a plan view. The distance L in fig. 3(a) represents the amount of this overlap.
When the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are partially overlapped in a plan view as in the present embodiment, the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 can be arranged in a high density in the laminate, and the multilayer substrate can be miniaturized. In this structure, the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are easily accessible due to inclination and displacement of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 caused by the resin flow, but the insulation property can be maintained even in this case.
EXAMPLE 3
Fig. 4(a) and 4(B) are partial sectional views of the multilayer substrate 3 according to embodiment 3. Fig. 4(a) is a sectional view in a stage before lamination pressing of a plurality of base materials. Fig. 4(B) is a cross-sectional view after lamination pressing. These drawings are cross-sectional views at positions corresponding to fig. 2(a) and 2(B) shown in embodiment 1.
The positional relationship between the 1 st conductive pattern 21 and the 2 nd conductive pattern 22 is different from the examples shown in fig. 2(a) and 2 (B). The relationship between the sizes of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 is different. The other basic structure is as shown in embodiment 1.
As shown in fig. 4(a), the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are in a positional relationship of overlapping with each other in a plan view in the lamination direction. In the present embodiment, the entire 2 nd conductive pattern 22 overlaps the 1 st conductive pattern 21 in a plan view. When the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are entirely overlapped in a plan view, inclination and displacement of the conductor patterns accompanying resin flow at the time of heating and pressing are small. However, when the cross-sectional shape of one conductor pattern (in this example, the 2 nd conductor pattern 22) is square (the aspect ratio is substantially 1: 1), and the cross-sectional shape of the other conductor pattern (in this example, the 1 st conductor pattern 21) is rectangular (the aspect ratio is, for example, about 1: 2), the conductor pattern having the square cross-sectional shape tends to be inclined with the flow of the resin. However, according to the present embodiment, even in such a structure, the insulation properties of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 can be maintained.
EXAMPLE 4 embodiment
Fig. 5(a) and 5(B) are partial sectional views of the multilayer substrate 4 according to embodiment 4. Fig. 5(a) is a sectional view in a stage before lamination pressing of a plurality of base materials. Fig. 5(B) is a cross-sectional view after lamination pressing. These drawings are cross-sectional views at positions corresponding to fig. 2(a) and 2(B) shown in embodiment 1. In this embodiment, an example of a multilayer substrate having three or more (three layers in the example of fig. 5(a) and 5 (B)) conductor patterns is shown.
The multilayer substrate 4 has a rectangular parallelepiped external shape. The multilayer board 4 is formed by stacking a 2 nd base material 12, a 3 rd base material 13, and a 4 th base material 14 in this order with the 1 st base material 11 as the lowermost layer. Each of the substrates 11, 12, 13, 14 is made of a thermoplastic resin.
In the direction shown in fig. 5(a), a 1 st conductive pattern 21 is formed on the upper surface of the 1 st base material 11, a 2 nd conductive pattern 22 is formed on the upper surface of the 2 nd base material 12, and a 3 rd conductive pattern 23 is formed on the upper surface of the 3 rd base material 13. Further, an insulating coating 31 is formed on the surface of the 1 st conductor pattern 21, an insulating coating 32 is formed on the surface of the 2 nd conductor pattern 22, and an insulating coating 33 is formed on the surface of the 3 rd conductor pattern 23.
The 1 st conductor pattern 21, the 2 nd conductor pattern 22, and the 3 rd conductor pattern 23 are substantially overlapped in a plan view, but these conductor patterns may be deviated to some extent in the line width direction (X direction) due to the relationship of the lamination shift accuracy. The other basic structure is as shown in embodiment 1.
When the conductor patterns of the respective layers are entirely overlapped when viewed in a plane in the lamination direction as in the present embodiment, the pressure applied to the conductor patterns during heating and pressing is likely to be equalized. However, if the conductor patterns are slightly shifted in the line width direction due to the accuracy of the stacking shift of the base material, the balance of the resin flow becomes uneven, and the conductor patterns are likely to be inclined in the line width direction. However, according to the present embodiment, even in such a structure, the insulation properties of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 can be maintained.
In addition, when the layer of the conductor pattern has three or more layers as in the present embodiment, one of two conductor patterns adjacent to each other in the stacking direction among these conductor patterns is the "1 st conductor pattern" in the present invention, and the other is the "2 nd conductor pattern" in the present invention. For example, in fig. 5(a), the conductor pattern 22 may be regarded as the "1 st conductor pattern" and the conductor pattern 23 may be regarded as the "2 nd conductor pattern".
EXAMPLE 5 EXAMPLE
In embodiment 5, an example of a multilayer substrate used as a coil device or an inductor element is shown.
Fig. 6 is an exploded perspective view of the multilayer substrate 5. The multilayer substrate 5 is formed by stacking a 1 st base material 11, a 2 nd base material 12, and a 3 rd base material 13 in this order with a 4 th base material 14 as the lowermost layer. Each of the substrates 11, 12, 13, 14 is made of a thermoplastic resin.
In the direction shown in fig. 6, a 1 st conductive pattern 21 is formed on the upper surface of the 1 st base material 11, and a 2 nd conductive pattern 22 is formed on the upper surface of the 2 nd base material 12. The 1 st conductor pattern 21 and the 2 nd conductor pattern 22 are both rectangular spiral conductor patterns. An insulating coating film (not shown) is formed on the surface of the 1 st conductor pattern 21. Similarly, an insulating film (not shown) is formed on the surface of the 2 nd conductor pattern 22.
Each of the substrates 11, 12, 13, 14 is a thermoplastic resin such as a Liquid Crystal Polymer (LCP). Each of the conductor patterns 21 and 22 is formed by patterning a copper foil, and the insulating film is an electrically insulating copper oxide film formed on the surface of the copper foil in the present embodiment. The via conductors 41, 42, 43, 44, 45, and 46 are formed by printing and applying, for example, an Sn-based conductive paste into holes formed in a base material, melting the paste by heat generated during heating and pressing, and then curing the paste.
The 1 st conductor pattern 21 and the 2 nd conductor pattern 22 overlap in a plan view. The degree of overlap differs depending on the positions of the conductor patterns 21 and 22, and is in the relationship shown in fig. 2(a), 2(B), 3(a), 3(B), 4(a), and 4 (B). Therefore, even in such a configuration, the insulation properties of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 can be maintained.
EXAMPLE 6 EXAMPLE
First, in the pattern forming step S1 shown in fig. 7, as shown in fig. 8(a), the 1 st conductor pattern 21 is formed on the 1 st base material 11 made of a thermoplastic resin, the 2 nd conductor pattern 22 is formed on the 2 nd base material 12, and the terminal electrodes 51 and 52 are formed on the 4 th base material 14. For example, a copper foil is attached to an LCP sheet, and the copper foil is patterned by photolithography. Further, a hole is formed in the 2 nd base material 12, and a Sn-based conductive paste containing a reducing agent, for example, is applied by printing in the hole and temporarily cured, thereby forming the via conductor 43 before curing. Examples of the reducing agent include alcohol-based reducing agents and aldehyde-based reducing agents.
In the insulating film forming step S2, an insulating film 31 formed of an oxide film is formed on the surface of the 1 st conductor pattern 21 by, for example, oxygen plasma treatment.
In the laminate forming step S3, the substrates 11, 12, 13, and 14 are stacked and heated and pressed. The portion of the insulating coating 31 of the 1 st conductor pattern 21 in contact with the via hole conductor 43 is reduced or removed by the reducing agent contained in the conductive paste, and the 2 nd conductor pattern is electrically connected to the base of the 1 st conductor pattern 21 through the via hole conductor 43.
Through the steps described above, a multilayer substrate 6 as shown in fig. 8(B) can be obtained.
(7 th embodiment)
Fig. 9(a) is a cross-sectional view of the multilayer substrate 7 according to the present embodiment at a stage before lamination and pressing of a plurality of base materials. Fig. 9(B) is a sectional view after lamination pressing. These drawings are cross-sectional views at positions corresponding to fig. 8(a) and 8(B) shown in embodiment 6, respectively.
The positional relationship between the 1 st conductive pattern 21 and the 2 nd conductive pattern 22 is different from the examples shown in fig. 8(a) and 8 (B). The relationship between the sizes of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 is different. The other basic structure is as shown in embodiment 1.
First, as shown in fig. 9(a), a 1 st conductive pattern 21 is formed on a 1 st base material 11 made of a thermoplastic resin, a 2 nd conductive pattern 22 is formed on a 2 nd base material 12, and terminal electrodes 51 and 52 are formed on a 4 th base material 14. For example, a copper foil is attached to an LCP sheet, and the copper foil is patterned by photolithography. Further, a hole is formed in the 2 nd base material 12, and a Sn-based conductive paste, for example, is applied by printing in the hole and temporarily cured, thereby forming the via conductor 43 before curing.
Further, a thermosetting resin film 35 is formed on the lower surface (the surface opposite to the surface on which the 2 nd conductor pattern 22 is formed) of the 2 nd substrate 12. For example, printing to form a film of epoxy. These thermosetting resin films 35 are formed at positions facing the 1 st conductor pattern 21, where the surfaces of the 1 st conductor pattern 21 are insulated and coated. The thermosetting resin film 35 is a film containing as a main component a thermosetting resin that is thermally cured at a temperature lower than the pressing temperature at the time of forming the laminate. Such as an epoxy adhesive. The thermosetting resin film 35 has a thermosetting start temperature of, for example, 120 ℃. When the thermosetting resin film 35 is thermally cured, the flowability at high temperature is lower than that of the respective substrates 11, 12, 13, and 14 (thermoplastic resin).
Then, the respective substrates 11, 12, 13, 14 are laminated, and for example, heated and pressed at a predetermined temperature (for example, 300 ℃) within a range of 180 ℃ to 320 ℃. Thus, a multilayer substrate 7 as shown in fig. 9(B) was obtained.
According to the present embodiment, even if the 1 st substrate 11 and the 2 nd substrate 12 soften at the pressing temperature, the thermosetting resin film 35 does not easily soften. Therefore, the insulation properties of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 can be maintained.
In the present embodiment, the step of coating the thermosetting resin film 35 on the surface of the 1 st conductor pattern 21 by the formation of the thermosetting resin film 35 and the heating and pressing corresponds to the "insulating coating forming step" of the present invention.
EXAMPLE 8 th embodiment
Embodiment 8 shows a multilayer substrate provided with an insulating film other than an oxide film, and a method for manufacturing the same.
Fig. 10(a) is a cross-sectional view of the multilayer substrate 8 according to the present embodiment at a stage before lamination and pressing of a plurality of base materials. Fig. 10(B) is a sectional view after lamination pressing.
First, as shown in fig. 10(a), a 1 st conductive pattern 21 is formed on a 1 st base material 11 made of a thermoplastic resin, and a 2 nd conductive pattern 22 is formed on a 2 nd base material 12. For example, a copper foil is attached to an LCP sheet, and the copper foil is patterned by photolithography.
Next, a paste-like thermosetting resin is print-coated on the upper surface of the 1 st substrate 11 at a position covering the 1 st conductor pattern 21, thereby forming an insulating coating 31. A paste-like thermosetting resin is print-coated on the upper surface of the 2 nd base material 12 at a position covering the 2 nd conductor pattern 22, thereby forming an insulating coating 32. The insulating coatings 31 and 32 made of the thermosetting resin are films mainly composed of a thermosetting resin that is thermally cured at a temperature lower than the pressing temperature at the time of forming the laminate. Such as an epoxy adhesive.
Next, in the state of the respective substrates 11 and 12 (in the state of being single bodies before lamination), the insulating coatings 31 and 32 based on the thermosetting resin are thermally cured at a temperature lower than the pressing temperature at the time of formation of the laminate. When the thermosetting start temperature of the thermosetting resin is, for example, 120 ℃ or higher, the insulating films 31 and 32 are thermally cured by heating at a temperature of 120 ℃ or higher and lower than the heating and pressing temperature. When the thermosetting resin is thermally cured, the flowability at high temperature is lower than that of the substrates 11, 12, and 13 (thermoplastic resin).
Then, the respective substrates 11, 12, and 13 are laminated, and for example, heated and pressed at a predetermined temperature (for example, 300 ℃) within a range of 180 ℃ to 320 ℃. Thus, a multilayer substrate 7 as shown in fig. 10(B) was obtained.
According to the present embodiment, even if the 1 st base material 11 and the 2 nd base material 12 soften at the pressing temperature, the insulating coatings 31 and 32 do not easily soften. Therefore, the insulation properties of the 1 st conductor pattern 21 and the 2 nd conductor pattern 22 can be maintained.
In addition, in the state of the 1 st base material 11 before lamination, the adjacent 1 st conductor patterns 21 are connected to each other via the insulating coating 31, and similarly, in the state of the 2 nd base material 12 before lamination, the adjacent 2 nd conductor patterns 22 are connected to each other via the insulating coating 32. Therefore, the adjacent conductor patterns of the conductor patterns 21 and 22 can be prevented from being displaced from each other due to the flow of the resin during the heating and pressing.
In addition to printing and applying a paste-like thermosetting resin, a thermosetting resin film may be applied to a predetermined position of the substrates 11 and 12, and then the thermosetting resin film may be thermally cured to be brought into the state shown in fig. 10 (a). According to this method, the thickness of the insulating film can be easily made thinner than in the case of printing and applying a paste-like thermosetting resin, and a film can be easily formed.
EXAMPLE 9 EXAMPLE
In embodiment 9, a method for manufacturing a multilayer substrate in which an insulating film made of a thermosetting resin is formed by a method other than print application is described.
Fig. 11(a) is a cross-sectional view of the multilayer substrate 9 according to the present embodiment at a stage before lamination and pressing of a plurality of base materials. Fig. 11(B) is a sectional view at a halfway stage before the lamination pressing. Fig. 11(C) is a sectional view after the lamination pressing. These drawings are cross-sectional views at positions corresponding to fig. 8(a) and 8(B) shown in embodiment 6. The multilayer substrate 9 of the present embodiment is manufactured as follows.
As shown in fig. 11(a), the 1 st conductive pattern 21 is formed on the 1 st base material 11 made of thermoplastic resin, the 2 nd conductive pattern 22 is formed on the 2 nd base material 12, and the terminal electrodes 51 and 52 are formed on the 4 th base material 14. Further, a via conductor 43 before curing is formed on the 2 nd base material 12.
As shown in fig. 11(B), a thermosetting resin film 35 is attached to the surface of the 1 st substrate 11 so as to cover the 1 st conductor pattern 21. In the thermosetting resin film 35, the hole H is formed in advance at a position corresponding to the via conductor 43.
The thermosetting resin film 35 is a prepreg mainly composed of a thermosetting resin having a thermosetting start temperature lower than a pressing temperature. The thermosetting resin is, for example, an epoxy resin. The thermosetting resin film 35 may be a thermosetting resin film that is cured in advance at a temperature equal to or higher than the pressing temperature.
Then, the multilayer substrate 9 as shown in fig. 11(C) is obtained by heating and pressing.
Other embodiments
In each of the above-described embodiments, an example is shown in which the surface (back surface) opposite to the surface (front surface) on which the 2 nd conductor pattern is formed on the 2 nd base material and the surface (front surface) on which the 1 st conductor pattern is formed on the 1 st base material face each other, but a surface (back surface) opposite to the surface on which the 2 nd conductor pattern is formed on the 2 nd base material and a surface (back surface) opposite to the surface on which the 1 st conductor pattern is formed on the 1 st base material may be laminated so as to face each other.
In the above-described embodiments, the example in which the 1 st base material and the 2 nd base material are in contact with each other is shown, but another base material on which a conductor pattern close to the 1 st conductor pattern is not formed may be sandwiched between the 1 st base material and the 2 nd base material. For example, the 1 st conductor pattern formation surface of the 1 st base material and the 2 nd conductor pattern formation surface of the 2 nd base material may be laminated with the base material on which the conductor pattern is not formed interposed therebetween.
In the embodiments described above, the multilayer substrate in which the number of stacked substrates is intentionally reduced is shown, but it is needless to say that the present invention can be applied to a structure in which substrates, insulating films, and substrates are stacked in this order. For example, the total number of layers of the substrate may be about 20.
As the thermosetting resin used for the multilayer substrate of the present invention, a polyimide resin can be used in addition to the epoxy resin.
In the above embodiments, although the components are illustrated as one unit, it is needless to say that the processes (manufacturing by a large-size process) may be performed in a state where the components are collectively arranged on a substrate including a plurality of element forming portions, and the components may be finally separated into individual pieces.
In the example shown in fig. 6, a coil device and an inductor are illustrated, but the multilayer substrate of the present invention can be applied to various electronic components such as an antenna, an actuator, and a sensor. The multilayer substrate of the present invention includes not only the chip component shape but also other components having arbitrary shapes. As described above, the present invention can be modified as appropriate without departing from the scope of the present invention.
Finally, the description of the above embodiments is in all respects illustrative and not restrictive. Modifications and variations can be appropriately made by those skilled in the art. For example, partial replacement or combination of the structures shown in the different embodiments can be performed. The scope of the present invention is shown not by the above-described embodiments but by the claims. Further, the scope of the present invention is intended to include all modifications equivalent in meaning and scope to the claims.
Description of the symbols
H … pore;
1 to 9 … multilayer substrates;
10 … a laminate;
11 … substrate No. 1;
12 … substrate No. 2;
13 … substrate No. 3;
14 … No. 4 substrate;
21 … 1 st conductor pattern;
22 … conductor pattern 2;
23 … conductor pattern No. 3;
31. 32, 33 … insulating coating film;
35 … a thermosetting resin film;
41-46 … via conductors;
51. 52 … terminal electrode.
Claims (7)
1. A multilayer substrate is characterized by comprising:
a 1 st base material made of a thermoplastic resin;
a 1 st conductor pattern formed on the upper surface of the 1 st base material;
a 2 nd base material made of a thermoplastic resin;
a 2 nd conductor pattern formed on the upper surface of the 2 nd base material; and
an insulating coating film made of a material having lower fluidity at a predetermined pressing temperature than the 1 st base material and the 2 nd base material, partially disposed between the 1 st base material and the 2 nd base material, and covering the 1 st conductor pattern,
the 2 nd base material is in contact with the upper surface of the 1 st base material, the 1 st conductor pattern and the 2 nd conductor pattern are conductors closest to each other in the lamination direction,
a plurality of base materials including the 1 st base material and the 2 nd base material are stacked and thermocompression bonded at the pressing temperature.
2. The multilayer substrate of claim 1,
the 1 st conductor pattern and the 2 nd conductor pattern are located at positions shifted from each other in a plan view.
3. The multilayer substrate according to claim 1 or 2,
the 1 st conductor pattern and the 2 nd conductor pattern partially overlap in a plan view.
4. The multilayer substrate according to claim 1 or 2,
the 1 st conductor pattern and the 2 nd conductor pattern are copper foil patterns.
5. The multilayer substrate of claim 4,
the insulating film is an oxide film formed on the surface of the copper foil.
6. The multilayer substrate according to claim 1 or 2,
the insulating coating film is a film of a thermosetting resin that is thermally cured at a temperature lower than the pressing temperature.
7. The multilayer substrate according to claim 1 or 2,
the 1 st conductor pattern and the 2 nd conductor pattern are coil patterns having a winding axis in the lamination direction.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016204674 | 2016-10-18 | ||
JP2016-204674 | 2016-10-18 | ||
PCT/JP2017/034271 WO2018074139A1 (en) | 2016-10-18 | 2017-09-22 | Multilayer substrate and method for manufacturing same |
Publications (1)
Publication Number | Publication Date |
---|---|
CN210075747U true CN210075747U (en) | 2020-02-14 |
Family
ID=62019131
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201790001317.4U Active CN210075747U (en) | 2016-10-18 | 2017-09-22 | Multilayer substrate |
Country Status (4)
Country | Link |
---|---|
US (1) | US11456108B2 (en) |
JP (1) | JP6562160B2 (en) |
CN (1) | CN210075747U (en) |
WO (1) | WO2018074139A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN219644174U (en) * | 2019-08-08 | 2023-09-05 | 株式会社村田制作所 | Multilayer substrate |
WO2021025025A1 (en) * | 2019-08-08 | 2021-02-11 | 株式会社村田製作所 | Resin multilayer substrate and method for producing resin multilayer substrate |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3141893B2 (en) | 1991-06-17 | 2001-03-07 | 株式会社東芝 | Planar inductor |
JP3755657B2 (en) * | 2002-05-16 | 2006-03-15 | 三菱電機株式会社 | Wiring board and manufacturing method thereof |
US7038143B2 (en) * | 2002-05-16 | 2006-05-02 | Mitsubishi Denki Kabushiki Kaisha | Wiring board, fabrication method of wiring board, and semiconductor device |
JP2006310716A (en) * | 2005-03-31 | 2006-11-09 | Tdk Corp | Planar coil element |
JP4877598B2 (en) * | 2006-12-27 | 2012-02-15 | Tdk株式会社 | Method for forming conductor pattern and electronic component |
JP4821908B2 (en) * | 2007-12-26 | 2011-11-24 | 株式会社村田製作所 | Multilayer electronic component and electronic component module including the same |
JP5962754B2 (en) * | 2012-03-27 | 2016-08-03 | 株式会社村田製作所 | Electronic components |
JP6000314B2 (en) * | 2013-10-22 | 2016-09-28 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Chip electronic component and manufacturing method thereof |
JP5757376B1 (en) * | 2013-11-28 | 2015-07-29 | 株式会社村田製作所 | Multilayer substrate manufacturing method, multilayer substrate and electromagnet |
CN105510690B (en) * | 2014-09-22 | 2018-04-27 | 登丰微电子股份有限公司 | Zero passage voltage detection circuit and method |
-
2017
- 2017-09-22 JP JP2018546206A patent/JP6562160B2/en active Active
- 2017-09-22 CN CN201790001317.4U patent/CN210075747U/en active Active
- 2017-09-22 WO PCT/JP2017/034271 patent/WO2018074139A1/en active Application Filing
-
2019
- 2019-04-04 US US16/374,769 patent/US11456108B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
WO2018074139A1 (en) | 2018-04-26 |
JPWO2018074139A1 (en) | 2019-06-24 |
US20190228900A1 (en) | 2019-07-25 |
US11456108B2 (en) | 2022-09-27 |
JP6562160B2 (en) | 2019-08-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6424453B2 (en) | Multilayer substrate manufacturing method and multilayer substrate | |
TWI466146B (en) | Common mode filter and method of manufacturing the same | |
CN210575405U (en) | Electronic component, vibrating plate, and electronic device | |
JP2019016743A (en) | Multilayer substrate | |
US20160165720A1 (en) | Multilayer substrate manufacturing method and multilayer substrate | |
JP6705567B2 (en) | Multilayer substrate, mounting structure of multilayer substrate, method of manufacturing multilayer substrate, and method of manufacturing electronic device | |
CN210075747U (en) | Multilayer substrate | |
KR100678083B1 (en) | Fabricating method of the embedded capacitor and embedded capacitor using the same | |
US9980383B2 (en) | Laminated circuit substrate | |
JP6380716B1 (en) | Multilayer substrate, mounting structure of multilayer substrate on circuit board, and method for manufacturing multilayer substrate | |
JP6648832B2 (en) | Multilayer substrate and method of manufacturing the same | |
JP6263167B2 (en) | Multilayer substrate and method for manufacturing multilayer substrate | |
WO2016117122A1 (en) | Method for producing wiring board, and wiring board | |
JP4010919B2 (en) | Inductive element manufacturing method | |
US20170042033A1 (en) | Component built-in multilayer board | |
CN210899888U (en) | Multilayer substrate and electronic device | |
WO2021025025A1 (en) | Resin multilayer substrate and method for producing resin multilayer substrate | |
CN210157483U (en) | Multilayer substrate | |
WO2021025024A1 (en) | Multilayer board and method for manufacturing multilayer board | |
US20170223837A1 (en) | Component built-in substrate and method for manufacturing component built-in substrate | |
JP5585035B2 (en) | Circuit board manufacturing method | |
WO2019240000A1 (en) | Method for manufacturing electric element, electric element, and electric element mounting structure | |
JP2004103756A (en) | Coil component and its manufacturing method | |
JP2016146370A (en) | Substrate with built-in component and method for manufacturing the same | |
JP2007012667A (en) | Electric circuit board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |