CN210006753U - Light emitting diode - Google Patents
Light emitting diode Download PDFInfo
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- CN210006753U CN210006753U CN201920780532.XU CN201920780532U CN210006753U CN 210006753 U CN210006753 U CN 210006753U CN 201920780532 U CN201920780532 U CN 201920780532U CN 210006753 U CN210006753 U CN 210006753U
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Abstract
The utility model relates to an kind of emitting diode this emitting diode is including the aluminium indium nitride layer, silicon nitride layer and the second N type gallium nitride layer of range upon range of setting because the silicon nitride layer becomes network structure, consequently, the second N type gallium nitride layer of range upon range of on silicon nitride layer can be through this network structure along emitting diode's range upon range of direction growth to realize the three-dimensional growth on second N type gallium nitride layer, again because the crystal lattice on aluminium indium nitride layer is close consequently with the crystal lattice on N type gallium nitride layer and second N type gallium nitride layer, aluminium indium nitride layer, silicon nitride layer and second N type gallium nitride layer cooperate, can strengthen the ability of N type layer conduction electron, and then the reinforcing emitting diode's luminous effect.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to kinds of emitting diode.
Background
Light Emitting Diodes (LEDs) are kinds of solid-state semiconductor devices capable of Emitting Light, and are used by in the fields of illumination and lighting, such as indicator lights and display screens.
In the conventional art, the core of the led is a PN junction, and under the action of an electric field, holes in the P-type layer forming the PN junction and electrons in the N-type layer forming the PN junction recombine to form visible light.
The applicant found in the course of implementing the conventional technique that: the conventional light emitting diode has poor light emitting efficiency.
SUMMERY OF THE UTILITY MODEL
Based on this, it is necessary to provide kinds of light emitting diodes for solving the problem of poor light emitting efficiency of the light emitting diodes in the conventional technology.
A light emitting diode, comprising:
a substrate;
an U-shaped gallium nitride layer covering the substrate;
an N-type GaN layer covering the U-type GaN layer;
the N-type layer covers the N-type gallium nitride layer, the N-type layer comprises a laminated aluminum indium nitride layer, a silicon nitride layer and a second N-type gallium nitride layer, the silicon nitride layer covers the aluminum indium nitride layer, and the second N-type gallium nitride layer covers the silicon nitride layer;
the multiple quantum well structure layer covers the N-type layer;
and the P-type semiconductor layer covers the multiple quantum well structure layer.
In the light emitting diode, the silicon nitride layer is of a net structure, so that the second N-type gallium nitride layer stacked on the silicon nitride layer can grow along the stacking direction of the light emitting diode through the net structure, thereby realizing the three-dimensional growth of the second N-type gallium nitride layer, and the aluminum indium nitride layer, the silicon nitride layer and the second N-type gallium nitride layer are matched with each other because the crystal lattice of the aluminum indium nitride layer is close to the crystal lattices of the N-type gallium nitride layer and the second N-type gallium nitride layer, so that the electron conduction capability of the N-type layer can be enhanced, and the light emitting effect of the light emitting diode is further enhanced.
Drawings
Fig. 1 is a schematic flow chart of a method for forming light emitting diodes according to embodiments of the present application.
Fig. 2 is a schematic diagram of a hierarchical structure of embodiments of the present application.
Fig. 3 is a schematic flow chart illustrating the formation of N-type layers in embodiments of the present application.
Fig. 4 is a schematic flow chart of another embodiments of the present application.
Fig. 5 is a schematic diagram of a hierarchical structure of another embodiments of the present application.
Fig. 6 is a schematic flow chart of a method for forming light emitting diodes according to still another embodiments of the present application.
Fig. 7 is a schematic diagram of a hierarchical structure of leds according to another embodiment of the present application.
Fig. 8 is a schematic flow chart illustrating the formation of multiple quantum well structure layers according to embodiments of the present application.
Wherein, the meanings represented by the reference numerals of the figures are respectively as follows:
10. a light emitting diode;
100. a substrate;
102. th surface;
104. a second surface;
200. U-type GaN layer;
300. th N-type GaN layer;
400. an N-type layer;
412. an aluminum indium nitride layer;
414. a silicon nitride layer;
416. a second N-type gallium nitride layer;
500. a multiple quantum well structure layer;
512. a quantum well layer;
514. a quantum barrier layer;
600. a P-type semiconductor layer;
700. a buffer layer;
800. and a stress release layer.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, as those skilled in the art will be able to make similar modifications without departing from the spirit and scope of the present invention.
Aiming at the problem of poor light emitting efficiency of the light emitting diode in the prior art, light emitting diodes capable of improving the lattice quality of the light emitting diode so as to improve the light emitting effect of the light emitting diode and a forming method thereof are provided.
A method for forming a light emitting diode, as shown in FIG. 1, comprising the steps of:
s100, providing a substrate 100, wherein the substrate 100 has an th surface 102 and a second surface 104 which are oppositely arranged.
Specifically, a substrate 100 for forming the light emitting diode 10 is provided, the substrate 100 may be a sapphire substrate, a silicon carbide substrate, or other type of substrate, the substrate 100 has opposing surfaces 102 and a second surface 104.
S200, preparing an U-shaped gallium nitride layer 200 covering the surface 102.
Specifically, surfaces of the substrate 100 are provided with a U-shaped gallium nitride layer 200 covering the surfaces, and the U-shaped gallium nitride layer 200 can be provided on any of the surface 102 and the second surface 104, in this embodiment, the U-shaped gallium nitride layer 200 is provided on the surface 102 of the substrate 100 and covers the surface 102, and the U-shaped gallium nitride layer 200 is a gallium nitride layer not doped with other impurities.
S300, preparing an th N-type gallium nitride layer 300 covering the th U-type gallium nitride layer 200.
Specifically, a N-type gallium nitride layer 300 is prepared on the surface of the U-type gallium nitride layer 200 far away from the substrate 100, the N-type gallium nitride layer 300 covers the U-type gallium nitride layer 200, and the N-type gallium nitride layer 300 can generate electrons under the action of an electric field for combining with holes, so that energy is released.
S400, preparing an N-type layer 400 to cover the th N-type gallium nitride layer 300, wherein the N-type layer 400 comprises a laminated aluminum indium nitride layer 412, a silicon nitride layer 414 and a second N-type gallium nitride layer 416, the silicon nitride layer 414 covers the aluminum indium nitride layer 412, and the second N-type gallium nitride layer 416 covers the silicon nitride layer 414.
Specifically, an N-type layer 400 is prepared on the surface of the th N-type gallium nitride layer 300 far away from the th U-type gallium nitride layer 200, the N-type layer 400 covers the th N-type gallium nitride layer 300, the N-type layer 400 may include an aluminum indium nitride layer 412, a silicon nitride layer 414 and a second N-type gallium nitride layer 416 which are stacked, wherein the aluminum indium nitride layer 412 is close to the th N-type gallium nitride layer 300 and covers the th N-type gallium nitride layer 300, the silicon nitride layer 414 is located between the aluminum indium nitride layer 412 and the second N-type gallium nitride layer 416 and covers the aluminum indium nitride layer 412, and the second N-type gallium nitride layer 416 covers the silicon nitride layer 414.
S500, preparing a multi-quantum well structure layer 500 to cover the N-type layer 400.
Specifically, a multiple quantum well structure layer 500 is prepared on the surface of the N-type layer 400 far from the th N-type gallium nitride layer 300, the multiple quantum well structure layer 500 covers the N-type layer 400 to improve the recombination rate of electrons and holes, and the multiple quantum well structure layer 500 may generally include a quantum well layer 512 and a quantum barrier layer 514 which are stacked and staggered.
S600, preparing a P-type semiconductor layer 600 to cover the multiple quantum well structure layer 500.
Specifically, a P-type semiconductor layer 600 is formed on the surface of the multiple quantum well structure layer 500 away from the N-type layer 400. The P-type semiconductor layer 600 covers the multiple quantum well structure layer 500 to generate holes under the action of an electric field.
When the light emitting diode 10 formed by the method is powered on, the th N-type gallium nitride layer 300 can generate electrons and move towards the multiple quantum well structure layer 500 under the action of an electric field, meanwhile, the P-type semiconductor layer 600 generates holes and the multiple quantum well structure layer 500 under the action of the electric field so as to be combined with the electrons to emit light, the light emitting diode 10 formed by the forming method can improve the lattice quality of the light emitting diode 10 and further improve the light emitting effect of the light emitting diode 10 because the energy level of the indium aluminum nitride layer 412 is higher and the lattice of the indium aluminum nitride is close to that of a gallium nitride material, meanwhile, the N-type layer 400 further comprises a silicon nitride layer 414 which is in a mesh structure, and when the N-type layer 416 covers the silicon nitride layer 414, the mesh structure of the silicon nitride layer 414 is preferentially filled, so that the second N-type gallium nitride layer 416 stacked on the silicon nitride layer 414 can grow along the stacking direction of the light emitting diode 10 through the mesh structure, thereby realizing the three-dimensional growth of the second N-type gallium nitride layer 416, the improvement of the electron conduction capability of the N-type gallium nitride layer 412, the second N-type indium nitride layer 416 and the electron conduction layer can be matched with the light emitting diode 10 and the light emitting diode 10.
In embodiments, the step S300 may specifically include:
and introducing gallium, silicon and nitrogen into the chemical vapor deposition chamber within the growth temperature range of 1070 ℃ to 1100 ℃, so that the gallium, the silicon and the nitrogen carry out a chemical combination reaction on the surface of the U-shaped gallium nitride layer (200) to prepare the N-shaped gallium nitride layer (300).
Specifically, the N-type gallium nitride layer 300 may be prepared on the surface of the U-type gallium nitride layer 200 by using a chemical vapor deposition method, the N-type gallium nitride layer 300 may be prepared by setting a temperature of a chemical vapor deposition chamber to 1070 ℃ to 1100 ℃, and introducing a gallium source, a silicon source, and a nitrogen source into the chemical vapor deposition chamber to cause a chemical reaction between the gallium source, the silicon source, and nitrogen, thereby obtaining a silicon-doped gallium nitride layer, the silicon-doped gallium nitride layer constitutes the N-type gallium nitride layer 300, and for convenience of distinction, the N-type gallium nitride layer constituting the N-type gallium nitride layer 300 is named as a gallium nitride layer.
More specifically, the growth temperature of the th N-type gan layer 300 may be 1070 ℃, 1100 ℃ or 1085 ℃, and the concentration of silicon in the th gan layer may be 1 × 1019/cm3To 4X 1019/cm3That is, in the gallium nitride layer of th, the concentration of silicon may be 1 × 1019/cm3And may be 4X 1019/cm3It may be 2.5X 1019/cm3。
In embodiments, as shown in fig. 3, the step S400 may specifically include:
and S410, preparing an indium aluminum nitride layer 412 by using a chemical vapor deposition method within the growth temperature range of 750 ℃ to 1000 ℃, and covering the N-type gallium nitride layer 300.
Specifically, the aluminum indium nitride layer 412 covering the N-type gallium nitride layer 300 is formed on the N-type gallium nitride layer 300, and the aluminum indium nitride layer 412 may be formed by a chemical vapor deposition method at a growth temperature ranging from 750 ℃ to 1000 ℃, and specifically, aluminum, indium and nitrogen are introduced into a chemical vapor deposition chamber at a growth temperature ranging from 750 ℃ to 1000 ℃, so that a reaction gas including aluminum, indium and nitrogen is diffused toward the surface of the N-type gallium nitride layer 300 away from the U-type gallium nitride layer 200, the reaction gas is adsorbed onto the surface of the N-type gallium nitride layer 300, and a solid aluminum indium nitride layer 412 is formed on the surface of the 35 N-type gallium nitride layer 300 by a thermal decomposition reaction or/and an indium synthesis reaction, wherein the growth temperature of the aluminum nitride layer 412 may be 750 ℃, or 1000 ℃, or 875 ℃ and the aluminum source of the aluminum source may be trimethylaluminum, the indium source may be a trimethylaluminum source, and the indium source may be indium nitrogen source.
S420, the silicon nitride layer 414 is continuously prepared to cover the indium aluminum nitride layer 412.
Specifically, the silicon nitride layer 414 covering the aluminum indium nitride layer 412 is prepared on the aluminum indium nitride layer 412 while maintaining the growth temperature, the silicon nitride layer 414 is prepared by maintaining the temperature in the chemical vapor deposition chamber and continuing to prepare the silicon nitride layer 414 by using the chemical vapor deposition method, and specifically, the method may include maintaining the temperature in the chemical vapor deposition chamber, stopping the introduction of aluminum and indium into the chemical vapor deposition chamber in step S410, introducing silicon into the chemical vapor deposition chamber, diffusing a reaction gas containing silicon and nitrogen toward the surface of the aluminum indium nitride layer 412 away from the N-type gallium nitride layer 300, adsorbing the reaction gas containing silicon and nitrogen onto the surface of the aluminum indium nitride layer 412, forming a solid silicon nitride layer 414 on the surface of the aluminum indium nitride layer 412 by using a thermal decomposition reaction or/and a chemical synthesis reaction, and introducing silicon into the chemical vapor deposition chamber may be silicon hydride.
S430, the second N-type gan layer 416 is continuously prepared to cover the silicon nitride layer 414.
Specifically, a second N-type gallium nitride layer 416 is formed on the silicon nitride layer 414 to cover the silicon nitride layer 414, while maintaining the growth temperature. When the second N-type gallium nitride layer 416 is prepared, the temperature in the chemical vapor deposition chamber is maintained unchanged, and the chemical vapor deposition method is continuously used to prepare the second N-type gallium nitride layer 416. It may specifically be: and maintaining the temperature in the chemical vapor deposition chamber unchanged, maintaining the silicon introduced into the chemical vapor deposition chamber unchanged, and introducing gallium into the chemical vapor deposition chamber. Reacting gas containing gallium, silicon and nitrogenDiffusing to the surface of the silicon nitride layer 414 far from the indium aluminum nitride layer 412, adsorbing reaction gas containing gallium, silicon and nitrogen to the surface of the silicon nitride layer 414, forming a solid second N-type gallium nitride layer 416 on the surface of the silicon nitride layer 414 by using thermal decomposition reaction or/and chemical synthesis reaction, wherein the second N-type gallium nitride layer 416 is a silicon-doped gallium nitride layer, and in order to be distinguished from the th gallium nitride layer, the N-type gallium nitride layer in the N-type layer 400 is named as a second N-type gallium nitride layer 416, and in the second N-type gallium nitride layer 416, the concentration range of silicon is 1 × 1019/cm3To 4X 1019/cm3. That is, the concentration of silicon in the second gallium nitride layer may be 1 × 1019/cm3And may be 4X 1019/cm3It may be 2.5X 1019/cm3. The gallium introduced into the chemical vapor deposition chamber may be trimethyl gallium.
S440, repeating the above steps 3 to 10 times to prepare the N-type layer 400.
Specifically, aluminum indium nitride layers 412, silicon nitride layers 414 and second N-type gallium nitride layers 416 form cycles, may form 3 to 10 cycles of the N-type layer 400, that is, the N-type layer 400 may be formed by cyclically laminating 3 aluminum indium nitride layers 412, silicon nitride layers 414 and second N-type gallium nitride layers 416, or 10 aluminum indium nitride layers 412, silicon nitride layers 414 and second N-type gallium nitride layers 416, or 6 aluminum indium nitride layers 412, silicon nitride layers 414 and second N-type gallium nitride layers 416.
The forming method of the light emitting diode generates th N-type gallium nitride layer 300 in 1070 ℃ to 1100 ℃ high temperature and generates N-type layer 400 in 750 ℃ to 1000 ℃ low temperature, the light emitting diode 10 formed by the forming method can improve the energy level of the light emitting diode 10 and enhance the current expansion capability of the light emitting diode 10 by utilizing the high temperature layer and the low temperature layer, thereby improving the light emitting efficiency of the light emitting diode 10, meanwhile, the th N-type gallium nitride layer 300 and the N-type layer 400 which are adjacent to the light emitting diode 10 adopt a high temperature and low temperature form, which can relieve thermal stress, thereby reducing the polarization of the light emitting diode 10, the forming method of the light emitting diode and the formed light emitting diode 10 can solve the problem of poor edge quality of the light emitting diode 10 due to large stress of the high temperature N-type layer in the traditional technology by growing the hierarchical structure of the light emitting diode 10 step by step, and meanwhile, the silicon nitride layer 414 is inserted into the N-type layer 400, which can enable the second N-type gallium nitride layer 416 to be three-dimensional, thereby improving the capability of the conduction electron of the N-type gallium nitride layer, improving the quality of the light emitting diode 10, and improving the epitaxial growth efficiency of the light emitting diode.
In embodiments, as shown in fig. 4 and 5, the method for forming a light emitting diode further includes, before step S200:
s700, preparing a buffer layer 700 covering the th surface 102, wherein the buffer layer 700 is arranged between the substrate 100 and the U-shaped GaN layer 200.
Specifically, before the U-shaped gallium nitride layer 200 covering the th surface 102 of the substrate 100 is formed on the substrate 100, a buffer layer 700 may be further prepared between the substrate 100 and the U-shaped gallium nitride layer 200, wherein the buffer layer 700 is used for providing flat surface for the U-shaped gallium nitride layer 200, so as to improve the light emitting effect of the light emitting diode 10, and the buffer layer 700 covers the th surface 102 of the substrate 100.
Further , the step S700 may specifically include:
preparing a buffer layer 700 by using a chemical vapor deposition method at a growth temperature of 550 ℃, wherein the buffer layer 700 covers the surface 102 and comprises a second U-shaped gallium nitride layer.
Specifically, a second U-shaped gallium nitride layer covering the th surface 102 is formed on the substrate 100, the second U-shaped gallium nitride layer may be formed by a chemical vapor deposition method at a growth temperature of about 550 ℃, the second U-shaped gallium nitride layer may be formed by diffusing a reaction gas containing gallium and nitrogen toward the th surface 102 of the substrate 100, adsorbing the reaction gas containing gallium and nitrogen to the th surface 102, and forming a solid gallium nitride layer on the th surface 102 by using a thermal decomposition reaction or/and a chemical synthesis reaction to form the buffer layer 700, the buffer layer 700 may have a thickness of 25nm to 35nm, that is, the buffer layer 700 may have a thickness of 25nm, 35nm, or 30nm, and the reaction gas containing gallium and nitrogen may be a reaction gas containing trimethyl gallium and nitrogen.
Further , in the method for forming the light emitting diode, the step S200 includes:
an th U-shaped gallium nitride layer 200 is prepared by chemical vapor deposition at a growth temperature ranging from 500 ℃ to 1100 ℃, covering the buffer layer 700 or the th surface 102.
Specifically, when the method for forming the light emitting diode has step S700, that is, when the buffer layer 700 is formed by the method for forming the light emitting diode, the U-type gallium nitride layer 200 is prepared to cover the surface of the buffer layer 700 away from the substrate 100, and when the method for forming the light emitting diode does not have step S700, that is, when the buffer layer 700 is not formed by the method for forming the light emitting diode, the U-type gallium nitride layer 200 is prepared to cover the surface 102, the U-type gallium nitride layer 200 is an undoped gallium nitride layer, the method for forming the U-type gallium nitride layer 200 may also be a chemical vapor deposition method, and no further description is given, when the U-type gallium nitride layer 200 is prepared by a chemical vapor deposition method, the growth temperature range of the chemical vapor deposition chamber may be 500 ℃ to 1100 ℃, that is the growth temperature of the U-type gallium nitride layer 200 may be 500 ℃, 1100 ℃ may also be 800 ℃, and the thickness of the U-type gallium nitride layer 200 may be 0.5 μm, that is 1.5 μm, and the thickness may also be 1.75 μm.
In embodiments, as shown in fig. 6 and 7, the method for forming a light emitting diode further includes, before step S500:
s800, preparing a stress release layer 800 to cover the N-type layer 400, wherein the stress release layer 800 is arranged between the N-type layer 400 and the multiple quantum well structure layer 500.
Specifically, before forming the multiple quantum well structure layer 500 covering the N-type layer 400 on the N-type layer 400, a stress relief layer 800 may be further prepared between the N-type layer 400 and the multiple quantum well structure layer 500, where the stress relief layer 800 is used for relieving stress of the light emitting diode 10, and the stress relief layer 800 may be a low indium-doped and low silicon-doped gallium nitride layer, as in .
When the method for forming the light emitting diode has the step S800, that is, when the stress release layer 800 is formed in the method for forming the light emitting diode, the multiple quantum well structure layer 500 is prepared to cover the stress release layer 800. At this time, the light emitting diode 10 is formed as shown in fig. 7. When the method for forming the light emitting diode does not include the step S800, that is, when the method for forming the light emitting diode does not include the stress release layer 800, the multiple quantum well structure layer 500 is prepared to cover the N-type layer 400, which is not described in detail.
In embodiments, as shown in fig. 8, the step S500 may specifically include:
s510, preparing a quantum well layer 512 in a chemical vapor deposition chamber by using a chemical vapor deposition method, wherein the quantum well layer 512 covers the N-type layer 400, and the quantum well layer 512 comprises an indium gallium nitride layer.
Specifically, when the light emitting diode 10 does not include a stress relief structure layer, a multiple quantum well structure layer 500 may be prepared on the N-type layer 400. At this time, a quantum well layer 512 is first prepared on the N-type layer 400, and the quantum well layer 512 covers the N-type layer 400. The quantum well layer 512 may be fabricated using a chemical vapor deposition process. The quantum well layer 512 may be indium gallium nitride (In)xGa1-xN,0.22 is more than or equal to x is more than or equal to 0.20). The quantum well layer 512 may be 20nm to 40nm thick. That is, the thickness of the quantum well layer 512 may be 20nm, or may be40nm, or 30 nm.
When the light emitting diode 10 includes a stress relief structure layer, a multiple quantum well structure layer 500 may be fabricated on the stress relief structure layer. At this time, a quantum well layer 512 is firstly prepared on the stress release structure layer, and the quantum well layer 512 covers the stress release structure layer. The quantum well layer 512 may be fabricated using a chemical vapor deposition process. The quantum well layer 512 may be indium gallium nitride (In)xGa1-xN,0.22 is more than or equal to x is more than or equal to 0.20). The quantum well layer 512 may be 20nm to 40nm thick. That is, the thickness of the quantum well layer 512 may be 20nm, 40nm, or 30 nm.
And S520, continuing to prepare the quantum barrier layer 514 by using a chemical vapor deposition method to cover the quantum well layer 512, wherein the quantum barrier layer 514 comprises a silicon-doped gallium nitride layer.
Specifically, a quantum barrier layer 514 is formed on the surface of the quantum well layer 512 away from the N-type layer 400. The quantum barrier layer 514 covers the quantum well layer 512. The quantum barrier layer 514 may be fabricated using a chemical vapor deposition process. The quantum barrier layer 514 may be a silicon-doped gallium nitride layer. The thickness of the quantum barrier layer 514 may be 100nm to 140 nm. That is, the thickness of the quantum barrier layer 514 may be 100nm, 140nm, or 120 nm.
S530, repeating the above steps 8 to 15 times to prepare the multiple quantum well structure layer 500.
Specifically, quantum well layers 512 and quantum barrier layers 514 constitute cycles to form quantum well structure layers, generally speaking, the quantum well structure layers constituting the multiple quantum well structure layer 500 may be 8 to 15, that is, the multiple quantum well structure layer 500 may be formed by stacking 8 quantum well structure layers, 15 quantum well structure layers, or 12 quantum well structure layers, and thus, the multiple quantum well structure layer 500 may be formed by repeating the above steps S510 and S520 eight to fifteen times.
In embodiments, the step S600 includes preparing a 100nm to 120nm thick magnesium-doped gallium nitride layer by using a chemical vapor deposition method at a growth temperature ranging from 900 ℃ to 1000 ℃ to cover the multi-quantum well structure layer 500 to form the P-type semiconductor layer 600.
Specifically, a P-type semiconductor layer 600 is prepared on the surface of the multiple quantum well structure layer 500 away from the N-type layer 400, covering the multiple quantum well structure layer 500. The P-type semiconductor layer 600 may be prepared using a chemical vapor deposition method at a growth temperature range of 900 to 1000 ℃. In other words, the growth temperature of the P-type semiconductor layer 600 may be 900 ℃, 1000 ℃, or 950 ℃. The P-type semiconductor layer 600 may be a P-type gallium nitride layer, and specifically may be a magnesium-doped gallium nitride layer. The thickness of the P-type semiconductor layer 600 may be 100nm to 120 nm. That is, the thickness of the P-type semiconductor layer 600 may be 100nm, 120nm, or 110 nm.
The present application also provides light emitting diodes 10, which are prepared based on the above-described embodiments, and include a substrate 100, a U-type gallium nitride layer 200, a N-type gallium nitride layer 300, an N-type layer 400, a multiple quantum well structure layer 500, and a P-type semiconductor layer 600.
Specifically, the substrate 100 is located at the bottom of the light emitting diode 10, and its may be a sapphire substrate, a silicon carbide substrate or other types of substrates.
The th U-shaped gallium nitride layer 200 is located over the substrate 100 and covers the th surface 102 of the substrate 100. the th U-shaped gallium nitride layer 200 may be an undoped gallium nitride layer.
The st N-type GaN layer 300 covers the th U-type GaN layer 200 to generate electrons under the action of an electric field the th N-type GaN layer 300 can be a silicon-doped GaN layer.
The N-type layer 400 covers the th N-type gallium nitride layer 300, the N-type layer 400 may generally include an aluminum indium nitride layer 412, a silicon nitride layer 414, and a second N-type gallium nitride layer 416, which are stacked, wherein the aluminum indium nitride layer 412 covers the th N-type gallium nitride layer 300, the silicon nitride layer 414 covers the aluminum indium nitride layer 412, and the second N-type gallium nitride layer 416 covers the silicon nitride layer 414.
The multiple quantum well structure layer 500 covers the N-type layer 400 for improving the recombination efficiency of electrons and holes, the multiple quantum well structure layer 500 may generally include quantum wells and quantum barriers alternately stacked.
The P-type layer may be a semiconductor layer doped with P-type impurities, such as a magnesium-doped gallium nitride layer, and is located above the multiple quantum well structure layer 500, covering the multiple quantum well structure layer 500.
When the light emitting diode 10 works, the P-type layer can generate holes, the N-type gallium nitride layer 300 and the N-type layer 400 can generate electrons, and the electrons and the holes can compositely emit light in the multiple quantum well structure layer 500. in the light emitting diode 10, because the energy level of the indium aluminum nitride layer 412 is higher and the lattice of the indium aluminum nitride is close to that of the gallium nitride material, the lattice quality of the light emitting diode 10 can be improved, so that the light emitting effect of the light emitting diode 10 is improved.
In embodiments, the N-type gan layer 300 is a silicon-doped gan layer, and the N-type gan layer 300 has a thickness ranging from 0.5 μm to 1 μm, i.e., the N-type gan layer 300 may have a thickness of 0.5 μm or 1 μm.
, the silicon concentration of th gallium nitride layer is 1 × 1019/cm3To 4X 1019/cm3That is, in the gallium nitride layer of th, the concentration of silicon may be 1 × 1019/cm3Or can also beTo be 4 × 1019/cm3It may be 2.5X 1019/cm3。
In embodiments, the LED 10 may include a plurality of stacked N-type layers 400, where a plurality refers to three or more, generally indicates that the LED 10 may include 3 to 10 stacked N-type layers 400, and the plurality of N-type layers 400 are stacked and covered along the stacking direction of the LED 10.
, the second N-type GaN layer 416 has a silicon concentration in the range of 1 × 1019/cm3To 4X 1019/cm3. That is, the concentration of silicon in the second gallium nitride layer may be 1 × 1019/cm3And may be 4X 1019/cm3It may be 2.5X 1019/cm3。
In embodiments, the light emitting diode 10 further comprises a buffer layer 700. the buffer layer 700 covers the substrate 100 and is disposed between the substrate 100 and the U-shaped gallium nitride layer 200.
, the buffer layer 700 includes a second U-shaped gan layer with a thickness ranging from 25nm to 35nm, i.e. the buffer layer 700 may have a thickness of 25nm, 35nm, or 30 nm.
In embodiments, the light emitting diode 10 includes a plurality of the multiple quantum well structure layers 500, and the multiple quantum well structure layers 500 are stacked and covered along a stacking direction of the light emitting diode 10.
, the multiple quantum well structure layer 500 includes a quantum well layer 512 and a quantum barrier layer 514 that are stacked, the quantum well layer 512 includes an indium gallium nitride layer, and the quantum barrier layer 514 includes a silicon-doped gallium nitride layer.
In embodiments, the P-type semiconductor layer 600 is a magnesium-doped gallium nitride layer having a thickness in the range of 100nm to 120 nm.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1, A light-emitting diode, comprising:
a substrate (100);
an th U-shaped gallium nitride layer (200) covering the substrate (100);
an th N-type GaN layer (300) covering the th U-type GaN layer (200);
an N-type layer (400) covering the th N-type gallium nitride layer (300), the N-type layer (400) comprising an aluminum indium nitride layer (412), a silicon nitride layer (414), and a second N-type gallium nitride layer (416) in a stacked arrangement, the silicon nitride layer (414) covering the aluminum indium nitride layer (412), the second N-type gallium nitride layer (416) covering the silicon nitride layer (414);
a multiple quantum well structure layer (500) covering the N-type layer (400);
and the P-type semiconductor layer (600) covers the multi-quantum well structure layer (500).
2. The led of claim 1, wherein said N-type gan layer (300) is a silicon-doped gan layer, and wherein said N-type gan layer (300) has a thickness in the range of 0.5 to 1 μm.
3. The led of claim 2, wherein said N-type gan layer (300) has a si concentration in the range of 1 to 11019/cm3To 4X 1019/cm3。
4. The led of claim 1, wherein said led (10) comprises a plurality of said N-type layers (400), said plurality of N-type layers (400) being stacked and covered in a stacking direction of said led (10).
5. The LED of claim 4, wherein the second N-type GaN layer (416) has a silicon concentration in the range of 1 x 1019/cm3To 4X 1019/cm3。
6. The light-emitting diode according to claim 1, further comprising:
and the buffer layer (700) covers the substrate (100), and the buffer layer (700) is arranged between the substrate (100) and the U-shaped gallium nitride layer (200).
7. The led of claim 6, wherein said buffer layer (700) comprises a second U-shaped gallium nitride layer having a thickness in the range of 25nm to 35 nm.
8. The led of any one of claims 1-7 to , wherein the led (10) comprises a plurality of said multiple quantum well structure layers (500), and a plurality of said multiple quantum well structure layers (500) are stacked and covered along a stacking direction of the led (10).
9. The led of claim 8, wherein said multiple quantum well structure layer (500) comprises a quantum well layer (512) and a quantum barrier layer (514) stacked; the quantum well layer (512) comprises an indium gallium nitride layer; the quantum barrier layer (514) comprises a silicon-doped gallium nitride layer.
10. The led of claim 9, wherein said P-type semiconductor layer (600) is a magnesium-doped gallium nitride layer having a thickness in the range of 100nm to 120 nm.
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| CN110071199B (en) * | 2019-05-27 | 2024-02-23 | 芜湖德豪润达光电科技有限公司 | Light emitting diode and preparation method thereof |
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