CN209880544U - Semiconductor packaging structure and semiconductor multilayer chip packaging structure - Google Patents
Semiconductor packaging structure and semiconductor multilayer chip packaging structure Download PDFInfo
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- CN209880544U CN209880544U CN201920667688.7U CN201920667688U CN209880544U CN 209880544 U CN209880544 U CN 209880544U CN 201920667688 U CN201920667688 U CN 201920667688U CN 209880544 U CN209880544 U CN 209880544U
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Abstract
The utility model provides a semiconductor packaging structure, semiconductor packaging structure includes: the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, wherein the upper surface of the chip to be sealed is provided with a contraposition mark; the plastic packaging layer is formed on the upper surface of the chip to be packaged and comprises a metal column, a semi-sealed cavity and a plastic packaging material layer, wherein the metal column is positioned on the upper surface of the chip to be packaged and electrically connected with the metallization layer, the semi-sealed cavity is positioned on the periphery of the alignment mark, and the plastic packaging material layer wraps the metal column and the semi-sealed cavity; and the rewiring layer is positioned on the upper surface of the plastic packaging layer and comprises a dielectric layer and a metal wire layer positioned on the dielectric layer. The semi-sealed cavity capable of protecting the alignment mark from being polluted is introduced, so that the alignment mark can be directly exposed after plastic packaging without other additional processes, and accurate positioning is provided for subsequent processes.
Description
Technical Field
The utility model relates to a semiconductor technology encapsulation field especially relates to a semiconductor package structure and semiconductor multilayer chip package structure.
Background
With the trend of multi-functionalization and miniaturization of electronic products, high-density microelectronic assembly technology is becoming mainstream in new generation of electronic products. In order to match the development of the new generation of electronic products, especially the development of products such as smart phones, palm computers, super books and the like, the size of the chip is developed towards the directions of higher density, higher speed, smaller size, lower cost and the like. The emergence of the fan-out type wafer level packaging technology provides a wider development prospect for the improvement of the technology.
In the fan-out type multilayer packaging structure, the plastic packaging material used in the plastic packaging is a shading material, and after the plastic packaging process is finished, the alignment mark on the front layer can be shielded, so that the proper alignment mark meeting the high-precision requirement cannot be found in the subsequent processes of exposure, etching and the like.
Therefore, in the semiconductor chip package, how to perform accurate alignment after the plastic packaging process is a problem to be solved urgently by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor package structure, which is capable of shielding the alignment mark before the plastic package process by adding a half of sealing structure, so that the alignment mark can be directly exposed without additional process after the grinding process.
In order to achieve the above object, the present invention provides a semiconductor package structure, the package structure includes:
the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, wherein the upper surface of the metallization layer is provided with a contraposition mark;
the plastic packaging layer is formed on the upper surface of the chip to be packaged and comprises a metal column, a semi-sealed cavity and a plastic packaging material layer, wherein the metal column is positioned on the upper surface of the chip to be packaged and electrically connected with the metallization layer, the semi-sealed cavity is positioned on the periphery of the alignment mark, and the plastic packaging material layer wraps the metal column and the semi-sealed cavity;
the rewiring layer is positioned on the upper surface of the plastic packaging layer and comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, wherein the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
Optionally, an adhesive layer is further disposed between the semi-sealed cavity and the metallization layer.
Optionally, the cross-sectional shape of the semi-sealed cavity comprises a circle, a triangle, a square, or a hexagon.
Optionally, the metallization layer includes a dielectric layer and a metal interconnection structure formed in the dielectric layer, and a material of the metal interconnection structure includes any one of copper, aluminum, and titanium.
Optionally, the upper surface of the metal interconnection structure is flush with or higher than the upper surface of the dielectric layer.
Optionally, the material of the metal pillar includes any one of copper, aluminum, and titanium.
Optionally, the material of the semi-sealed cavity comprises glass, plastic, ceramic, metal.
Optionally, the material of the plastic package layer includes one of an epoxy-based resin, a liquid thermosetting epoxy resin, and a plastic compound.
The utility model provides a semiconductor multilayer chip packaging structure, which is characterized in that the structure comprises at least one second metallization layer bonded on the semiconductor chip packaging structure, and the upper surface of the second metallization layer is provided with a contraposition mark; the second plastic package layer comprises a second metal column, a second semi-sealed cavity and a second plastic package layer, wherein the second metal column is positioned on the upper surface of the second metallization layer and is electrically connected with the second metallization layer, the second semi-sealed cavity is positioned at the periphery of the second alignment mark, and the second plastic package layer wraps the second metal column and the second semi-sealed cavity; and the second redistribution layer is formed on the upper surface of the second plastic packaging layer.
As described above, the utility model discloses in semiconductor chip package, through introducing the semi-sealed cavity that is located above the counterpoint mark, can protect the counterpoint mark not blocked by the plastic envelope material, in subsequent processing procedure, do not make the counterpoint mark show out through other process means, provide clear visible counterpoint mark for subsequent exposure, photoetching process, eliminate the problem of counterpoint failure.
Drawings
Fig. 1 shows a flow chart of a process for fabricating a semiconductor package structure.
FIG. 2 is a schematic diagram of providing a chip to be sealed with alignment marks
FIG. 3 is a schematic diagram illustrating a deposited metal pillar according to an embodiment.
Fig. 4 is a schematic view illustrating a mounting of a semi-sealed cavity according to a first embodiment.
FIG. 5 is a schematic view after molding according to the first embodiment.
FIG. 6 is a schematic view of the first embodiment after polishing.
Fig. 7 is a schematic diagram illustrating the formation of a redistribution layer according to the first embodiment.
Fig. 8 is a schematic view of a semiconductor multilayer chip package according to a second embodiment.
Description of the element reference numerals
10 chip to be sealed
11 metallization layer
12 plastic packaging layer
13 rewiring layer
101 substrate
102 alignment mark
111 dielectric layer
112 metal interconnection structure
121 plastic packaging material layer
122 semi-sealed cavity
123 metal column
131 dielectric layer
132 metal wire layer
21 second metallization layer
22 second plastic-sealed layer
23 second rewiring layer
211 second dielectric layer
212 second metal interconnect structure
221 second molding compound layer
222 second semi-sealed cavity
223 second metal column
231 second dielectric layer
232 second metal wire layer
202 second alignment mark
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only schematic and illustrative of the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
Example one
As shown in fig. 1 to 7, the present embodiment provides a semiconductor package structure and a method for manufacturing the same.
As shown in fig. 7, the semiconductor package structure provided in this embodiment includes: the semiconductor package comprises a substrate 101, a metallization layer 11 located on the substrate, an alignment mark 102 marked on the metallization layer, and a molding compound layer 12 located on the upper surface of the metallization layer, wherein the molding compound layer 12 comprises a metal pillar 123 located on the metallization layer and electrically connected with the metallization layer, a semi-sealed cavity 122 located at the periphery of the alignment mark 102, a molding compound layer 121 located on the metallization layer and covering the metal pillar and the semi-sealed cavity, and a redistribution layer 13 located on the molding compound layer 12, wherein the redistribution layer 13 comprises a dielectric 131 and a metal wire layer 132, and the redistribution layer 13 is electrically connected with the metallization layer 11 through the metal pillar 123.
Referring to fig. 1, the method for manufacturing a semiconductor package structure includes the following steps:
1) providing a chip to be sealed with an alignment mark, wherein the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, and the alignment mark is positioned on the upper surface of the chip to be sealed;
2) depositing a metal column which is formed on the upper surface of the chip to be sealed and electrically connected with the metallization layer;
3) mounting a semi-sealed cavity, wherein the semi-sealed cavity is a cavity with one surface opened and the other surface closed, and the opening of the semi-sealed cavity is buckled on the alignment mark;
4) plastic packaging, namely completely coating the metal column and the semi-sealed cavity with a plastic packaging material, and forming a plastic packaging layer on the metallization layer;
5) grinding, namely grinding the plastic packaging layer until the upper surface of the metal column and the alignment mark are exposed;
6) and forming a rewiring layer, wherein the rewiring layer comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
The technical solution of the present embodiment is further described in detail with reference to the accompanying drawings.
As shown in fig. 2, step 1) is performed to provide a chip to be sealed 10 with an alignment mark, where the chip to be sealed 10 includes: the semiconductor device comprises a substrate 101, a metallization layer 11 located above the substrate, wherein the metallization layer 11 comprises a dielectric layer 111 and a metal interconnection structure 112 located in the dielectric layer; the alignment mark 102 is located on the chip to be tested.
Optionally, the material of the metal interconnection structure includes any one of copper, aluminum, and titanium. The upper surface of the metal interconnection structure is flush with or higher than the upper surface of the dielectric layer.
Specifically, in this embodiment, metal copper is used as a material for the metal interconnection structure, and the upper surface of the metal interconnection structure is higher than the upper surface of the dielectric layer.
As shown in fig. 3, step 2) is performed to deposit metal pillars 123 to form electrical connections with the metallization layer 11.
Optionally, the preparation method of the metal pillar includes an electroplating process and a wire bonding process.
Optionally, the material of the metal pillar includes any one of copper, aluminum, and titanium.
As shown in fig. 4, step 3) is performed, and the semi-sealed cavity 122 is mounted, so that the semi-sealed cavity is buckled on the alignment mark 102. The semi-sealed cavity can ensure that the plastic package material can not be poured onto the alignment mark in the subsequent plastic package process, thereby providing a clear alignment point for the subsequent process.
The semi-sealed cavity is a cavity with one open side and the other closed side. The semi-sealed cavity can be of a three-dimensional structure such as a hemisphere, a column and the like. The cross section of the cavity can be square, hexagonal, circular, triangular or any other shape. The cross sectional area of the semi-sealed cavity is larger than the surface area of the alignment mark, so that the semi-sealed cavity can completely cover the alignment mark, and the alignment mark is prevented from being polluted by the plastic package material.
Optionally, the material of the semi-sealed cavity comprises glass, plastic, ceramic, metal.
In the step 3), the semi-sealed cavity is fixed above the alignment mark in a mounting mode. In this embodiment, the mounting manner of the semi-sealed cavity includes the following steps:
3-1) coating an adhesive on the opening surface of the semi-sealed cavity;
3-2) buckling the side coated with the adhesive on the alignment mark and adhering and fixing the side coated with the adhesive on the metalized layer.
Therefore, an adhesive layer (not shown) is also provided between the fixed semi-sealed cavity and the metallization layer.
As shown in fig. 5, step 4) is performed to perform plastic package, and a plastic package layer 12 is formed on the surface of the metallization layer. And plastic packaging is carried out on the structure by adopting a plastic packaging material, the metal column and the semi-sealed cavity are completely wrapped, and the upper surface of a plastic packaging layer formed after plastic packaging is higher than the upper surfaces of the semi-sealed cavity and the metal column. The molding compound layer 12 includes a metal pillar 123 located on the metallization layer and electrically connected to the metallization layer, a semi-sealed cavity 122 located at the periphery of the alignment mark 102, and a molding compound layer 121 located on the metallization layer and covering the metal pillar and the cavity wall.
Optionally, the material used for plastic package includes one of epoxy-based resin, liquid thermosetting epoxy resin, and plastic compound.
Optionally, the plastic package adopts a process including a compression molding process, a liquid seal molding process, a spin coating process, and a transfer molding process.
As shown in fig. 6, step 5) is performed to polish the molding layer 12 until the alignment mark 102 is exposed and the metal pillar 123 is exposed.
Optionally, the abrading means comprises chemical mechanical polishing.
As shown in fig. 7, step 6) is performed to form a redistribution layer 13 on the upper surface of the molding compound layer 12, wherein the redistribution layer 13 includes a dielectric layer 131 and a patterned metal wire layer 132 located in the dielectric layer 131. Specifically, the method for preparing the rewiring layer at least comprises the following steps:
and 6-1) depositing a dielectric layer, wherein the dielectric layer fills the hole surrounded by the cavity wall of the semi-sealed cavity and covers the plastic packaging layer and the upper surface of the metal column.
6-2) exposing the upper surface of the metal column by photoetching and etching,
6-3) forming a metal wire layer, and forming a patterned metal wire layer by photoetching and etching.
Optionally, the material of the metal wire layer includes any one of copper, aluminum, gold, nickel, and titanium. The metal wire layer can be formed by physical vapor deposition, chemical vapor deposition, magnetron sputtering or electroplating, chemical plating and other processes.
As described above, in the semiconductor package structure and the manufacturing method thereof provided by this embodiment, the semi-sealed cavity located above the alignment mark is introduced, so that the alignment mark can be protected from being blocked by the plastic encapsulant, and the alignment mark can be directly exposed without using other additional means in the subsequent process requiring alignment.
Example two
In this embodiment, on the basis of the semiconductor chip package structure provided in the first embodiment, at least one chip is bonded to the redistribution layer in the first embodiment, so as to form a semiconductor multilayer chip package structure having multiple chips.
As an example, as shown in fig. 8, the semiconductor two-layer chip package structure provided by the present embodiment includes: a second metallization layer 21 overlying the structure provided in the first embodiment, the second metallization layer 21 being electrically connected to the redistribution layer 13 in the first embodiment, the second metallization layer 21 having a second alignment mark 202 on an upper surface thereof; the second molding compound layer 22 is located on the upper surface of the second metallization layer 21, the second molding compound layer 22 includes a second metal pillar 223 located on the second metallization layer and electrically connected to the second metallization layer, a second semi-sealed cavity 222 located on the periphery of the second alignment mark 202, a second molding compound layer 221 located on the second metallization layer and covering the second metal pillar and the second semi-sealed cavity, and a second redistribution layer 23 located on the second molding compound layer 22, wherein the second redistribution layer 23 includes a second dielectric layer 231 and a second metal wire layer 232, and the second redistribution layer 23 is electrically connected to the second metallization layer 21 through the metal pillar 223. In this embodiment, the same reference numerals are used for the same parts as those in the first embodiment, and the description thereof is omitted.
The preparation method of the semiconductor two-layer chip packaging structure provided by the embodiment comprises the following steps: by repeating the steps 2) to 6) in the first embodiment on the basis of the semiconductor chip packaging method provided in the first embodiment, the semiconductor two-level chip packaging structure provided in this embodiment can be formed.
In another example, the method for manufacturing the semiconductor multilayer chip package structure further includes repeating steps 2) to 6) in the first step for multiple times to obtain the semiconductor multilayer chip package structure.
As described above, in the process of manufacturing the semiconductor multilayer chip package structure, the semi-sealed cavity capable of protecting the alignment mark from being contaminated by the molding compound is introduced for many times, so that the alignment mark can be directly exposed without other additional processes after plastic packaging, a visible alignment mark is provided for subsequent exposure, photoetching and other processes, and the problem of alignment failure is solved.
To sum up, the utility model discloses a semiconductor chip packaging structure, the structure includes: the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, wherein the upper surface of the metallization layer is provided with a contraposition mark; the plastic packaging layer is formed on the upper surface of the chip to be packaged and comprises a metal column, a semi-sealed cavity and a plastic packaging material layer, wherein the metal column is positioned on the upper surface of the chip to be packaged and electrically connected with the metallization layer, the semi-sealed cavity is positioned on the periphery of the alignment mark, and the plastic packaging material layer wraps the metal column and the semi-sealed cavity; the rewiring layer is positioned on the upper surface of the plastic packaging layer and comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, wherein the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column. The semi-sealed cavity capable of protecting the alignment mark from being polluted by the plastic package material is introduced once or for multiple times, so that the alignment mark can be directly exposed after plastic package without other additional processes, and accurate positioning is provided for subsequent processes.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A semiconductor package, comprising:
the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, wherein the upper surface of the metallization layer is provided with a contraposition mark;
the plastic packaging layer is formed on the upper surface of the chip to be packaged and comprises a metal column, a semi-sealed cavity and a plastic packaging material layer, wherein the metal column is positioned on the upper surface of the chip to be packaged and electrically connected with the metallization layer, the semi-sealed cavity is positioned on the periphery of the alignment mark, and the plastic packaging material layer wraps the metal column and the semi-sealed cavity;
the rewiring layer is positioned on the upper surface of the plastic packaging layer and comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, wherein the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
2. The semiconductor package of claim 1, wherein an adhesive layer is further disposed between the semi-sealed cavity and the metallization layer.
3. The semiconductor package structure of claim 1, wherein a cross-sectional shape of the semi-sealed cavity comprises a circle, a triangle, a square, or a hexagon.
4. The semiconductor package structure of claim 1, wherein the metallization layer comprises a dielectric layer and a metal interconnect structure formed in the dielectric layer, and a material of the metal interconnect structure comprises any one of copper, aluminum, and titanium.
5. The semiconductor package structure of claim 4, wherein an upper surface of the metal interconnect structure is flush with or higher than an upper surface of the dielectric layer.
6. The semiconductor package structure of claim 1, wherein the metal pillar comprises a material selected from the group consisting of copper, aluminum, and titanium.
7. The semiconductor package structure of claim 1, wherein the material of the semi-sealed cavity comprises glass, plastic, ceramic, metal.
8. The semiconductor package structure of claim 1, wherein the material of the plastic encapsulation layer comprises one of an epoxy-based resin, a liquid thermosetting epoxy resin, and a plastic compound.
9. A semiconductor multilayer chip package structure, comprising at least a second metallization layer bonded on the semiconductor package structure of claim 1, wherein the second metallization layer has alignment marks on its upper surface; the second plastic package layer comprises a second metal column, a second semi-sealed cavity and a second plastic package layer, wherein the second metal column is positioned on the upper surface of the second metallization layer and is electrically connected with the second metallization layer, the second semi-sealed cavity is positioned at the periphery of the second alignment mark, and the second plastic package layer wraps the second metal column and the second semi-sealed cavity; and the second redistribution layer is formed on the upper surface of the second plastic packaging layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920667688.7U CN209880544U (en) | 2019-05-10 | 2019-05-10 | Semiconductor packaging structure and semiconductor multilayer chip packaging structure |
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| CN201920667688.7U CN209880544U (en) | 2019-05-10 | 2019-05-10 | Semiconductor packaging structure and semiconductor multilayer chip packaging structure |
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| CN209880544U true CN209880544U (en) | 2019-12-31 |
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| CN201920667688.7U Active CN209880544U (en) | 2019-05-10 | 2019-05-10 | Semiconductor packaging structure and semiconductor multilayer chip packaging structure |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |