CN113035832A - Wafer-level chip packaging structure, manufacturing method thereof and electronic equipment - Google Patents

Wafer-level chip packaging structure, manufacturing method thereof and electronic equipment Download PDF

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Publication number
CN113035832A
CN113035832A CN202110568594.6A CN202110568594A CN113035832A CN 113035832 A CN113035832 A CN 113035832A CN 202110568594 A CN202110568594 A CN 202110568594A CN 113035832 A CN113035832 A CN 113035832A
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layer
chip
wafer
manufacturing
aluminum pad
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CN113035832B (en
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吴春悦
何正鸿
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Forehope Electronic Ningbo Co Ltd
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Forehope Electronic Ningbo Co Ltd
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
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Abstract

The application provides a wafer-level chip packaging structure, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. In the wafer level chip packaging structure, a first re-wiring layer and a second re-wiring layer are respectively arranged on two sides of a chip, an aluminum pad is connected with the first re-wiring layer, the first re-wiring layer is connected with the second re-wiring layer through a conductive column, and a metal lug of the wafer level chip packaging structure is connected with the second re-wiring layer. The wafer level chip packaging structure has better stability and is not easy to generate local fracture due to thermal shock. In addition, since two rewiring layers are provided, more functions can be integrated, and the degree of integration is high. The manufacturing method provided by the application is used for manufacturing the wafer-level chip packaging structure, and the electronic equipment provided by the application comprises the wafer-level chip packaging structure.

Description

Wafer-level chip packaging structure, manufacturing method thereof and electronic equipment
Technical Field
The application relates to the technical field of semiconductors, in particular to a wafer-level chip packaging structure, a manufacturing method thereof and electronic equipment.
Background
In the existing chip packaging structure, a chip is often flipped on a substrate, and the thermal expansion coefficients of the chip and the substrate connected with the chip are different, so that when the chip is subjected to thermal shock, large stress is generated between the chip and the substrate, which causes the connection between the chip and the substrate to be unstable and easy to break. And is limited by the packaging mode, the existing wafer level chip packaging structure is not easy to realize high-density integration of more functions (such as an antenna function and a shielding function).
Disclosure of Invention
The present disclosure provides a wafer level chip package structure, a method for manufacturing the same, and an electronic device, which have better structural stability and can integrate more functions with high density.
The embodiment of the application can be realized as follows:
in a first aspect, the present application provides a wafer level chip package structure, including:
the chip is provided with a first surface and a second surface which are opposite, and the first surface is provided with an aluminum pad;
the plastic package body wraps the first surface and the side surface of the chip, and the plastic package body exposes the aluminum pad of the chip;
the first rewiring layer is positioned on one side, facing the first surface of the chip, and is electrically connected with the aluminum pad of the chip;
a functional structure electrically connected to the first re-wiring layer, the functional structure including at least one of an antenna structure and a shield layer;
a second rewiring layer covering the second surface of the chip and the plastic package body, the second rewiring layer and the first rewiring layer being electrically connected through a conductive post penetrating through the plastic package body;
and a metal bump electrically connected to the second re-wiring layer.
In an optional embodiment, the wafer-level chip package structure further includes a passivation layer covering the surface of the plastic package body and exposing the aluminum pad through the opening, and the redistribution layer is electrically connected to the aluminum pad through the opening of the passivation layer.
In an alternative embodiment, the first redistribution layer includes a first line and a first dielectric material encasing the first line, the first line being electrically connected to the functional structure through an opening in the first dielectric material;
the second rewiring layer comprises a second line and a second dielectric material wrapping the second line, and the metal bump is electrically connected with the second line through an opening in the second dielectric material.
In an optional embodiment, the functional structure includes a shielding layer and an antenna structure, the shielding layer is disposed on a side of the first redistribution layer away from the chip and connected to a ground terminal of the first redistribution layer; the antenna structure is located on the surface of the wafer-level chip packaging structure and connected with the feedback end of the first re-wiring layer.
In an alternative embodiment, the antenna structure is arranged alongside the shielding layer or at least partially overlaps the shielding layer.
In an alternative embodiment, the chip comprises a first chip and a second chip having different functions.
In an alternative embodiment, a shielding heat conduction layer is further arranged between the second surface of the chip and the second rewiring layer.
In a second aspect, the present application provides a method for manufacturing a wafer level chip package structure, including:
obtaining a chip, wherein the chip is provided with a first surface and a second surface which are opposite, the first surface is provided with an aluminum pad, and the second surface of the chip is attached to a carrier;
manufacturing a plastic package body to wrap the first surface and the side surface of the chip and expose the aluminum pad of the chip;
manufacturing a first rewiring layer electrically connected with the aluminum pad;
manufacturing a functional structure on the first rewiring layer, wherein the functional structure comprises at least one of an antenna structure and a shielding layer;
removing the carrier, wherein a connecting hole is formed in the plastic package body, the connecting hole extends to the first rewiring layer from one side, adjacent to the second surface of the chip, of the plastic package body, and a conductive material is filled in the connecting hole to form a conductive column connected with the first rewiring layer;
manufacturing a second re-wiring layer covering the second surface of the chip and the plastic package body, wherein the second re-wiring layer is electrically connected with the conductive columns;
and manufacturing a metal bump electrically connected with the second re-wiring layer.
In an alternative embodiment, before the step of fabricating the first re-wiring layer electrically connected to the aluminum pad, the fabrication method further includes: manufacturing a passivation layer on the plastic package body, wherein the passivation layer is provided with an opening so as to expose the aluminum pad;
a step of fabricating a first re-wiring layer electrically connected to the aluminum pad, comprising:
laying a first layer of dielectric material on the passivation layer, and slotting on the first layer of dielectric material to form a line pattern;
manufacturing a first circuit according to the circuit pattern, wherein the first circuit is connected with the aluminum pad through the opening of the passivation layer;
and laying a second layer of dielectric material on the first layer of dielectric material and the first circuit, and manufacturing a connecting end which is connected with the first circuit and exposed on the surface of the second layer of dielectric material, wherein the connecting end is used for connecting with the functional structure.
In an alternative embodiment, the functional structure includes a shielding layer and an antenna structure, the connection terminal includes a ground terminal and a feedback terminal, and the step of fabricating the functional structure on the first redistribution layer includes:
manufacturing a shielding layer on the first rewiring layer, wherein the shielding layer is connected with a grounding end;
and manufacturing an antenna structure, wherein the antenna structure and the shielding layer are arranged side by side or at least partially overlapped on the shielding layer, and the antenna structure is connected with the feedback end.
In an alternative embodiment, before the manufacturing the second redistribution layer covering the second side of the chip and the plastic package body, the manufacturing method further includes:
and laying a shielding heat conduction layer on the second surface of the chip.
In a third aspect, the present application provides an electronic device, including the wafer-level chip package structure according to any one of the foregoing embodiments or the wafer-level chip package structure manufactured by the manufacturing method according to any one of the foregoing embodiments.
The beneficial effects of the embodiment of the application include, for example:
in the wafer level chip package structure of this embodiment, the first redistribution layer and the second redistribution layer are respectively disposed on two sides of the chip, the aluminum pad is connected to the first redistribution layer, the first redistribution layer is connected to the second redistribution layer through the conductive pillar, and the metal bump of the wafer level chip package structure is connected to the second redistribution layer. In addition, because two rewiring layers are arranged, the second rewiring layer is used for arranging the metal bumps, and related functional structures such as an antenna structure and a shielding layer can be integrated on the first rewiring layer, so that more functions can be realized, and the integration level is higher.
The manufacturing method provided by the embodiment of the application is used for manufacturing the wafer-level chip packaging structure, and the electronic device provided by the embodiment of the application comprises the wafer-level chip packaging structure or the wafer-level chip packaging structure manufactured by the manufacturing method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a schematic diagram of a wafer level chip package structure according to an embodiment of the present disclosure;
FIG. 2 is a flow chart illustrating a method for fabricating a wafer level chip package structure according to an embodiment of the present disclosure;
fig. 3 to 13 are schematic views illustrating a wafer level chip package structure in a manufacturing process according to an embodiment of the present invention.
Icon: 010-wafer level chip package structure; 100-a first chip; 110-a second chip; 120-aluminum pad; 130-a shielding heat conducting layer; 200-plastic package body; 210-a conductive post; 220-a passivation layer; 300 — a first rewiring layer; 310-a first line; 320-a first dielectric material; 330-ground terminal; 340-feedback end; 410-a shielding layer; 420-an antenna structure; 500-a second rewiring layer; 510-a second line; 520-a second dielectric material; 600-metal bumps; 020-carrier.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the present invention product is usually put into use, it is only for convenience of describing the present application and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present application.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
With the rapid development of the semiconductor industry, the flip-chip package structure is widely applied to the semiconductor industry. Flip chip packaging utilizes bumps for electrical connection between the chip (chip) and the substrate. The substrate is irreversibly plastically deformed under the influence of external force, temperature, humidity, and other conditions, and the thermal expansion coefficient of the chip material (silicon, thermal expansion coefficient of 2.5 ppm/DEG C) in the molding body is not matched with that of the substrate material (thermal expansion coefficient of 12 ppm/DEG C), so that the connection stability between the chip and the substrate is poor. And the existing wafer level chip packaging structure is not easy to integrate more functions with high density.
In order to solve at least one of the above problems in the prior art, embodiments of the present application provide a wafer level chip package structure, a method for manufacturing the same, and an electronic device.
Fig. 1 is a schematic diagram of a wafer level chip package structure 010 according to an embodiment of the present disclosure. As shown in fig. 1, the wafer level chip package structure 010 provided in this embodiment includes:
a chip having opposite first and second faces, the first face being provided with an aluminum pad 120;
a plastic package body 200 wrapping the first and side surfaces of the chip, the plastic package body 200 exposing the aluminum pad 120 of the chip;
a first re-wiring layer 300, the first re-wiring layer 300 being located on a side of the chip facing the first surface, the first re-wiring layer 300 being electrically connected to the aluminum pad 120 of the chip;
a functional structure electrically connected to the first re-wiring layer 300, the functional structure including at least one of the antenna structure 420 and the shielding layer 410;
a second redistribution layer 500 covering the second surface of the chip and the plastic package body 200, the second redistribution layer 500 being electrically connected to the first redistribution layer 300 through a conductive pillar 210 penetrating the plastic package body 200;
and a metal bump 600 electrically connected to the second re-wiring layer 500.
In this embodiment, the chips include a first chip 100 and a second chip 110 having different functions, and in alternative embodiments, the number of the chips may be one or more than three. Packaging multiple chips together can make the final wafer-level chip package structure 010 have stronger performance. It should be understood that the chip of the embodiment of the present application is provided with a microcircuit thereon, and is provided with an aluminum pad 120 as an output/receiving terminal of an electrical signal.
In the present embodiment, by providing the first and second re-wiring layers 300 and 500 on the sides of the first and second faces of the chip, respectively, the first re-wiring layer 300 and the second re-wiring layer 500 are connected by the conductive pillar 210, and the metal bump 600 is connected to the second re-wiring layer 500. Therefore, the aluminum pad 120 is finally connected to the metal bump 600 through the first re-wiring layer 300, the conductive pillar 210 and the second re-wiring layer, rather than directly connecting the metal bump 600 through the substrate as in the conventional structure, so that there is more buffer space from the aluminum pad 120 to the metal bump 600 when thermal shock is encountered, and fracture is not easily caused. In this embodiment, since both sides of the chip have redistribution layers, the first redistribution layer 300 can facilitate connection of functional structures, including the antenna structure 420 and/or the shielding layer 410, and can implement a corresponding shielding function or an antenna transceiving function. Therefore, the wafer-level chip package structure 010 provided by the embodiment of the application has more functions and higher integration level.
Specifically, in the embodiment, the wafer-level chip package structure 010 further includes a passivation layer 220, the passivation layer 220 covers the surface of the plastic package body 200, the aluminum pad 120 is exposed through the opening, and the redistribution layer is electrically connected to the aluminum pad 120 through the opening of the passivation layer 220. The passivation layer 220 may be made of a polymer dielectric material, such as epoxy, polyimide benzocyclobutene, etc.
As shown in fig. 1, the first re-wiring layer 300 includes a first line 310 and a first dielectric material 320 wrapping the first line 310, the first line 310 being electrically connected to the functional structure through an opening on the first dielectric material 320; the second redistribution layer 500 includes a second line 510 and a second dielectric material 520 wrapping the second line 510, and the metal bump 600 is electrically connected to the second line 510 through an opening on the second dielectric material 520. The first wire 310 is connected to the first wire 310 through the opening of the passivation layer 220, thereby realizing signal transmission.
Specifically, in the present embodiment, the functional structure includes an antenna structure 420 and a shielding layer 410, where the shielding layer 410 is disposed on a side of the first redistribution layer 300 away from the chip and connected to the ground terminal 330 of the first redistribution layer 300; the antenna structure 420 is located on the surface of the wafer-level chip package structure 010 and connected to the feedback terminal 340 of the first redistribution layer 300. The shielding layer 410 is made of a metal material, and is attached to the surface of the first dielectric material 320 of the first redistribution layer 300, and the ground terminal 330 connected to the first wiring 310 is connected to the shielding layer 410 through the first dielectric material 320. The grounding of the shielding layer 410 can provide a better electromagnetic shielding effect for the chip in the plastic package body 200, and the size of the shielding layer 410 can be designed as required, for example, in some embodiments, the shielding layer 410 can also cover the surface of the left side of the plastic package body 200.
In this embodiment, the antenna structure 420 is a layered structure, the antenna structure 420 partially overlaps the shielding layer 410, and a portion not overlapping the shielding layer 410 is connected to the first line 310 of the first redistribution layer 300 through the feedback terminal 340, in this embodiment, the feedback terminal 340 passes through the first dielectric material 320 of the first redistribution layer 300, and two ends of the feedback terminal are respectively connected to the antenna structure 420 and the first line 310. It is understood that in other embodiments of the present application, the antenna structure 420 may be disposed alongside the shielding layer 410, as long as the antenna structure is not shielded by the shielding layer 410 and can normally transmit and receive signals.
In the embodiment of the present invention, the conductive post 210 may be made of copper, gold, silver, or an alloy, or may be made of other conductive materials such as conductive adhesive.
In this embodiment, the metal bump 600 may include a UBM metal layer, a copper pillar, and a tin cap disposed at an end of the copper pillar. The specific structure can refer to a bump structure in the prior art. The second redistribution layer 500 has an opening in the second dielectric material 520, through which the metal bump 600 is electrically connected to the second wire 510 inside the second redistribution layer 500. The metal bumps 600 may be used for connecting with other circuit structures outside, for example, the metal bumps 600 may be connected with wires on a circuit board.
Optionally, in this embodiment, the wafer-level chip package structure 010 further includes a shielding heat conduction layer 130, and the shielding heat conduction layer 130 is disposed between the second surface of the chip and the second redistribution layer 500. The shielding heat conduction layer 130 is used for shielding the second side of the chip, and therefore includes a metal layer attached to the second sides of the first chip 100 and the second chip 110; in order to avoid interference with the electrical signal of the second redistribution layer 500, the shielding heat conductive layer 130 further includes an insulating layer covering the metal layer, so as to avoid electrical connection between the shielding heat conductive layer 130 and the second redistribution layer 500. In addition, the shielding heat-conducting layer 130 is attached to the second surface of the chip, so that the metal has better heat-conducting property, and is favorable for heat dissipation of the chip. In alternative embodiments, the shielding and heat conducting layer 130 may not be provided.
Fig. 2 is a flowchart illustrating a method for manufacturing the wafer-level chip package structure 010 according to an embodiment of the disclosure; fig. 3 to 13 are schematic views illustrating a wafer level chip package structure 010 in a manufacturing process according to an embodiment of the disclosure. As shown in fig. 2, a method for manufacturing a wafer-level chip package structure 010 provided by the embodiment of the present application includes:
step S100, a chip is obtained, the chip is provided with a first surface and a second surface which are opposite, an aluminum pad is arranged on the first surface, and the second surface of the chip is attached to a carrier.
Taking the fabrication of the wafer-level chip package structure 010 provided in the embodiment of the present application as an example, first obtain a chip, attach the second surface of the chip to the carrier 020, and make the first surface of the chip and the aluminum pad 120 face upward, as shown in fig. 3. In the present embodiment, the first chip 100 and the second chip 110 are obtained separately, and the first chip 100 and the second chip 110 have different functions, for example, the first chip 100 has a storage or processing function, and the second chip 110 has a function related to the rf antenna. In this embodiment, the material of the carrier 020 may be glass, silicon oxide, or metal. The carrier 020 can eliminate the warpage problem in the process. In order to facilitate the separation of the subsequent chip and the carrier 020, the surface of the carrier 020 can be pasted with a glue layer which is convenient for separation, and the chip is pasted on the glue layer. The glue layer may be a UV glue layer, which enables the carrier 020 to be separated from the structure provided thereon by illumination. In alternative embodiments, the glue layer includes, but is not limited to, an adhesive glue, Epoxy (Epoxy), Polyimide (PI).
And S200, manufacturing a first surface and a side surface of the plastic package body wrapping the chip, and exposing the aluminum pad of the chip.
Taking the wafer-level chip package structure 010 provided in the embodiment of the present application as an example, after the chips are mounted, the plastic package body 200 is fabricated to wrap the first surfaces and the side surfaces of the first chip 100 and the second chip 110, and the aluminum pads 120 are exposed so as to be connected to the redistribution layer in the subsequent fabrication, as shown in fig. 4.
In this embodiment, after the plastic package body 200 is completed, a passivation layer 220 is further disposed on the surface of the plastic package body 200, the passivation layer 220 has insulation properties, and the passivation layer 220 has an opening to expose the aluminum pad 120, as shown in fig. 5. Specifically, a coater may be used to uniformly coat a liquid passivation layer (passivation) on the plastic package 200 by spin coating, and then a Hot plate (Hot plate) is used to perform soft baking (soft cake) molding to form a film, a mask is used to cover the position of the predetermined opening of the passivation layer 220 by a Proximity (Proximity) method through an exposure machine without exposing to light, and a developing method is used to remove the unexposed area by spraying a developing solution to form an opening of the passivation layer 220, which exposes the aluminum pad 120. The passivation layer 220 is cured to a stable state of complete curing by Oven (Oven) heating again, and organic contaminants on the surface of the passivation layer 220 and residues in the opening are removed by plasma desmear (Descum). In the present embodiment, the passivation layer 220 may be made of a polymer dielectric material, such as epoxy, polyimide benzocyclobutene, etc.
Step S300, a first rewiring layer electrically connected with the aluminum pad of the chip is manufactured.
Taking the wafer-level chip package structure 010 provided in the embodiment of the present application as an example, the step includes laying a first layer of dielectric material on the passivation layer 220, and forming a groove on the first layer of dielectric material to form a circuit pattern. Then, a first wiring 310 is formed according to the wiring pattern, and the first wiring 310 is connected to the aluminum pad 120 through the opening of the passivation layer 220, as shown in fig. 6. A second layer of dielectric material is laid over the first layer of dielectric material and the first line 310, the first and second layers of dielectric material together forming a first dielectric material 320. Connection terminals are then made to the first lines 310 and exposed to the surface of the second layer of dielectric material, the connection terminals being used for connection to functional structures. In the present embodiment, the connection end includes a ground end 330 for connecting with the shielding layer 410 and a feedback end 340 for connecting with the antenna structure 420, since the antenna structure 420 of the present embodiment is partially overlapped on the shielding layer 410, after covering the second layer of dielectric material, the ground end 330 is fabricated first, and the structure shown in fig. 7 is obtained; the feedback terminal 340 is fabricated during subsequent fabrication of the antenna structure 420.
Specifically, in this embodiment, a coating machine may be used to spin-coat a photoresist on the passivation layer 220 (i.e., lay a first layer of dielectric material), and then a hot plate is used to perform a soft baking process to form a film, and an exposure-development process is used to remove the unexposed area with a developing solution to form the pattern of the first line 310. The first line 310 may then be prepared by one of a physical vapor deposition Process (PVD), a chemical vapor deposition process (CVD), sputtering, electroplating, or electroless plating. Then, the organic contaminants on the surface of the RDL circuit are removed again by using a plasma glue remover. A second layer of dielectric material is then overlaid on the first layer of dielectric material and the first trace 310, forming a first re-routing layer 300 (without ground 330 and feedback 340).
In the present embodiment, the dielectric material (the first layer of dielectric material and/or the second layer of dielectric material) may be amine-based cured epoxy material, epoxy polymer, polyimide, or the like.
The ground terminal 330 may be fabricated by: a ground terminal 330 is formed by laser drilling a hole in the first dielectric material 320 of the first redistribution layer 300 and sputtering metal into the hole.
Step S400, manufacturing a functional structure on the first redistribution layer, where the functional structure includes at least one of an antenna structure and a shielding layer.
Taking the wafer-level chip package structure 010 provided in the embodiment of the present application as an example, the functional structure includes the antenna structure 420 and the shielding layer 410, therefore, the step S400 specifically includes fabricating the shielding layer 410 on the first redistribution layer 300, and the shielding layer 410 is connected to the ground terminal 330; the antenna structure 420 is fabricated, the antenna structure 420 and the shielding layer 410 are disposed side by side or at least partially overlapped on the shielding layer 410, and the antenna structure 420 is connected to the feedback terminal 340.
Since the ground terminal 330 is already formed in step S300, the shielding layer 410 only needs to be formed on the surface of the first redistribution layer 300. Specifically, a groove for accommodating the shielding layer 410 may be first formed by photolithography and development, and then the shielding layer 410 is formed by electroplating in the groove, and the shielding layer 410 is connected to the ground terminal 330, as shown in fig. 8.
Next, the antenna structure 420 is fabricated by first forming a hole in the dielectric material by laser, then sputtering metal to form the feedback terminal 340, and then printing the antenna layer to form the antenna structure 420. In this embodiment, a portion of the antenna structure 420 overlaps the shielding layer 410, as shown in fig. 9.
Step S500, removing the carrier, forming a connection hole in the plastic package body, the connection hole extending from a side of the plastic package body adjacent to the second surface of the chip to the first redistribution layer, and filling the connection hole with a conductive material to form a conductive pillar connected to the first redistribution layer.
Taking the wafer-level chip package structure 010 provided in the embodiment of the present application as an example, after the carrier 020 is removed, the entire structure is turned over, a connection hole is opened on the plastic package body 200, the connection hole extends from a side of the plastic package body 200 adjacent to the second surface of the chip to the first redistribution layer 300, and then the connection hole is filled with a conductive material to form the conductive pillar 210 connected to the first redistribution layer 300, as shown in fig. 10.
Step S600, a second redistribution layer covering the second surface of the chip and the plastic package body is fabricated, and the second redistribution layer is electrically connected to the conductive pillar.
Taking the wafer-level chip package structure 010 provided in the embodiment of the present application as an example, before the second redistribution layer 500 is fabricated, the shielding heat conduction layer 130 may be further disposed on the second surface of the chip, as shown in fig. 11. The metal layer of the shielding heat conduction layer 130 can be formed by selecting a sputtering mode to play a shielding effect; an insulating layer is then laid outside the metal layer to electrically isolate the second redistribution layer 500 to be fabricated. After the shield heat conductive layer 130 is formed, a second redistribution layer 500 is formed. The second redistribution layer 500 includes a second line 510 and a second dielectric material 520 encasing the second line 510, the second line 510 connecting the conductive pillars 210. The second redistribution layer 500 is fabricated as shown in fig. 12. The manufacturing method of the second redistribution layer 500 is similar to the manufacturing method of the first redistribution layer 300, and is not repeated here.
In an alternative embodiment, the shielding heat conduction layer 130 may not be fabricated, and the second redistribution layer 500 may be fabricated directly.
Step S700, a metal bump electrically connected to the second redistribution layer is fabricated.
Taking the wafer-level chip package structure 010 provided in the embodiment of the present application as an example for manufacturing, the metal bump 600 includes a UBM metal layer, a copper pillar, and a tin cap disposed at an end of the copper pillar, so that an unexposed region can be removed by exposing and developing on the second dielectric material 520 of the second redistribution layer 500, an opening for disposing the UBM metal layer is exposed, and then the UBM metal layer is formed at the opening (a layer of Ti/Cu can be sputtered first and then a copper layer is sputtered again, wherein the first layer of Ti/Cu is mainly used to improve the bonding force of the second layer of copper), and the UBM metal layer is connected to the second circuit 510. And then manufacturing the copper cylinder, wherein the copper cylinder can be prepared by one of a physical vapor deposition Process (PVD), a chemical vapor deposition process (CVD), sputtering, electroplating or chemical plating. Then, the organic contaminants on the surface are removed again by using a plasma glue remover. And then, printing solder paste on the end part of the copper pillar by using a printing mode, and forming a solder cap by using a reflow baking mode. The structure shown in fig. 13 is finally obtained.
In the embodiment of the present invention, a connection hole is formed on the plastic package body 200 by a laser drilling method, and the conductive pillar 210 is formed in the connection hole, so that the first redistribution layer 300 is connected to the second redistribution layer 500. Through holing on plastic-sealed body 200, avoid leading to circuit layer and chip material fracture scheduling problem that the too big stress leads to at the chip trompil. And the heat conduction to the outside of the plastic package body 200 can be realized through the conductive pillars 210. The material of the plastic package body 200 can be prepared by adding a high thermal conductive material to epoxy-based resin (epoxy-based resin) and silicone-based resin (silicone-based resin). The high heat conduction material can be alumina heat conduction powder, nano alumina and the like.
In the embodiment of the application, two rewiring layers are distributed on two sides of a chip, so that more input/output points can be provided, and more functions can be integrated. Optionally, the thicknesses of the first redistribution layer 300 and the second redistribution layer 500 may be designed to be the same, and the materials have the same thermal expansion coefficients, so as to reduce the internal stress, and greatly improve the reliability of the overall structure.
In addition, the electronic device provided in the embodiment of the present application includes the wafer-level chip package structure 010 or the wafer-level chip package structure 010 manufactured by the manufacturing method.
In summary, in the wafer-level chip package structure 010 of the present embodiment, the first redistribution layer 300 and the second redistribution layer 500 are respectively disposed on two sides of the chip, the aluminum pad 120 is connected to the first redistribution layer 300, the first redistribution layer 300 is connected to the second redistribution layer 500 through the conductive pillar 210, and the metal bump 600 of the wafer-level chip package structure 010 is connected to the second redistribution layer 500, because the aluminum pad 120 is finally connected to the metal bump 600 through the first redistribution layer 300, the conductive pillar 210, and the second redistribution layer, rather than directly connecting the metal bump 600 through the substrate as in the conventional structure, there is more buffer space between the aluminum pad 120 and the metal bump 600 when thermal shock is encountered, and the fracture is not easily caused. In addition, because two redistribution layers are provided, the second redistribution layer 500 is used for providing the metal bump 600, and the first redistribution layer 300 can integrate related functional structures, such as the antenna structure 420 and the shielding layer 410, to achieve more functions and achieve higher integration.
The manufacturing method provided by the embodiment of the application is used for manufacturing the wafer-level chip package structure 010, and the electronic device provided by the embodiment of the application comprises the wafer-level chip package structure 010 or the wafer-level chip package structure 010 manufactured by the manufacturing method.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A wafer level chip package structure, comprising:
the chip is provided with a first surface and a second surface which are opposite, and the first surface is provided with an aluminum pad;
the plastic package body wraps the first surface and the side surface of the chip, and the plastic package body exposes the aluminum pad of the chip;
a first re-wiring layer located on a side of the chip facing the first face, the first re-wiring layer being electrically connected to the aluminum pad of the chip;
a functional structure electrically connected with the first re-wiring layer, the functional structure including at least one of an antenna structure and a shielding layer;
a second redistribution layer covering the second surface of the chip and the plastic package body, the second redistribution layer being electrically connected to the first redistribution layer through a conductive pillar penetrating the plastic package body;
and a metal bump electrically connected to the second redistribution layer.
2. The wafer level chip package structure of claim 1, further comprising a passivation layer covering a surface of the plastic package body and exposing the aluminum pad through an opening, wherein the redistribution layer is electrically connected to the aluminum pad through the opening of the passivation layer.
3. The wafer level chip package structure of claim 1, wherein the first redistribution layer comprises a first trace and a first dielectric material encapsulating the first trace, the first trace electrically connected to the functional structure through an opening in the first dielectric material;
the second rewiring layer comprises a second line and a second dielectric material wrapping the second line, and the metal bump is electrically connected with the second line through an opening in the second dielectric material.
4. The wafer-level chip package structure of claim 1, wherein the functional structure comprises the shielding layer and the antenna structure, the shielding layer is disposed on a side of the first redistribution layer away from the chip and connected to a ground terminal of the first redistribution layer; the antenna structure is located on the surface of the wafer-level chip packaging structure and connected with the feedback end of the first re-wiring layer.
5. The wafer-level chip package structure according to claim 4, wherein the antenna structure is disposed alongside or at least partially overlapping the shielding layer.
6. The wafer-level chip package structure of claim 2, wherein the chips comprise a first chip and a second chip having different functions.
7. The wafer-level chip package structure according to claim 1, wherein a shielding heat conduction layer is further disposed between the second surface of the chip and the second redistribution layer.
8. A method for manufacturing a wafer level chip package structure is characterized by comprising the following steps:
obtaining a chip, wherein the chip is provided with a first surface and a second surface which are opposite, the first surface is provided with an aluminum pad, and the second surface of the chip is attached to a carrier;
manufacturing a plastic package body to wrap the first surface and the side surface of the chip and expose the aluminum pad of the chip;
manufacturing a first rewiring layer electrically connected with the aluminum pad;
fabricating a functional structure on the first re-routing layer, the functional structure including at least one of an antenna structure and a shielding layer;
removing the carrier, forming a connecting hole on the plastic package body, wherein the connecting hole extends from one side of the plastic package body adjacent to the second surface of the chip to the first rewiring layer, and filling a conductive material in the connecting hole to form a conductive column connected with the first rewiring layer;
manufacturing a second redistribution layer covering the second surface of the chip and the plastic package body, wherein the second redistribution layer is electrically connected with the conductive column;
and manufacturing a metal bump electrically connected with the second re-wiring layer.
9. The method of fabricating a wafer level chip package structure according to claim 8, wherein before the step of fabricating the first re-wiring layer electrically connected to the aluminum pad, the method further comprises: manufacturing a passivation layer on the plastic package body, wherein the passivation layer is provided with an opening so as to expose the aluminum pad;
the step of fabricating a first redistribution layer electrically connected to the aluminum pad includes:
laying a first layer of dielectric material on the passivation layer, and grooving on the first layer of dielectric material to form a circuit pattern;
manufacturing a first circuit according to the circuit pattern, wherein the first circuit is connected with the aluminum pad through an opening of the passivation layer;
and laying a second layer of dielectric material on the first layer of dielectric material and the first line, and manufacturing a connecting end which is connected to the first line and exposed on the surface of the second layer of dielectric material, wherein the connecting end is used for being connected with the functional structure.
10. The method of claim 9, wherein the functional structure comprises the shielding layer and the antenna structure, the connecting terminal comprises a ground terminal and a feedback terminal, and the step of forming the functional structure on the first redistribution layer comprises:
manufacturing the shielding layer on the first rewiring layer, wherein the shielding layer is connected with the grounding end;
and manufacturing the antenna structure, wherein the antenna structure and the shielding layer are arranged side by side or at least partially overlapped on the shielding layer, and the antenna structure is connected with the feedback end.
11. The method of claim 8, wherein before the second redistribution layer covering the second side of the chip and the plastic-sealed body is formed, the method further comprises:
and laying a shielding heat conduction layer on the second surface of the chip.
12. An electronic device comprising the wafer-level chip package structure according to any one of claims 1 to 7 or the wafer-level chip package structure manufactured by the manufacturing method according to any one of claims 8 to 11.
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