CN111916362A - Semiconductor packaging structure and preparation method thereof - Google Patents

Semiconductor packaging structure and preparation method thereof Download PDF

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Publication number
CN111916362A
CN111916362A CN201910390440.5A CN201910390440A CN111916362A CN 111916362 A CN111916362 A CN 111916362A CN 201910390440 A CN201910390440 A CN 201910390440A CN 111916362 A CN111916362 A CN 111916362A
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China
Prior art keywords
layer
semi
sealed cavity
metal
metal column
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CN201910390440.5A
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Chinese (zh)
Inventor
吕娇
陈彦亨
吴政达
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201910390440.5A priority Critical patent/CN111916362A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, wherein the semiconductor packaging structure comprises: the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, wherein the upper surface of the chip to be sealed is provided with a contraposition mark; the plastic packaging layer is formed on the upper surface of the chip to be packaged and comprises a metal column, a semi-sealed cavity and a plastic packaging material layer, wherein the metal column is positioned on the upper surface of the chip to be packaged and electrically connected with the metallization layer, the semi-sealed cavity is positioned on the periphery of the alignment mark, and the plastic packaging material layer wraps the metal column and the semi-sealed cavity; and the rewiring layer is positioned on the upper surface of the plastic packaging layer and comprises a dielectric layer and a metal wire layer positioned on the dielectric layer. The semi-sealed cavity capable of protecting the alignment mark from being polluted is introduced, so that the alignment mark can be directly exposed after plastic packaging without other additional processes, and accurate positioning is provided for subsequent processes.

Description

Semiconductor packaging structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor technology packaging, in particular to a semiconductor packaging structure and a preparation method thereof.
Background
With the trend of multi-functionalization and miniaturization of electronic products, high-density microelectronic assembly technology is becoming mainstream in new generation of electronic products. In order to match the development of the new generation of electronic products, especially the development of products such as smart phones, palm computers, super books and the like, the size of the chip is developed towards the directions of higher density, higher speed, smaller size, lower cost and the like. The emergence of the fan-out type wafer level packaging technology provides a wider development prospect for the improvement of the technology.
In the fan-out type multilayer packaging structure, the plastic packaging material used in the plastic packaging is a shading material, and after the plastic packaging process is finished, the alignment mark on the front layer can be shielded, so that the proper alignment mark meeting the high-precision requirement cannot be found in the subsequent processes of exposure, etching and the like.
Therefore, in the semiconductor chip package, how to perform accurate alignment after the plastic packaging process is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, in which a half of the sealing structure is added to shield the alignment mark before the plastic package process, so that the alignment mark can be directly exposed without additional process after the grinding process.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor package structure, the method at least comprising the steps of:
1) providing a chip to be sealed with an alignment mark, wherein the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, and the alignment mark is positioned on the upper surface of the metallization layer;
2) depositing a metal column which is formed on the upper surface of the chip to be sealed and electrically connected with the metallization layer;
3) fixing the semi-sealed cavity; the semi-sealed cavity is a cavity with one open side and the other closed side, and the open side of the semi-sealed cavity is buckled on the alignment mark;
4) plastic packaging, namely completely coating the metal column and the semi-sealed cavity with a plastic packaging material, and forming a plastic packaging layer on the metallization layer;
5) grinding, namely grinding the plastic packaging layer until the upper surface of the metal column and the alignment mark are exposed;
6) and forming a rewiring layer, wherein the rewiring layer comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
Optionally, in the step 3), the manner of fixing the semi-sealed cavity includes mounting.
Optionally, the mounting step includes at least:
3-1) coating an adhesive on the opening surface of the semi-sealed cavity;
3-2) buckling the side coated with the adhesive on the alignment mark and adhering and fixing the side coated with the adhesive on the metalized layer.
Optionally, the metallization layer includes a dielectric layer and a metal interconnection structure formed in the dielectric layer, and a material of the metal interconnection structure includes any one of copper, aluminum, and titanium.
Optionally, the upper surface of the metal interconnection structure is flush with or higher than the upper surface of the dielectric layer.
Optionally, the preparation method of the metal pillar includes a wire bonding process and an electroplating process.
Optionally, the material of the metal pillar includes any one of copper, aluminum, and titanium.
Optionally, the material of the semi-sealed cavity comprises glass, plastic, ceramic, metal.
Optionally, the material of the molding compound includes one of an epoxy-based resin, a liquid thermosetting epoxy resin, and a plastic compound.
Optionally, the plastic packaging includes a compression molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process, or a spin coating process.
Optionally, the grinding comprises chemical mechanical polishing.
Optionally, the step 6) comprises at least the following steps:
6-1) forming a dielectric layer on the upper surface of the plastic packaging layer, wherein the dielectric layer fills the semi-sealed cavity and covers the plastic packaging layer;
6-2) exposing the upper surface of the metal column through a photoetching process;
6-3) forming a metal wire layer on the upper surface of the dielectric layer, wherein the metal wire layer is electrically connected with the metal column.
The present invention also provides a semiconductor package structure, including:
the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, wherein the upper surface of the metallization layer is provided with a contraposition mark;
the plastic packaging layer is formed on the upper surface of the chip to be packaged and comprises a metal column, a semi-sealed cavity and a plastic packaging material layer, wherein the metal column is positioned on the upper surface of the chip to be packaged and electrically connected with the metallization layer, the semi-sealed cavity is positioned on the periphery of the alignment mark, and the plastic packaging material layer wraps the metal column and the semi-sealed cavity;
the rewiring layer is positioned on the upper surface of the plastic packaging layer and comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, wherein the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
Optionally, an adhesive layer is further disposed between the semi-sealed cavity and the metallization layer.
Optionally, the cross-sectional shape of the semi-sealed cavity comprises a circle, a triangle, a square, or a hexagon.
The invention also provides a preparation method of the semiconductor multilayer chip packaging structure, which is characterized in that after the semiconductor packaging structure is prepared by adopting any one of the methods, at least one second metallization layer is bonded with the rewiring layer by taking the alignment mark on the metallization layer as a reference to form electrical connection, wherein the upper surface of the second metallization layer is provided with a second alignment mark; and continuously repeating the steps 2) to 6) in the steps to form the semiconductor multilayer chip packaging structure.
The invention also provides a semiconductor multilayer chip packaging structure, which is characterized by comprising at least one second metallization layer bonded on the semiconductor chip packaging structure, wherein the upper surface of the second metallization layer is provided with a contraposition mark; the second plastic package layer comprises a second metal column, a second semi-sealed cavity and a second plastic package layer, wherein the second metal column is positioned on the upper surface of the second metallization layer and is electrically connected with the second metallization layer, the second semi-sealed cavity is positioned at the periphery of the second alignment mark, and the second plastic package layer wraps the second metal column and the second semi-sealed cavity; and the second redistribution layer is formed on the upper surface of the second plastic packaging layer.
As described above, in the semiconductor chip package of the present invention, the semi-sealed cavity above the alignment mark is introduced, so that the alignment mark can be protected from being blocked by the molding compound, and the alignment mark is not exposed by other process means in the subsequent process, thereby providing a clear alignment mark for the subsequent exposure and lithography process and eliminating the problem of alignment failure.
Drawings
Fig. 1 shows a flow chart of a process for fabricating a semiconductor package structure.
FIG. 2 is a schematic diagram of providing a chip to be sealed with alignment marks
FIG. 3 is a schematic diagram illustrating a deposited metal pillar according to an embodiment.
Fig. 4 is a schematic view illustrating a mounting of a semi-sealed cavity according to a first embodiment.
FIG. 5 is a schematic view after molding according to the first embodiment.
FIG. 6 is a schematic view of the first embodiment after polishing.
Fig. 7 is a schematic diagram illustrating the formation of a redistribution layer according to the first embodiment.
Fig. 8 is a schematic view of a semiconductor multilayer chip package according to a second embodiment.
Description of the element reference numerals
10 chip to be sealed
11 metallization layer
12 plastic packaging layer
13 rewiring layer
101 substrate
102 alignment mark
111 dielectric layer
112 metal interconnection structure
121 plastic packaging material layer
122 semi-sealed cavity
123 metal column
131 dielectric layer
132 metal wire layer
21 second metallization layer
22 second plastic-sealed layer
23 second rewiring layer
211 second dielectric layer
212 second metal interconnect structure
221 second molding compound layer
222 second semi-sealed cavity
223 second metal column
231 second dielectric layer
232 second metal wire layer
202 second alignment mark
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
As shown in fig. 1 to 7, the present embodiment provides a semiconductor package structure and a method for manufacturing the same.
As shown in fig. 7, the semiconductor package structure provided in this embodiment includes: the semiconductor package comprises a substrate 101, a metallization layer 11 located on the substrate, an alignment mark 102 marked on the metallization layer, and a molding compound layer 12 located on the upper surface of the metallization layer, wherein the molding compound layer 12 comprises a metal pillar 123 located on the metallization layer and electrically connected with the metallization layer, a semi-sealed cavity 122 located at the periphery of the alignment mark 102, a molding compound layer 121 located on the metallization layer and covering the metal pillar and the semi-sealed cavity, and a redistribution layer 13 located on the molding compound layer 12, wherein the redistribution layer 13 comprises a dielectric 131 and a metal wire layer 132, and the redistribution layer 13 is electrically connected with the metallization layer 11 through the metal pillar 123.
Referring to fig. 1, the method for manufacturing a semiconductor package structure includes the following steps:
1) providing a chip to be sealed with an alignment mark, wherein the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, and the alignment mark is positioned on the upper surface of the chip to be sealed;
2) depositing a metal column which is formed on the upper surface of the chip to be sealed and electrically connected with the metallization layer;
3) mounting a semi-sealed cavity, wherein the semi-sealed cavity is a cavity with one surface opened and the other surface closed, and the opening of the semi-sealed cavity is buckled on the alignment mark;
4) plastic packaging, namely completely coating the metal column and the semi-sealed cavity with a plastic packaging material, and forming a plastic packaging layer on the metallization layer;
5) grinding, namely grinding the plastic packaging layer until the upper surface of the metal column and the alignment mark are exposed;
6) and forming a rewiring layer, wherein the rewiring layer comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
The technical solution of the present embodiment is further described in detail with reference to the accompanying drawings.
As shown in fig. 2, step 1) is performed to provide a chip to be sealed 10 with an alignment mark, where the chip to be sealed 10 includes: the semiconductor device comprises a substrate 101, a metallization layer 11 located above the substrate, wherein the metallization layer 11 comprises a dielectric layer 111 and a metal interconnection structure 112 located in the dielectric layer; the alignment mark 102 is located on the chip to be tested.
Optionally, the material of the metal interconnection structure includes any one of copper, aluminum, and titanium. The upper surface of the metal interconnection structure is flush with or higher than the upper surface of the dielectric layer.
Specifically, in this embodiment, metal copper is used as a material for the metal interconnection structure, and the upper surface of the metal interconnection structure is higher than the upper surface of the dielectric layer.
As shown in fig. 3, step 2) is performed to deposit metal pillars 123 to form electrical connections with the metallization layer 11.
Optionally, the preparation method of the metal pillar includes an electroplating process and a wire bonding process.
Optionally, the material of the metal pillar includes any one of copper, aluminum, and titanium.
As shown in fig. 4, step 3) is performed, and the semi-sealed cavity 122 is mounted, so that the semi-sealed cavity is buckled on the alignment mark 102. The semi-sealed cavity can ensure that the plastic package material can not be poured onto the alignment mark in the subsequent plastic package process, thereby providing a clear alignment point for the subsequent process.
The semi-sealed cavity is a cavity with one open side and the other closed side. The semi-sealed cavity can be of a three-dimensional structure such as a hemisphere, a column and the like. The cross section of the cavity can be square, hexagonal, circular, triangular or any other shape. The cross sectional area of the semi-sealed cavity is larger than the surface area of the alignment mark, so that the semi-sealed cavity can completely cover the alignment mark, and the alignment mark is prevented from being polluted by the plastic package material.
Optionally, the material of the semi-sealed cavity comprises glass, plastic, ceramic, metal.
In the step 3), the semi-sealed cavity is fixed above the alignment mark in a mounting mode. In this embodiment, the mounting manner of the semi-sealed cavity includes the following steps:
3-1) coating an adhesive on the opening surface of the semi-sealed cavity;
3-2) buckling the side coated with the adhesive on the alignment mark and adhering and fixing the side coated with the adhesive on the metalized layer.
Therefore, an adhesive layer (not shown) is also provided between the fixed semi-sealed cavity and the metallization layer.
As shown in fig. 5, step 4) is performed to perform plastic package, and a plastic package layer 12 is formed on the surface of the metallization layer. And (3) plastic packaging the structure by using a plastic packaging material, completely wrapping the metal column 123 and the semi-sealed cavity 122, and enabling the upper surface of a plastic packaging layer 12 formed after plastic packaging to be higher than the upper surfaces of the semi-sealed cavity 122 and the metal column 123. The molding compound layer 12 includes a metal pillar 123 located on the metallization layer and electrically connected to the metallization layer, a semi-sealed cavity 122 located at the periphery of the alignment mark 102, and a molding compound layer 121 located on the metallization layer and covering the metal pillar and the cavity wall.
Optionally, the material used for plastic package includes one of epoxy-based resin, liquid thermosetting epoxy resin, and plastic compound.
Optionally, the plastic package adopts a process including a compression molding process, a liquid seal molding process, a spin coating process, and a transfer molding process.
As shown in fig. 6, step 5) is performed to polish the molding layer 12 until the alignment mark 102 is exposed and the metal pillar 123 is exposed.
Optionally, the abrading means comprises chemical mechanical polishing.
As shown in fig. 7, step 6) is performed to form a redistribution layer 13 on the upper surface of the molding compound layer 12, wherein the redistribution layer 13 includes a dielectric layer 131 and a patterned metal wire layer 132 located in the dielectric layer 131. Specifically, the method for preparing the rewiring layer at least comprises the following steps:
and 6-1) depositing a dielectric layer, wherein the dielectric layer fills the hole surrounded by the cavity wall of the semi-sealed cavity and covers the plastic packaging layer and the upper surface of the metal column.
6-2) exposing the upper surface of the metal column by photoetching and etching,
6-3) forming a metal wire layer, and forming a patterned metal wire layer by photoetching and etching.
Optionally, the material of the metal wire layer includes any one of copper, aluminum, gold, nickel, and titanium. The metal wire layer can be formed by physical vapor deposition, chemical vapor deposition, magnetron sputtering or electroplating, chemical plating and other processes.
As described above, in the semiconductor package structure and the manufacturing method thereof provided by this embodiment, the semi-sealed cavity located above the alignment mark is introduced, so that the alignment mark can be protected from being blocked by the plastic encapsulant, and the alignment mark can be directly exposed without using other additional means in the subsequent process requiring alignment.
Example two
In this embodiment, on the basis of the semiconductor chip package structure provided in the first embodiment, at least one chip is bonded to the redistribution layer in the first embodiment, so as to form a semiconductor multilayer chip package structure having multiple chips.
As an example, as shown in fig. 8, the semiconductor two-layer chip package structure provided by the present embodiment includes: a second metallization layer 21 overlying the structure provided in the first embodiment, the second metallization layer 21 being electrically connected to the redistribution layer 13 in the first embodiment, the second metallization layer 21 having a second alignment mark 202 on an upper surface thereof; a second molding compound layer 22 on the upper surface of the second metallization layer 21, the second molding compound layer 22 including a second metal pillar 223 electrically connected to the second metallization layer on the second metallization layer, a second semi-sealed cavity 222 around the second alignment mark 202, a second molding compound layer 221 covering the second metal pillar and the second semi-sealed cavity on the second metallization layer, and a second redistribution layer 23 on the second molding compound layer 22, wherein the second redistribution layer 23 includes a second dielectric layer 231 and a second metal wire layer 232, and the second redistribution layer 23 is electrically connected to the second metallization layer 21 through the metal pillar 223. In this embodiment, the same reference numerals are used for the same parts as those in the first embodiment, and the description thereof is omitted.
The preparation method of the semiconductor two-layer chip packaging structure provided by the embodiment comprises the following steps: by repeating the steps 2) to 6) in the first embodiment on the basis of the semiconductor chip packaging method provided in the first embodiment, the semiconductor two-level chip packaging structure provided in this embodiment can be formed.
In another example, the method for manufacturing the semiconductor multilayer chip package structure further includes repeating steps 2) to 6) in the first step for multiple times to obtain the semiconductor multilayer chip package structure.
As described above, in the process of manufacturing the semiconductor multilayer chip package structure, the semi-sealed cavity capable of protecting the alignment mark from being contaminated by the molding compound is introduced for many times, so that the alignment mark can be directly exposed without other additional processes after plastic packaging, a visible alignment mark is provided for subsequent exposure, photoetching and other processes, and the problem of alignment failure is solved.
In summary, the semiconductor chip package structure and the method for manufacturing the same of the present invention include: 1) providing a chip to be sealed with an alignment mark, wherein the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, and the alignment mark is positioned on the upper surface of the metallization layer; 2) depositing a metal column which is formed on the upper surface of the chip to be sealed and electrically connected with the metallization layer; 3) fixing a semi-sealed cavity, wherein the semi-sealed cavity is a cavity with one surface opened and the other surfaces closed, and the opening of the semi-sealed cavity is buckled on the alignment mark; 4) plastic packaging, namely completely coating the metal column and the semi-sealed cavity with a plastic packaging material, and forming a plastic packaging layer on the metallization layer; 5) grinding, namely grinding the plastic packaging layer until the upper surface of the metal column and the alignment mark are exposed; 6) and forming a rewiring layer, wherein the rewiring layer comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column. The semi-sealed cavity capable of protecting the alignment mark from being polluted by the plastic package material is introduced once or for multiple times, so that the alignment mark can be directly exposed after plastic package without other additional processes, and accurate positioning is provided for subsequent processes.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (17)

1. A preparation method of a semiconductor packaging structure is characterized by comprising the following steps:
1) providing a chip to be sealed with an alignment mark, wherein the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, and the alignment mark is positioned on the upper surface of the metallization layer;
2) depositing a metal column which is formed on the upper surface of the chip to be sealed and electrically connected with the metallization layer;
3) fixing a semi-sealed cavity, wherein the semi-sealed cavity is a cavity with one surface opened and the other surfaces closed, and the opening of the semi-sealed cavity is buckled on the alignment mark;
4) plastic packaging, namely completely coating the metal column and the semi-sealed cavity with a plastic packaging material, and forming a plastic packaging layer on the metallization layer;
5) grinding, namely grinding the plastic packaging layer until the upper surface of the metal column and the alignment mark are exposed;
6) and forming a rewiring layer, wherein the rewiring layer comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
2. The method for manufacturing a semiconductor package structure according to claim 1, wherein the step 3) includes mounting the semi-sealed cavity.
3. The method for manufacturing a semiconductor package structure according to claim 2, wherein the mounting step at least comprises:
3-1) coating an adhesive on the opening surface of the semi-sealed cavity;
and 3-2) buckling the side coated with the adhesive on the alignment mark and fixedly adhering the side coated with the adhesive to the metalized layer.
4. The method of claim 1, wherein the metallization layer comprises a dielectric layer and a metal interconnection structure formed in the dielectric layer, and the metal interconnection structure is made of any one of copper, aluminum and titanium.
5. The method for manufacturing a semiconductor package structure according to claim 4, wherein an upper surface of the metal interconnection structure is flush with or higher than an upper surface of the dielectric layer.
6. The method of claim 1, wherein the metal pillar comprises a wire bonding process and an electroplating process.
7. The method of claim 1, wherein the metal pillar comprises any one of copper, aluminum and titanium.
8. The method of claim 1, wherein the material of the semi-sealed cavity comprises glass, plastic, ceramic, or metal.
9. The method of claim 1, wherein the molding compound comprises one of an epoxy-based resin, a liquid thermosetting epoxy resin, and a plastic compound.
10. The method of manufacturing a semiconductor package structure according to claim 1, wherein the plastic encapsulation comprises a compression molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process, or a spin coating process.
11. The method of claim 1, wherein the grinding comprises chemical mechanical polishing.
12. The method for manufacturing a semiconductor package structure according to claim 1, wherein the step 6) at least comprises the following steps:
6-1) forming a dielectric layer on the upper surface of the plastic packaging layer, wherein the dielectric layer fills the semi-sealed cavity and covers the plastic packaging layer;
6-2) exposing the upper surface of the metal column through a photoetching process;
6-3) forming a metal wire layer on the upper surface of the dielectric layer, wherein the metal wire layer is electrically connected with the metal column.
13. A semiconductor package, comprising:
the chip to be sealed comprises a substrate and a metallization layer positioned on the substrate, wherein the upper surface of the metallization layer is provided with a contraposition mark;
the plastic packaging layer is formed on the upper surface of the chip to be packaged and comprises a metal column, a semi-sealed cavity and a plastic packaging material layer, wherein the metal column is positioned on the upper surface of the chip to be packaged and electrically connected with the metallization layer, the semi-sealed cavity is positioned on the periphery of the alignment mark, and the plastic packaging material layer wraps the metal column and the semi-sealed cavity;
the rewiring layer is positioned on the upper surface of the plastic packaging layer and comprises a dielectric layer and a metal wire layer positioned on the dielectric layer, wherein the dielectric layer exposes the upper surface of the metal column, and the metal wire layer is electrically connected with the metal column.
14. The semiconductor package of claim 13, wherein an adhesive layer is further disposed between the semi-sealed cavity and the metallization layer.
15. The semiconductor package structure of claim 13, wherein a cross-sectional shape of the semi-sealed cavity comprises a circle, a triangle, a square, or a hexagon.
16. A method for preparing a semiconductor multilayer chip packaging structure is characterized in that the method comprises the steps of bonding at least one second metallization layer and a rewiring layer by taking a counterpoint mark on the metallization layer as a reference to form electrical connection after the semiconductor packaging structure is prepared by the method of claim 1, wherein the upper surface of the second metallization layer is provided with a second counterpoint mark; and continuously repeating the steps 2) to 6) in the claim 1 to form the semiconductor multilayer chip packaging structure.
17. A semiconductor multilayer chip package structure, comprising at least a second metallization layer bonded on the semiconductor package structure of claim 13, wherein the second metallization layer has alignment marks on its upper surface; the second plastic package layer comprises a second metal column, a second semi-sealed cavity and a second plastic package layer, wherein the second metal column is positioned on the upper surface of the second metallization layer and is electrically connected with the second metallization layer, the second semi-sealed cavity is positioned at the periphery of the second alignment mark, and the second plastic package layer wraps the second metal column and the second semi-sealed cavity; and the second redistribution layer is formed on the upper surface of the second plastic packaging layer.
CN201910390440.5A 2019-05-10 2019-05-10 Semiconductor packaging structure and preparation method thereof Pending CN111916362A (en)

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CN112466803A (en) * 2021-02-04 2021-03-09 中芯集成电路制造(绍兴)有限公司 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112466803A (en) * 2021-02-04 2021-03-09 中芯集成电路制造(绍兴)有限公司 Method for manufacturing semiconductor device
CN112466803B (en) * 2021-02-04 2021-06-25 中芯集成电路制造(绍兴)有限公司 Method for manufacturing semiconductor device

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