CN209822673U - High-voltage LED chip - Google Patents
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- CN209822673U CN209822673U CN201920747346.6U CN201920747346U CN209822673U CN 209822673 U CN209822673 U CN 209822673U CN 201920747346 U CN201920747346 U CN 201920747346U CN 209822673 U CN209822673 U CN 209822673U
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Abstract
The utility model discloses a high-voltage LED chip, which comprises a substrate, a first light-emitting structure and a second light-emitting structure which are arranged on the substrate, and a cutting channel which is arranged between the first light-emitting structure and the second light-emitting structure; and a passivation layer disposed on the first light emitting structure, the second light emitting structure and the scribe line; the first light-emitting structure comprises a first semiconductor layer, a first active layer, a second semiconductor layer, a first electrode arranged on the second semiconductor layer and a second electrode arranged on the first semiconductor layer; the second light-emitting structure comprises a third semiconductor layer, a second active layer, a fourth semiconductor layer, a third electrode arranged on the third semiconductor layer and a fourth electrode arranged on the fourth semiconductor layer; the third electrode and the fourth electrode are in conductive connection through a metal film arranged on the cutting path. The utility model discloses in through special structural design, effectively reduced the photoetching operation number of times of this kind of LED chip, manufacturing cost has descended 20-40%.
Description
Technical Field
The utility model relates to a light emitting diode technical field especially relates to a high pressure LED chip.
Background
The high-voltage LED chip is formed by serially connecting a plurality of chips in an LED chip preparation section to emit light, the number of times of welding wires of a downstream packaging factory is reduced, the production efficiency is improved, the cost is saved, meanwhile, the design requirement on a heat dissipation system can be greatly reduced by the high-voltage LED chip, and the heat dissipation technical obstacle of an LED lighting market is overcome.
At present, the mainstream high-voltage LED chip manufacturers in China adopt 6 photoetching processes, namely Mesa photoetching, deep etching photoetching, current barrier layer photoetching, transparent conducting layer photoetching, electrode photoetching and passivation layer photoetching, wherein a metal spans the bridging part of adjacent chips and uses a current barrier layer as an insulating layer for isolating the adjacent chips, so that the current barrier layer photoetching must be carried out between the Mesa photoetching and the transparent conducting layer photoetching, namely the two steps of photoetching must be carried out step by step, and in order to keep the redundancy, a certain light-emitting area must be sacrificed, thereby losing the brightness of the chips, increasing the use voltage and heat of the chips and reducing the service life of the chips to a certain extent.
In order to simplify the production process of the high-voltage LED chip, chinese patent application CN108807607A proposes a new production method, which adopts five photo-etching processes, such as current blocking layer photo-etching, transparent conducting layer photo-etching, Mesa etching, deep etching photo-etching, passivation layer photo-etching and electrode photo-etching, to produce the high-voltage LED chip, thereby saving the production cost. However, the process flow is still long, the production is complex and the production cost is high.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that a high pressure LED chip is provided, its cost of manufacture is low.
In order to solve the above technical problem, the present invention provides a high voltage LED chip, which includes a substrate, a first light emitting structure and a second light emitting structure disposed on the substrate, and a cutting path between the first light emitting structure and the second light emitting structure; and a passivation layer disposed on the first light emitting structure, the second light emitting structure and the scribe line;
the first light-emitting structure comprises a first semiconductor layer, a first active layer, a second semiconductor layer, a first electrode arranged on the second semiconductor layer and a second electrode arranged on the first semiconductor layer;
the second light emitting structure comprises a third semiconductor layer, a second active layer, a fourth semiconductor layer, a third electrode arranged on the third semiconductor layer and a fourth electrode arranged on the fourth semiconductor layer;
and the third electrode and the fourth electrode are in conductive connection through a metal film arranged on the cutting channel.
As an improvement of the technical scheme, the side wall of the cutting channel has an inclined angle.
As an improvement of the technical scheme, the inclination angle is less than or equal to 60 degrees.
As an improvement of the technical scheme, the width of the cutting channel is 10-20 μm.
As an improvement of the technical scheme, the width of the cutting channel is 13-18 μm.
As an improvement of the above technical solution, the first electrode, the second electrode, the third electrode, and the fourth electrode sequentially include a first Cr layer, an Al layer, a second Cr layer, a first Ti layer, a first Au layer, a third Cr layer, a second Ti layer, and a second Au layer.
As an improvement of the above technical solution, a transparent conductive layer is further disposed between the second semiconductor layer and the transparent conductive layer, and between the fourth semiconductor layer and the transparent conductive layer.
As an improvement of the above technical solution, a saw-toothed epitaxial buffer layer is further disposed between the first semiconductor layer and the substrate, and between the second semiconductor layer and the substrate.
Implement the utility model discloses, following beneficial effect has:
1. the utility model discloses only have the one deck passivation layer, it can effectively shorten manufacturing cycle, saves the cost.
2. The cutting tool of the utility model has an inclination angle, so that the electrode connection is more stable and the wire is not easy to break; the utility model discloses connect safe simple between each led chip, the reliability is high.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a high voltage LED chip according to the present invention;
FIG. 2 is a schematic structural diagram of an LED chip after an epitaxial layer and a transparent conductive layer are formed;
FIG. 3 is a schematic diagram of an LED chip structure after a first photolithography process;
FIG. 4 is a schematic diagram of the structure of the LED chip after the second photolithography process;
FIG. 5 is a schematic diagram of the structure of the LED chip after deposition of the passivation layer;
FIG. 6 is a schematic structural diagram of an LED chip after a third photolithography process;
fig. 7 is a schematic diagram of an elegant LED chip structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings. Only this statement, the utility model discloses the upper and lower, left and right, preceding, back, inside and outside etc. position words that appear or will appear in the text only use the utility model discloses an attached drawing is the benchmark, and it is not right the utility model discloses a concrete restriction.
The traditional high-voltage LED chip has long production period, more times of required photoetching process and high production cost. Therefore, the utility model discloses a preparation method of high pressure LED chip, refer to fig. 1, it includes following step:
s1: sequentially forming an epitaxial layer and a transparent conducting layer on a substrate;
specifically, an N-type gallium nitride layer 21, an MQW quantum well layer 22 and a P-type silicon nitride layer 203 are sequentially formed on a substrate by adopting a Metal Organic Chemical Vapor Deposition (MOCVD) method to obtain an epitaxial layer 2; and then evaporating a transparent conductive layer 3 on the surface of the epitaxial layer 2 by adopting an electron beam evaporation method.
Referring to fig. 2, fig. 2 is a schematic structural diagram of the LED chip after the step S1; wherein, 1 material of substrate can be sapphire, carborundum or silicon, also can be other semiconductor materials, preferred, the utility model discloses choose the sapphire substrate for use.
The transparent conductive layer 3 is made of indium tin oxide; the thickness of the transparent conducting layer 3 is 50-200nm, and when the thickness of the transparent conducting layer 3 is less than 50nm, the adhesion between the transparent conducting layer and the electrode can be reduced; when the thickness is larger than 200nm, the process difficulty is increased, and the light emitting efficiency of the LED chip is also reduced. Preferably, the thickness of the transparent conductive layer 3 is 80 to 100 nm.
Furthermore, an epitaxial buffer layer is arranged between the substrate and the epitaxial layer.
S2: photoetching and etching the transparent conducting layer and the epitaxial layer to form a light-emitting structure;
specifically, step S2 includes:
s21: forming a first photoresist on the surface of the transparent conducting layer;
the first photoresist can be a positive photoresist and can also be a negative photoresist;
s22: photoetching to form a first pattern photoetching area;
specifically, the pattern on the original negative film is transferred to a photosensitive bottom plate through exposure and the light source, and then the photoresist on the exposed area or the unexposed area is removed.
S23: etching the transparent conductive layer to form a first light-emitting structure exposed area and a second light-emitting structure exposed area;
wherein, the transparent conducting layer can be etched by adopting a dry etching or wet etching mode; preferably, the transparent conductive layer is etched by wet etching; specifically, the transparent conducting layer is etched by adopting a mixed solution of ferric chloride and hydrochloric acid, the etching time is 500-220 s, preferably 150-500 s, and the etching time not only can fully etch the transparent conducting layer, but also can ensure that the whole thickness of the ITO layer is not greatly reduced and the current expansibility of the chip is not influenced.
S24: etching the exposed areas of the first light-emitting structure and the second light-emitting structure; forming a first hole and a second hole;
wherein, the transparent conducting layer can be etched by adopting a dry etching or wet etching mode; preferably, dry etching is adopted to etch the transparent conductive layer; the dry etching can form good control on the critical dimension and ensure the uniformity.
S25: and removing the first photoresist to form a first light-emitting structure and a second light-emitting structure.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an LED chip after a first photolithography process; wherein the first light emitting structure 4 includes a first semiconductor layer 41, a first active layer 42, and a second semiconductor layer 43; the second light emitting structure 5 includes a third semiconductor layer 51, a second active layer 52, and a fourth semiconductor layer 53; the first hole 44 penetrates through the second semiconductor layer 43 and the first active layer 42 to reach the first semiconductor layer 41; the second hole 54 penetrates the fourth semiconductor layer 53 and the second active layer 52 to reach the third semiconductor layer 51.
The utility model combines the photoetching of the transparent conducting layer and the photoetching of Mesa into one photoetching and two etchings; the manufacturing period is shortened, and the cost is reduced; meanwhile, the light emitting area of the high-voltage LED chip can be increased.
S3: photoetching and etching the substrate to form a cutting path;
specifically, step S3 includes:
s31: forming a second photoresist on the surface of the substrate;
the second photoresist can be a positive photoresist and can also be a negative photoresist.
S32: photoetching to form a second pattern photoetching area;
s33: performing through etching to the surface of the substrate, and forming a cutting channel between the first light-emitting structure and the second light-emitting structure;
wherein, the etching can be carried out by adopting a dry etching or wet etching mode; preferably, dry etching is adopted, and the dry etching can well control the critical dimension and ensure the uniformity.
S34: and removing the second photoresist.
Referring to fig. 4, fig. 4 is a schematic structural diagram of the LED chip after the second photolithography process; in order to improve the connection stability between the high-voltage LED chips, the side wall of the cutting channel 6 has a certain inclination angle; the cutting channel 6 with the structure can also improve the side light-emitting efficiency of the light-emitting structure and improve the light-emitting efficiency of the chip. Preferably, the inclination angle is less than or equal to 60 degrees, and when the inclination angle is too large, the metal film is difficult to form and is easy to break in the later electrode evaporation process. Preferably, the inclination angle is 30-55 degrees, which can ensure that the electrode is not broken during evaporation, and simultaneously, the light-emitting efficiency of the chip is improved to a higher extent.
Further, in order to guarantee the connection stability between the LED chips, the width of the cutting street is set to be 10-20 μm; the cutting line is too narrow, so that the inclination angle is too large, and the wire is easy to break; the cutting channel is too wide, so that the light-emitting area is reduced, and the light-emitting efficiency of the chip is reduced. Preferably, the width of the cutting channel is set to be 13-18 μm; and more preferably 16 μm, to ensure high light-emitting efficiency of the LED chip and secure connection of the LED chip.
S4: forming a passivation layer on the surface of the substrate;
specifically, Metal Organic Chemical Vapor Deposition (MOCVD) is used
The passivation layer is deposited by metal organic chemical vapor deposition, and the material of the passivation layer is silicon dioxide or silicon nitride, but is not limited thereto, and preferably, silicon dioxide is used for short term. Referring to fig. 5, fig. 5 is a schematic structural diagram of an LED chip after depositing a passivation layer 7, wherein the thickness of the passivation layer 7 is 50-500nm, preferably 80-200 nm.
S5: photoetching and etching the passivation layer to form an electrode area;
specifically, S5 includes:
s51: forming a third photoresist on the surface of the passivation layer;
s52: photoetching to form a third pattern photoetching area;
s53: etching the passivation layer to form a first electrode area, a second electrode area, a third electrode area and a fourth electrode area;
s54; removing the third photoresist;
fig. 6 is a schematic structural diagram of the LED chip after the third photolithography process. Referring to fig. 6, after the third photolithography process, a passivation layer 7 covers the sidewalls and bottom of the scribe line 6, and the portions of the semiconductor layers except for the electrode regions. The passivation layer can strengthen electrode bridging and improve the efficiency of the LED chip. The first electrode region 45 is located at the second semiconductor layer 43, the second electrode region 46 is located at the first semiconductor layer 41, the third electrode region 55 is located at the fourth semiconductor layer 53, and the fourth electrode region 56 is located at the third semiconductor layer 53.
S6: forming an electrode in the electrode area through photoetching and evaporation;
specifically, step S6 includes:
(6.1) forming a fourth photoresist on the surface of the substrate;
(6.2) forming a fourth pattern photoetching area by photoetching;
(6.3) evaporating the first electrode area, the second electrode area, the third electrode area and the fourth electrode area to form a first electrode, a second electrode, a third electrode and a fourth electrode;
wherein, the evaporation of the electrode is carried out by adopting an electron beam evaporation, thermal evaporation or magnetron sputtering process. Preferably, a first electrode 47 is formed by depositing a metal in the first electrode region 45 and a second electrode 48 is formed by depositing a metal in the second electrode region 46 by electron beam evaporation; and depositing metal on the third electrode area 55 to form a third electrode 57, and depositing metal on the fourth electrode area 56 to form a fourth electrode 58.
Meanwhile, a metal film 61 is deposited on the scribe line 6, so that the second electrode 48 is electrically connected to the third electrode 57.
And (6.4) tearing gold and removing the fourth photoresist to obtain the high-voltage LED chip.
It should be noted that, the conventional high-voltage LED chip generally adopts at least two passivation processes; firstly forming a current barrier layer on the epitaxial layer, and then carrying out primary passivation after forming an electrode; this passivation process adds at least two photolithography processes and is costly to manufacture. The invention reduces the passivation process into one step by improving the process, thereby reducing the manufacturing cost. However, in order to eliminate the adverse effect of reducing the number of times of passivation, the electrode was designed.
Specifically, in the present invention, the first electrode 47, the second electrode 48, the third electrode 57, or the fourth electrode 58 sequentially includes a first Cr layer, an Al layer, a second Cr layer, a first Ti layer, a first Au layer, a third Cr layer, a second Ti layer, and a second Au layer. The LED chip adopting the electrode with the structure still has good power under the condition that only one passivation layer is arranged. The structure of each electrode in the present invention is not limited thereto, and a part of the metal layer may be reduced or increased. In the present invention, the first electrode, the second electrode, the third electrode, and the fourth electrode may have different structures.
Among the metal elements adopted by the electrode, Cr can form good ohmic contact with a semiconductor layer and has good adhesive force, so that an electrode alloy layer is prevented from falling off; the Pt and the Au have the advantages of good conductivity, stability, good ductility and the like, and the Al layer has good reflection performance, so that the overall performance of the LED chip is improved; ti may prevent Al migration in the Al layer.
Further, in order to improve the efficiency of the LED chip, the thickness of the first Cr layer is 1-10nm, the thickness of the Al layer is 30-80nm, the thickness of the second Cr layer is 10-100nm, the thickness of the first Ti layer is 50-100nm, the thickness of the first Au layer is 10-30nm, the thickness of the third Cr layer is 10-50nm, the thickness of the third Ti layer is 10-30nm, and the thickness of the second Au layer is 20-50 nm. By adopting the electrode with the thickness and the structure, the second electrode and the third electrode can be stably connected, and the cost is low; and each electrode can have good performance under the condition of only adopting one-time passivation.
Correspondingly, referring to fig. 7, the utility model also discloses a high-voltage LED chip, which comprises a substrate 1, a first light-emitting structure 4 and a second light-emitting structure 5 arranged on the substrate, and a cutting channel 6 arranged between the first light-emitting structure and the second light-emitting structure; and a passivation layer 7 disposed on the first light emitting structure 4, the second light emitting structure 5 and the scribe line 6;
the first light emitting structure 4 includes a first semiconductor layer 41, a first active layer 42, a second semiconductor layer 43, a first electrode 47 disposed on the second semiconductor layer 43, and a second electrode 48 disposed on the first semiconductor layer 41;
the second light emitting structure 5 includes a third semiconductor layer 51, a second active layer 52, a fourth semiconductor layer 53, a third electrode 57 disposed on the third semiconductor layer 51, and a fourth electrode 58 disposed on the fourth semiconductor layer;
the second electrode 48 and the third electrode 57 are electrically connected through a metal film 61 provided in the scribe line.
Wherein the scribe line 6 penetrates through the first semiconductor layer 41 and the third semiconductor layer 51 and extends to the substrate surface.
In order to improve the connection stability between the high-voltage LED chips, the side wall of the cutting channel 6 has a certain inclination angle; the cutting channel 6 with the structure can also improve the side light-emitting efficiency of the light-emitting structure and improve the light-emitting efficiency of the chip. Preferably, the inclination angle is less than or equal to 60 degrees, and when the inclination angle is too large, the metal film is difficult to form and is easy to break in the later electrode evaporation process. Preferably, the inclination angle is 30-55 degrees, which can ensure that the electrode is not broken during evaporation, and simultaneously, the light-emitting efficiency of the chip is improved to a higher extent.
It should be noted that, in this embodiment, only one passivation is performed on the scribe line 6 and the surface of each semiconductor layer, so as to form a passivation layer, and the high voltage LED chip in this embodiment does not include other passivation layers except for this passivation layer, such as a current blocking layer, an insulating layer, and the like.
Further, in order to guarantee the connection stability between the LED chips, the width of the cutting street is set to be 10-20 μm; the cutting line is too narrow, so that the inclination angle is too large, and the wire is easy to break; the cutting channel is too wide, so that the light-emitting area is reduced, and the light-emitting efficiency of the chip is reduced. Preferably, the width of the cutting channel is set to be 13-18 μm; and more preferably 16 μm, to ensure high light-emitting efficiency of the LED chip and secure connection of the LED chip.
In order to ensure the efficiency of the LED chip, the first electrode 47, the second electrode 48, the third electrode 57 or the fourth electrode 58 sequentially include a first Cr layer, an Al layer, a second Cr layer, a first Ti layer, a first Au layer, a third Cr layer, a second Ti layer and a second Au layer. The LED chip adopting the electrode with the structure still has good power under the condition that only one passivation layer is arranged. The structure of each electrode in the present invention is not limited thereto, and a part of the metal layer may be reduced or increased. In the present invention, the first electrode, the second electrode, the third electrode, and the fourth electrode may have different structures.
Among the metal elements adopted by the electrode, Cr can form good ohmic contact with a semiconductor layer and has good adhesive force, so that an electrode alloy layer is prevented from falling off; the Pt and the Au have the advantages of good conductivity, stability, good ductility and the like, and the Al layer has good reflection performance, so that the overall performance of the LED chip is improved; ti may prevent Al migration in the Al layer.
Further, in order to improve the efficiency of the LED chip, the thickness of the first Cr layer is 1-10nm, the thickness of the Al layer is 30-80nm, the thickness of the second Cr layer is 10-100nm, the thickness of the first Ti layer is 50-100nm, the thickness of the first Au layer is 10-30nm, the thickness of the third Cr layer is 10-50nm, the thickness of the third Ti layer is 10-30nm, and the thickness of the second Au layer is 20-50 nm. By adopting the electrode with the thickness and the structure, the second electrode and the third electrode can be stably connected, and the cost is low; and each electrode can have good performance under the condition that a passivation layer is arranged.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered as the protection scope of the present invention.
Claims (8)
1. A high-voltage LED chip is characterized by comprising a substrate, a first light-emitting structure and a second light-emitting structure which are arranged on the substrate, and a cutting channel which is positioned between the first light-emitting structure and the second light-emitting structure; and a passivation layer disposed on the first light emitting structure, the second light emitting structure and the scribe line;
the first light-emitting structure comprises a first semiconductor layer, a first active layer, a second semiconductor layer, a first electrode arranged on the second semiconductor layer and a second electrode arranged on the first semiconductor layer;
the second light emitting structure comprises a third semiconductor layer, a second active layer, a fourth semiconductor layer, a third electrode arranged on the third semiconductor layer and a fourth electrode arranged on the fourth semiconductor layer;
and the third electrode and the fourth electrode are in conductive connection through a metal film arranged on the cutting channel.
2. The high voltage LED chip of claim 1, wherein the side walls of the dicing street have an oblique angle.
3. The high voltage LED chip of claim 2, wherein said tilt angle is less than or equal to 60 degrees.
4. The high voltage LED chip of claim 2, wherein the width of the scribe line is 10-20 μ ι η.
5. The high voltage LED chip of claim 4, wherein the width of the scribe line is 13-18 μm.
6. The high voltage LED chip of claim 1, wherein the first, second, third or fourth electrode comprises in sequence a first Cr layer, an Al layer, a second Cr layer, a first Ti layer, a first Au layer, a third Cr layer, a second Ti layer and a second Au layer.
7. The high voltage LED chip of claim 1, wherein a transparent conductive layer is further disposed between the second semiconductor layer and the transparent conductive layer and between the fourth semiconductor layer and the transparent conductive layer.
8. The high voltage LED chip of claim 1, wherein a saw-toothed epitaxial buffer layer is disposed between said first semiconductor layer and said substrate, and between said second semiconductor layer and said substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201920308692 | 2019-03-11 | ||
| CN2019203086924 | 2019-03-11 |
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| CN209822673U true CN209822673U (en) | 2019-12-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110190158A (en) * | 2019-03-11 | 2019-08-30 | 佛山市国星半导体技术有限公司 | A kind of high voltage LED chip and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110190158A (en) * | 2019-03-11 | 2019-08-30 | 佛山市国星半导体技术有限公司 | A kind of high voltage LED chip and preparation method thereof |
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