CN209804639U - 3D chip packaging structure - Google Patents
3D chip packaging structure Download PDFInfo
- Publication number
- CN209804639U CN209804639U CN201920852233.2U CN201920852233U CN209804639U CN 209804639 U CN209804639 U CN 209804639U CN 201920852233 U CN201920852233 U CN 201920852233U CN 209804639 U CN209804639 U CN 209804639U
- Authority
- CN
- China
- Prior art keywords
- layer
- connection structure
- electrical connection
- chip
- plastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
the utility model provides a 3D chip package structure, 3D chip package structure includes: rewiring layers; a chip flip-bonded to an upper surface of the rewiring layer; a first electrical connection structure on an upper surface of the rewiring layer; the first plastic packaging layer is positioned on the upper surface of the rewiring layer and is used for plastically packaging the chip and the first electric connection structure; the second electrical connection structure is positioned on the upper surface of the first plastic packaging layer; the second plastic packaging layer is positioned on the upper surface of the first plastic packaging layer; the third electrical connection structure is positioned on the upper surface of the second plastic packaging layer; the third plastic packaging layer is positioned on the upper surface of the second plastic packaging layer and plastically packages the third electric connection structure; the top metal wire layer is positioned on the upper surface of the third plastic packaging layer; and the solder ball bump is positioned on the lower surface of the rewiring layer. The utility model discloses an among the 3D chip package structure, the chip has realized the 3D encapsulation, and the cost is lower, the encapsulation integrated level is high, can satisfy miniaturized development trend's needs.
Description
Technical Field
the utility model relates to a semiconductor package technical field especially relates to a 3D chip package structure.
background
Lower cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. In the future, integrated circuit packages will increase the integration density of various electronic components by continually reducing the minimum feature size. Currently, advanced packaging methods include: wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Packaging (Fan-Out Wafer Level Packaging, FOWLP), flip Chip (FlipChip), stack on Packaging (POP), and the like.
However, the conventional packaging method and the packaging structure obtained by the packaging method have the problems of high cost, low integration level and incapability of meeting the requirement of miniaturization development trend.
SUMMERY OF THE UTILITY MODEL
In view of the above shortcomings in the prior art, an object of the present invention is to provide a 3D chip package structure for solving the problems of the package method and the package structure in the prior art, such as high cost, low integration level, and failure to meet the requirement of miniaturization development trend.
In order to achieve the above objects and other related objects, the utility model provides a 3D chip packaging structure, 3D chip packaging structure includes:
rewiring layers;
A chip flip-chip bonded to an upper surface of the rewiring layer and electrically connected to the rewiring layer;
A first electrical connection structure on an upper surface of the rewiring layer and electrically connected to the rewiring layer;
the first plastic packaging layer is positioned on the upper surface of the rewiring layer and is used for plastically packaging the chip and the first electric connection structure;
The second electrical connection structure is positioned on the upper surface of the first plastic package layer and is electrically connected with the first electrical connection structure;
the second plastic packaging layer is positioned on the upper surface of the first plastic packaging layer and plastically packages the second electric connection structure;
The third electrical connection structure is positioned on the upper surface of the second plastic package layer and is electrically connected with the second electrical connection structure;
the third plastic packaging layer is positioned on the upper surface of the second plastic packaging layer and plastically packages the third electric connection structure;
the top metal wire layer is positioned on the upper surface of the third plastic packaging layer and is electrically connected with the third electric connection structure;
and the solder ball bump is positioned on the lower surface of the rewiring layer and is electrically connected with the rewiring layer.
Optionally, the rewiring layer includes:
A wiring dielectric layer;
The metal laminated structure is positioned in the wiring dielectric layer and comprises a plurality of metal wire layers which are arranged at intervals and metal plugs, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.
Optionally, the rerouting layer further comprises:
The seed layer is positioned on the lower surface of the wiring dielectric layer and is electrically connected with the metal laminated structure;
The plastic packaging material layer is positioned on the lower surface of the seed layer; the wiring dielectric layer wraps the plastic packaging material layer and the seed layer;
and the bottom dielectric layer is positioned on the lower surface of the wiring dielectric layer.
Optionally, the first electrical connection structure, the second electrical connection structure, and the third electrical connection structure each include a bonding wire or a conductive pillar.
Optionally, the 3D chip packaging structure further includes:
A first interlayer dielectric layer located between the first plastic package layer and the second plastic package layer;
a first redistribution metal layer within the first interlayer dielectric layer and electrically connected to the first and second electrical connection structures;
A second interlayer dielectric layer located between the second plastic package layer and the third plastic package layer;
And the second rewiring metal layer is positioned in the second interlayer dielectric layer and is electrically connected with the second electric connection structure and the third electric connection structure.
Optionally, an orthographic projection of the second plastic package layer on the upper surface of the first plastic package layer is located in the upper surface of the first plastic package layer; and the orthographic projection of the third plastic packaging layer on the upper surface of the second plastic packaging layer is positioned in the upper surface of the second plastic packaging layer.
Optionally, the thickness of the second plastic package layer is smaller than that of the first plastic package layer and larger than that of the third plastic package layer.
In order to achieve the above and other related objects, the present invention also provides a method for manufacturing a 3D chip package structure, the method for manufacturing a 3D chip package structure includes the following steps:
Providing a substrate, and forming a sacrificial layer on the upper surface of the substrate;
Forming a rewiring layer on the upper surface of the sacrificial layer;
Providing a chip, and bonding the chip on the upper surface of the rewiring layer in a flip-chip manner, wherein the chip is electrically connected with the rewiring layer;
forming a first electrical connection structure and a first plastic packaging layer on the upper surface of the rewiring layer; the first electric connection structure is positioned in the first plastic package layer and is electrically connected with the rewiring layer; the first plastic packaging layer is used for plastically packaging the chip and the first electric connection structure;
Forming a second electrical connection structure and a second plastic packaging layer on the upper surface of the first plastic packaging layer; the second electric connection structure is positioned in the second plastic package layer and is electrically connected with the first electric connection structure;
Forming a third electrical connection structure and a third plastic packaging layer on the upper surface of the second plastic packaging layer; the third electric connection structure is positioned in the third plastic package layer and is electrically connected with the second electric connection structure;
Forming a top metal wire layer on the upper surface of the third plastic packaging layer, wherein the top metal wire layer is electrically connected with the third electrical connection structure;
removing the substrate and the sacrificial layer;
And forming a solder ball bump below the redistribution layer, wherein the solder ball bump is electrically connected with the redistribution layer.
Optionally, the step of forming the redistribution layer on the upper surface of the sacrificial layer includes:
forming a bottom dielectric layer on the upper surface of the sacrificial layer;
forming a plastic packaging material layer on the upper surface of the bottom dielectric layer;
forming a seed layer on the upper surface of the plastic packaging material layer;
carrying out graphical processing on the seed layer and the plastic packaging material layer;
forming a wiring dielectric layer and a metal laminated structure on the upper surface of the bottom dielectric layer, wherein the metal laminated structure is positioned in the wiring dielectric layer and is electrically connected with the seed layer; the metal laminated structure comprises a plurality of metal wire layers arranged at intervals and metal plugs, wherein the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.
Optionally, before forming the second electrical connection structure and the second plastic package layer on the upper surface of the first plastic package layer, a step of forming a first interlayer dielectric layer and a first redistribution metal layer on the upper surface of the first plastic package layer, where the first redistribution metal layer is located in the first interlayer dielectric layer and electrically connected to the first electrical connection structure; the second plastic package layer is formed on the upper surface of the first interlayer dielectric layer, and the second electric connection structure is formed on the upper surface of the first rewiring metal layer;
before forming the third electrical connection structure and the third plastic package layer on the upper surface of the second plastic package layer, a step of forming a second interlayer dielectric layer and a second rewiring metal layer on the upper surface of the second plastic package layer, wherein the second rewiring metal layer is located in the second interlayer dielectric layer and is electrically connected with the second electrical connection structure; the third plastic package layer is formed on the upper surface of the second interlayer dielectric layer, and the third electric connection structure is formed on the upper surface of the second rewiring metal layer.
Optionally, an orthographic projection of the second plastic package layer on the upper surface of the first plastic package layer is located in the upper surface of the first plastic package layer; and the orthographic projection of the third plastic packaging layer on the upper surface of the second plastic packaging layer is positioned in the upper surface of the second plastic packaging layer.
Optionally, the thickness of the second plastic package layer is smaller than that of the first plastic package layer and larger than that of the third plastic package layer.
As described above, the utility model discloses a 3D chip package structure has following beneficial effect: the utility model discloses an among the 3D chip package structure, the chip has realized the 3D encapsulation, and the cost is lower, the encapsulation integrated level is high, can satisfy miniaturized development trend's needs.
Drawings
fig. 1 is a flowchart illustrating a method for manufacturing a 3D chip package structure according to a first embodiment of the present invention.
Fig. 2 to 18 are schematic cross-sectional structural diagrams illustrating structures obtained in various steps of a method for manufacturing a 3D chip package structure according to a first embodiment of the present invention; fig. 18 is a schematic cross-sectional view of a 3D chip package structure provided in the second embodiment of the present invention.
description of the element reference numerals
10 base
11 sacrificial layer
12 rewiring layer
121 bottom dielectric layer
122 plastic packaging material layer
123 seed layer
124 wiring dielectric layer
125 metal laminated structure
13 chip
14 first electric connection structure
15 first plastic-sealed layer
16 first interlayer dielectric layer
17 first rewiring metal layer
18 second electrical connection structure
19 second plastic packaging layer
20 second interlayer dielectric layer
21 second redistribution metal layer
22 third electrical connection structure
23 third plastic packaging layer
24 top metal wire layer
25 solder ball bump
26 opening
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to fig. 1 to 18. It should be noted that the drawings provided in the present embodiment are only schematic and illustrative of the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
Example one
Referring to fig. 1, the present invention provides a method for manufacturing a 3D chip package structure, wherein the method for manufacturing the 3D chip package structure includes the following steps:
1) Providing a substrate, and forming a sacrificial layer on the upper surface of the substrate;
2) forming a rewiring layer on the upper surface of the sacrificial layer;
3) Providing a chip, and bonding the chip on the upper surface of the rewiring layer in a flip-chip manner, wherein the chip is electrically connected with the rewiring layer;
4) forming a first electrical connection structure and a first plastic packaging layer on the upper surface of the rewiring layer; the first electric connection structure is positioned in the first plastic package layer and is electrically connected with the rewiring layer; the first plastic packaging layer is used for plastically packaging the chip and the first electric connection structure;
5) Forming a second electrical connection structure and a second plastic packaging layer on the upper surface of the first plastic packaging layer; the second electric connection structure is positioned in the second plastic package layer and is electrically connected with the first electric connection structure;
6) Forming a third electrical connection structure and a third plastic packaging layer on the upper surface of the second plastic packaging layer; the third electric connection structure is positioned in the third plastic package layer and is electrically connected with the second electric connection structure;
7) forming a top metal wire layer on the upper surface of the third plastic packaging layer, wherein the top metal wire layer is electrically connected with the third electrical connection structure;
8) removing the substrate and the sacrificial layer;
9) and forming a solder ball bump below the redistribution layer, wherein the solder ball bump is electrically connected with the redistribution layer.
In step 1), referring to step S1 in fig. 1 and fig. 2, a substrate 10 is provided, and a sacrificial layer 11 is formed on an upper surface of the substrate 10.
as an example, the material of the substrate 10 may be one or a composite of two or more of silicon, glass, silicon oxide, ceramic, polymer and metal, and the shape thereof may be circular, square or any other desired shape. Preferably, in this embodiment, the material of the substrate 10 is silicon.
As an example, the sacrificial layer 11 is used as a separation layer between the redistribution layer and the substrate 10 in the subsequent process, and is preferably made of an adhesive material with a smooth surface, which must have a certain bonding force with the redistribution layer, and also has a strong bonding force with the substrate 10, and generally, the bonding force between the sacrificial layer 11 and the substrate 10 needs to be greater than that with the redistribution layer.
As an example, the sacrificial layer 11 may include a polymer layer or a tape-shaped adhesive layer; specifically, the material of the sacrificial layer 11 may be selected from an adhesive tape (e.g., a die attach film, a non-conductive film, or the like) having two adhesive surfaces, an adhesive glue formed by a spin coating process, or the like; preferably, in this embodiment, the sacrificial layer 11 is preferably a UV tape, which is easily torn off after being irradiated by UV light (ultraviolet light); of course, in other examples, the sacrificial layer 11 may also be formed by other material layers formed by a physical vapor deposition method or a chemical vapor deposition method, such as Epoxy resin (Epoxy), silicone rubber (silicone rubber), Polyimide (PI), Polybenzoxazole (PBO), benzocyclobutene (BCB), and the like, and when the substrate 10 is subsequently separated, the sacrificial layer 11 may be removed by wet etching, chemical mechanical polishing, and the like.
the sacrificial layer 11 may also be formed by an automatic patch process, as an example.
In step 2), please refer to step S2 in fig. 1 and fig. 3 to 5, a redistribution layer 12 is formed on the upper surface of the sacrificial layer 11.
As an example, in step 2), forming the redistribution layer 12 on the upper surface of the sacrificial layer 11 may include the following steps:
2-1) forming a bottom dielectric layer 121 on the upper surface of the sacrificial layer 11, as shown in fig. 3;
2-2) forming a plastic packaging material layer 122 on the upper surface of the bottom dielectric layer 121, as shown in fig. 3;
2-3) forming a seed layer 123 on the upper surface of the plastic packaging material layer 122, as shown in fig. 3;
2-4) performing patterning processing on the seed layer 123 and the plastic packaging material layer 122, as shown in fig. 4; specifically, a photolithography etching process may be used to perform patterning processing on the seed layer 123 and the plastic package material layer 122;
2-5) forming a wiring dielectric layer 124 and a metal stack structure 125 on the upper surface of the bottom dielectric layer 121, wherein the metal stack structure 125 is located in the wiring dielectric layer 124 and electrically connected to the seed layer 123, as shown in fig. 5; the metal stack structure 125 includes a plurality of metal wire layers (not shown) arranged at intervals and metal plugs (not shown) located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.
as an example, the material of the bottom dielectric layer 121 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the bottom dielectric layer 121 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, or the like.
By way of example, the material of the molding compound layer 122 may include, but is not limited to, polyimide, silicone, epoxy, or the like.
as an example, the seed layer 123 may be formed using, but not limited to, a sputtering process; the material of the seed layer 123 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 123 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.
As an example, the material of the wiring dielectric layer 124 may include a low-k dielectric material. As an example, the wiring dielectric layer 124 may use one of epoxy, silicon gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the wiring dielectric layer 124 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, or the like.
As an example, the metal line layer may include a single metal layer, and may also include two or more metal layers. As an example, the material of the metal wire layer and the material of the metal plug may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
In step 3), please refer to step S3 in fig. 1 and fig. 6, a chip 13 is provided, the chip 13 is flip-chip bonded to the upper surface of the redistribution layer 12, and the chip 13 is electrically connected to the redistribution layer 12.
As an example, the chip 13 may be any functional chip, a device structure (not shown) may be formed in the chip 13, and a connection pad (not shown) may be formed on the front surface of the chip 13, and the connection pad is electrically connected to the device structure.
As an example, the chip 13 may be flip-chip bonded to the upper surface of the redistribution layer 12 by using any one of existing bonding processes; the connection pads of the chip 13 are electrically connected to the metal stack structure 125 in the redistribution layer 12.
In step 4), please refer to step S4 in fig. 1 and fig. 6 to 8, forming a first electrical connection structure 14 and a first molding compound layer 15 on the upper surface of the redistribution layer 12; the first electrical connection structure 14 is located in the first molding compound layer 15, and the first electrical connection structure 14 is electrically connected with the redistribution layer 12; the first plastic package layer 15 is used for plastic packaging the chip 13 and the first electrical connection structure 14.
As an example, a wire bonding process or a pillar bonding process may be used to form the first electrical connection structure 14 on the upper surface of the redistribution layer 12; the first electrical connection structure 14 may include a wire bond or a conductive pillar.
As an example, the number of the first electrical connection structures 14 may be set according to actual needs, only four first electrical connection structures 14 are illustrated in fig. 6 to 8 as an example, and in an actual example, the number of the first electrical connection structures 14 is not limited thereto.
As an example, the first molding layer 15 may be formed on the upper surface of the rewiring layer 12 using, but not limited to, a molding underfill process, an imprint molding process, a transfer molding process, a liquid encapsulation molding process, a vacuum lamination process, or a spin coating process; preferably, in this embodiment, a mold underfill process is used to form the first molding layer 15 on the upper surface of the redistribution layer 12. The first plastic package layer 15 is formed by adopting a molding underfill process, and the first plastic package layer 15 can smoothly and rapidly fill the gap between the chip 13 and the first electrical connection structure 14, so that interface delamination can be effectively avoided; and the molding underfill process is not limited as the capillary underfill process in the prior art, greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.
by way of example, the material of the first molding layer 15 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy resin, or the like.
As an example, the upper surface of the first molding compound layer 15 initially formed may be higher than the top of the first electrical connection structure 14, as shown in fig. 7, in this case, after the first molding compound layer 15 is formed, a process of thinning the first molding compound layer 15 is further performed, and specifically, the first molding compound layer 15 may be thinned by, but not limited to, a chemical mechanical polishing process, so that the remaining upper surface of the first molding compound layer 15 is flush with the top of the first electrical connection structure 14, as shown in fig. 8. Of course, in other examples, the upper surface of the first molding compound layer 15 is formed to be flush with the top of the first electrical connection structure 14, as shown in fig. 8, and in this case, the process of thinning the first molding compound layer 15 can be omitted.
As an example, as shown in fig. 9, after the step 4), the following steps are further included: a first interlayer dielectric layer 16 and a first redistribution metal layer 17 are formed on the upper surface of the first molding compound layer 15, the first redistribution metal layer 17 is located in the first interlayer dielectric layer 16, and the first redistribution metal layer 17 is electrically connected to the first electrical connection structure 14. The first interlayer dielectric layer 16 can enhance the bonding force between the first molding compound layer 15 and the second molding compound layer 19 formed subsequently, and meanwhile, the first rewiring metal layer 17 in the first interlayer dielectric layer 16 can realize rewiring, and the position and the number of the second electrical connection structures 18 formed subsequently can be adjusted as required.
As an example, the material of the first interlayer dielectric layer 16 may include a low-k dielectric material. As an example, the first interlayer dielectric layer 16 may use one of epoxy, silicon gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the first interlayer dielectric layer 16 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, or the like.
as an example, the material of the first rewiring metal layer 17 may include one material or a combination of two or more materials of copper, aluminum, nickel, gold, silver, and titanium.
In step 5), please refer to step S5 in fig. 1 and fig. 10 to 11, forming a second electrical connection structure 18 and a second molding layer 19 on the upper surface of the first molding layer 15; the second electrical connection structure 18 is located in the second molding layer 19, and the second electrical connection structure 18 is electrically connected to the first electrical connection structure 14.
when the first interlayer dielectric layer 16 and the first redistribution metal layer 17 are formed on the upper surface of the first molding layer 15, the second molding layer 19 is formed on the upper surface of the first interlayer dielectric layer 16, the second electrical connection structure 18 is formed on the upper surface of the first redistribution metal layer 17, and the second electrical connection structure 18 is electrically connected to the first electrical connection structure 14 through the first redistribution metal layer 17.
as an example, the second electrical connection structure 18 may be formed by a wire bonding process or a post bonding process; the second electrical connection structure 18 may include a wire bond or a conductive post.
as an example, the number of the second electrical connection structures 18 may be set according to actual needs, only four second electrical connection structures 18 are illustrated in fig. 10 to 11 as an example, and in an actual example, the number of the second electrical connection structures 18 is not limited thereto.
by way of example, the second molding layer 19 may be formed using, but not limited to, a molding underfill process, an imprint molding process, a transfer molding process, a liquid-tight molding process, a vacuum lamination process, a spin coating process, or the like; preferably, in this embodiment, the second molding layer 19 is formed by a mold underfill process. The second plastic package layer 19 is formed by adopting a molding bottom filling process, and the second plastic package layer 19 can smoothly and quickly fill the gap between the second electrical connection structures 18, so that interface delamination can be effectively avoided; and the molding underfill process is not limited as the capillary underfill process in the prior art, greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.
By way of example, the material of the second molding layer 19 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy resin, or the like.
As an example, the orthographic projection of the second molding layer 19 on the upper surface of the first molding layer 15 is located in the upper surface of the first molding layer 15; that is, the orthographic projection edges of the second plastic package layer 19 on the upper surface of the first plastic package layer 15 are all located in the upper surface of the first plastic package layer 15 and have a distance with the edges of the upper surface of the first plastic package layer 15; that is, the dimension of the cross section (i.e., the section parallel to the upper surface of the substrate 10) of the second molding layer 19 in each direction is smaller than the dimension of the upper surface of the first molding layer 15 in the corresponding direction; that is, the area of the orthographic projection of the second molding layer 19 on the upper surface of the first molding layer 15 is smaller than the area of the upper surface of the first molding layer 15.
As an example, as shown in fig. 12, the following steps are further included after step 5): a second interlayer dielectric layer 20 and a second redistribution metal layer 21 are formed on the upper surface of the second molding compound layer 19, the second redistribution metal layer 21 is located in the second interlayer dielectric layer 20, and the second redistribution metal layer 21 is electrically connected to the second electrical connection structure 18. The second interlayer dielectric layer 20 can enhance the bonding force between the second molding compound layer 19 and the subsequently formed third molding compound layer 23, and meanwhile, the second rewiring metal layer 21 in the second interlayer dielectric layer 20 can realize rewiring, and the position and the number of the subsequently formed third electrical connection structures 22 can be adjusted according to requirements.
As an example, the material of the second interlayer dielectric layer 20 may include a low-k dielectric material. As an example, the second interlayer dielectric layer 20 may use one of epoxy, silicon gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the second interlayer dielectric layer 20 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, and the like.
As an example, the material of the second rewiring metal layer 21 may include one material or a combination of two or more materials of copper, aluminum, nickel, gold, silver, and titanium.
in step 6), please refer to step S6 in fig. 1 and fig. 13 to 14, forming a third electrical connection structure 22 and a third molding layer 23 on the upper surface of the second molding layer 19; the third electrical connection structure 22 is located in the third molding layer 23, and the third electrical connection structure 22 is electrically connected to the second electrical connection structure 18.
When the second interlayer dielectric layer 20 and the second redistribution metal layer 21 are formed on the upper surface of the second molding compound layer 19, the third molding compound layer 23 is formed on the upper surface of the second interlayer dielectric layer 20, the third electrical connection structure 22 is formed on the upper surface of the second redistribution metal layer 21, and the third electrical connection structure 22 is electrically connected to the second electrical connection structure 18 through the second redistribution metal layer 21.
as an example, the third electrical connection structure 22 may be formed by a wire bonding process or a pillar bonding process; the third electrical connection structure 22 may include a wire bond or a conductive post.
as an example, the number of the third electrical connection structures 22 may be set according to actual needs, only four third electrical connection structures 22 are illustrated in fig. 13 to 14 as an example, and in an actual example, the number of the third electrical connection structures 22 is not limited thereto.
By way of example, the third molding layer 23 may be formed using, but not limited to, a molding underfill process, an imprint molding process, a transfer molding process, a liquid-tight molding process, a vacuum lamination process, a spin coating process, or the like; preferably, in this embodiment, the third molding layer 23 is formed by a mold underfill process. The third plastic package layer 23 is formed by adopting a molding underfill process, and the third plastic package layer 23 can smoothly and rapidly fill the gap between the third electrical connection structures 22, so that interface delamination can be effectively avoided; and the molding underfill process is not limited as the capillary underfill process in the prior art, greatly reduces the process difficulty, can be used for smaller connection gaps, and is more suitable for stacked structures.
By way of example, the material of the third molding layer 23 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy resin, or the like.
As an example, an orthographic projection of the third molding layer 23 on the upper surface of the second molding layer 19 is located in the upper surface of the second molding layer 19; that is, the edges of the orthographic projection of the third plastic package layer 23 on the upper surface of the second plastic package layer 19 are all located in the upper surface of the second plastic package layer 19, and have a distance from the edges of the upper surface of the second plastic package layer 19; that is, the dimension of the cross section (i.e., the section parallel to the upper surface of the substrate 10) of the third molding layer 23 in each direction is smaller than the dimension of the upper surface of the second molding layer 19 in the corresponding direction; that is, the area of the orthographic projection of the third molding layer 23 on the upper surface of the second molding layer 19 is smaller than the area of the upper surface of the second molding layer 19.
As an example, the thickness of the second molding layer 19 is smaller than the thickness of the first molding layer 15 and larger than the thickness of the third molding layer 23. Of course, in other examples, the thickness of the first molding layer 15, the thickness of the second molding layer 19, and the thickness of the third molding layer 23 may be the same.
In step 7), please refer to step S7 in fig. 1 and fig. 15, a top metal wire layer 24 is formed on the upper surface of the third molding layer 23, and the top metal wire layer 24 is electrically connected to the third electrical connection structure 22.
as an example, the material of the top metal wire layer 24 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
In step 8), referring to step S8 in fig. 1 and fig. 16, the substrate 10 and the sacrificial layer 11 are removed.
As an example, a grinding process, a thinning process, or a tearing process may be used to remove the sacrificial layer 11 and the substrate 10; preferably, in this embodiment, the substrate 10 is removed by tearing off the sacrificial layer 11.
in step 9), please refer to step S9 in fig. 1 and fig. 17 to 18, forming solder ball bumps 25 below the redistribution layer 12, wherein the solder bumps 25 are electrically connected to the redistribution layer 12.
as an example, in step 9), forming the solder ball bump 25 under the redistribution layer 12 may include the following steps:
9-1) forming an opening 26 in the bottom dielectric layer 121 and the plastic packaging material layer 122, wherein the seed layer 123 is exposed from the opening 26, as shown in fig. 17;
9-2) forming solder ball bumps 25 in the openings 26, wherein the solder ball bumps 25 are in contact with the seed layer 123, as shown in fig. 18.
As an example, the material of the solder ball bump 25 may include at least one of copper and tin.
Example two
With reference to fig. 18 with reference to fig. 2 to fig. 17, the present invention further provides a 3D chip package structure, where the 3D chip package structure includes: a rewiring layer 12; a chip 13, the chip 13 being flip-chip bonded to an upper surface of the redistribution layer 12, and the chip 13 being electrically connected to the redistribution layer 12; a first electrical connection structure 14, wherein the first electrical connection structure 14 is located on the upper surface of the redistribution layer 12, and the first electrical connection structure 14 is electrically connected with the redistribution layer 12; the first plastic package layer 15 is located on the upper surface of the rewiring layer 12, and the chip 13 and the first electrical connection structure 14 are plastically packaged by the first plastic package layer 15; a second electrical connection structure 18, wherein the second electrical connection structure 18 is located on the upper surface of the first molding compound layer 15, and the second point connection structure 18 is electrically connected with the first electrical connection structure 14; the second plastic package layer 19 is positioned on the upper surface of the first plastic package layer 15, and the second electrical connection structure 18 is plastically packaged by the second plastic package layer 19; a third electrical connection structure 22, wherein the third electrical connection structure 22 is located on the upper surface of the second molding layer 19, and the third electrical connection structure 22 is electrically connected to the second electrical connection structure 18; the third plastic package layer 23 is located on the upper surface of the second plastic package layer 19, and the third plastic package layer 23 plastically packages the third electrical connection structure 22; a top metal wire layer 24, wherein the top metal wire layer 24 is located on the upper surface of the third plastic package layer 23, and the top metal wire layer 24 is electrically connected with the third electrical connection structure 22; and the solder ball bump 25 is positioned on the lower surface of the redistribution layer 12, and the solder ball bump 25 is electrically connected with the redistribution layer 12.
As an example, the re-routing layer 12 may include: a wiring dielectric layer 124; a metal stack structure 125, wherein the metal stack structure 125 is located in the wiring dielectric layer 124, the metal stack structure 125 includes a plurality of metal wire layers (not shown) arranged at intervals, and a metal plug (not shown) located between adjacent metal wire layers to electrically connect the adjacent metal wire layers.
As an example, the re-routing layer 12 may further include: a seed layer 123, wherein the seed layer 123 is located on a lower surface of the wiring dielectric layer 124, and the seed layer 123 is electrically connected to the metal stack structure 125; a plastic packaging material layer 122, where the plastic packaging material layer 122 is located on the lower surface of the seed layer 123; the wiring dielectric layer 124 encapsulates the plastic package material layer 122 and the bottom dielectric layer 121 of the seed layer 123, and the bottom dielectric layer 121 is located on the lower surface of the wiring dielectric layer 124.
As an example, the material of the bottom dielectric layer 121 may include a low-k dielectric material. Specifically, the material of the second dielectric layer 20 may include one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass; the bottom dielectric layer 121 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, or the like.
By way of example, the material of the molding compound layer 122 may include, but is not limited to, polyimide, silicone, epoxy, or the like.
As an example, the seed layer 123 may be formed using, but not limited to, a sputtering process; the material of the seed layer 123 may include at least one of Ti (titanium) and Cu (copper); specifically, the seed layer 123 may be a titanium layer, a copper layer, a stacked structure of a titanium layer and a copper layer, or a titanium-copper alloy layer.
as an example, the material of the wiring dielectric layer 124 may include a low-k dielectric material. As an example, the wiring dielectric layer 124 may use one of epoxy, silicon gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the wiring dielectric layer 124 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, or the like.
As an example, the metal line layer may include a single metal layer, and may also include two or more metal layers. As an example, the material of the metal wire layer and the material of the metal plug may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
As an example, the chip 13 may be any functional chip, a device structure (not shown) may be formed in the chip 13, and a connection pad (not shown) may be formed on the front surface of the chip 13, and the connection pad is electrically connected to the device structure.
As an example, the first electrical connection structure 14 may include a wire bond or a conductive pillar.
as an example, the number of the electrical connection structures 14 may be set according to actual needs, fig. 18 only illustrates four first electrical connection structures 14 as an example, and in an actual example, the number of the first electrical connection structures 14 is not limited thereto.
by way of example, the material of the first molding layer 15 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy resin, or the like.
as an example, the upper surface of the first molding layer 15 is flush with the top of the first electrical connection structure 14.
As an example, the second electrical connection structure 18 may include a wire bond or a conductive post.
as an example, the number of the second electrical connection structures 18 may be set according to actual needs, fig. 18 only illustrates four of the second electrical connection structures 18 as an example, and in an actual example, the number of the second electrical connection structures 18 is not limited thereto.
By way of example, the material of the second molding layer 19 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy resin, or the like.
As an example, the upper surface of the second molding layer 19 is flush with the upper surface of the second electrical connection structure 18.
As an example, the orthographic projection of the second molding layer 19 on the upper surface of the first molding layer 15 is located in the upper surface of the first molding layer 15; that is, the orthographic projection edges of the second plastic package layer 19 on the upper surface of the first plastic package layer 15 are all located in the upper surface of the first plastic package layer 15 and have a distance with the edges of the upper surface of the first plastic package layer 15; that is, the dimension of the cross section (i.e., the section parallel to the upper surface of the substrate 10) of the second molding layer 19 in each direction is smaller than the dimension of the upper surface of the first molding layer 15 in the corresponding direction; that is, the area of the orthographic projection of the second molding layer 19 on the upper surface of the first molding layer 15 is smaller than the area of the upper surface of the first molding layer 15.
As an example, the third electrical connection structure 22 may include a wire bond or a conductive post.
As an example, the number of the third electrical connection structures 22 may be set according to actual needs, fig. 18 only illustrates four third electrical connection structures 22 as an example, and in an actual example, the number of the third electrical connection structures 22 is not limited thereto.
by way of example, the material of the third molding layer 23 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy resin, or the like.
As an example, the upper surface of the third molding layer 23 is flush with the top of the third electrical connection structure 22.
As an example, an orthographic projection of the third molding layer 23 on the upper surface of the second molding layer 19 is located in the upper surface of the second molding layer 19; that is, the edges of the orthographic projection of the third plastic package layer 23 on the upper surface of the second plastic package layer 19 are all located in the upper surface of the second plastic package layer 19, and have a distance from the edges of the upper surface of the second plastic package layer 19; that is, the dimension of the cross section (i.e., the section parallel to the upper surface of the substrate 10) of the third molding layer 23 in each direction is smaller than the dimension of the upper surface of the second molding layer 19 in the corresponding direction; that is, the area of the orthographic projection of the third molding layer 23 on the upper surface of the second molding layer 19 is smaller than the area of the upper surface of the second molding layer 19.
As an example, the thickness of the second molding layer 19 is smaller than the thickness of the first molding layer 15 and larger than the thickness of the third molding layer 23. Of course, in other examples, the thickness of the first molding layer 15, the thickness of the second molding layer 19, and the thickness of the third molding layer 23 may be the same.
as an example, the material of the top metal wire layer 24 may include one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
as an example, the solder ball bumps 25 are in contact with the seed layer 123.
as an example, the material of the solder ball bump 25 may include at least one of copper and tin.
As an example, the 3D chip packaging structure further includes: a first interlayer dielectric layer 16, the first interlayer dielectric layer 16 being located between the first molding layer 15 and the second molding layer 19; a first redistribution metal layer 17, the first redistribution metal layer 17 being located within the first interlayer dielectric layer 16, and the first redistribution metal layer 17 being electrically connected to the first electrical connection structure 14 and the second electrical connection structure 18; a second interlayer dielectric layer 20, the second interlayer dielectric layer 20 being located between the second molding layer 19 and the third molding layer 23; a second redistribution metal layer 21, the second redistribution metal layer 21 being located within the second interlayer dielectric layer 20, and the second redistribution metal layer 21 being electrically connected to the second electrical connection structure 18 and the third electrical connection structure 22.
As an example, the material of the first interlayer dielectric layer 16 may include a low-k dielectric material. As an example, the first interlayer dielectric layer 16 may use one of epoxy, silicon gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the first interlayer dielectric layer 16 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, or the like.
as an example, the material of the first rewiring metal layer 17 may include one material or a combination of two or more materials of copper, aluminum, nickel, gold, silver, and titanium.
As an example, the material of the second interlayer dielectric layer 20 may include a low-k dielectric material.
As an example, the second interlayer dielectric layer 20 may use one of epoxy, silicon gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the second interlayer dielectric layer 20 may be formed using a process such as spin coating, CVD, plasma enhanced CVD, and the like.
as an example, the material of the second rewiring metal layer 21 may include one material or a combination of two or more materials of copper, aluminum, nickel, gold, silver, and titanium.
To sum up, the utility model provides a 3D chip packaging structure, 3D chip packaging structure includes: rewiring layers; a chip flip-chip bonded to an upper surface of the rewiring layer and electrically connected to the rewiring layer; a first electrical connection structure on an upper surface of the rewiring layer and electrically connected to the rewiring layer; the first plastic packaging layer is positioned on the upper surface of the rewiring layer and is used for plastically packaging the chip and the first electric connection structure; the second electrical connection structure is positioned on the upper surface of the first plastic package layer and is electrically connected with the first electrical connection structure; the second plastic packaging layer is positioned on the upper surface of the first plastic packaging layer and plastically packages the second electric connection structure; the third electrical connection structure is positioned on the upper surface of the second plastic package layer and is electrically connected with the second electrical connection structure; the third plastic packaging layer is positioned on the upper surface of the second plastic packaging layer and plastically packages the third electric connection structure; the top metal wire layer is positioned on the upper surface of the third plastic packaging layer and is electrically connected with the third electric connection structure; and the solder ball bump is positioned on the lower surface of the rewiring layer and is electrically connected with the rewiring layer. The utility model discloses an among the 3D chip package structure, the chip has realized the 3D encapsulation, and the cost is lower, the encapsulation integrated level is high, can satisfy miniaturized development trend's needs.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. The utility model provides a 3D chip package structure, its characterized in that, 3D chip package structure includes:
rewiring layers;
A chip flip-chip bonded to an upper surface of the rewiring layer and electrically connected to the rewiring layer;
A first electrical connection structure on an upper surface of the rewiring layer and electrically connected to the rewiring layer;
The first plastic packaging layer is positioned on the upper surface of the rewiring layer and is used for plastically packaging the chip and the first electric connection structure;
the second electrical connection structure is positioned on the upper surface of the first plastic package layer and is electrically connected with the first electrical connection structure;
The second plastic packaging layer is positioned on the upper surface of the first plastic packaging layer and plastically packages the second electric connection structure;
The third electrical connection structure is positioned on the upper surface of the second plastic package layer and is electrically connected with the second electrical connection structure;
The third plastic packaging layer is positioned on the upper surface of the second plastic packaging layer and plastically packages the third electric connection structure;
The top metal wire layer is positioned on the upper surface of the third plastic packaging layer and is electrically connected with the third electric connection structure;
And the solder ball bump is positioned on the lower surface of the rewiring layer and is electrically connected with the rewiring layer.
2. The 3D chip packaging structure according to claim 1, wherein: the re-routing layer includes:
A wiring dielectric layer;
The metal laminated structure is positioned in the wiring dielectric layer and comprises a plurality of metal wire layers which are arranged at intervals and metal plugs, and the metal plugs are positioned between the adjacent metal wire layers so as to electrically connect the adjacent metal wire layers.
3. The 3D chip packaging structure according to claim 2, wherein: the re-routing layer further comprises:
The seed layer is positioned on the lower surface of the wiring dielectric layer and is electrically connected with the metal laminated structure;
the plastic packaging material layer is positioned on the lower surface of the seed layer; the wiring dielectric layer wraps the seed layer and the plastic packaging material layer;
And the bottom dielectric layer is positioned on the lower surface of the wiring dielectric layer.
4. the 3D chip packaging structure according to claim 1, wherein: the first, second and third electrical connection structures include bonding wires or conductive pillars.
5. the 3D chip packaging structure according to claim 1, wherein: the 3D chip packaging structure further comprises:
A first interlayer dielectric layer located between the first plastic package layer and the second plastic package layer;
a first redistribution metal layer within the first interlayer dielectric layer and electrically connected to the first and second electrical connection structures;
A second interlayer dielectric layer located between the second plastic package layer and the third plastic package layer;
And the second rewiring metal layer is positioned in the second interlayer dielectric layer and is electrically connected with the second electric connection structure and the third electric connection structure.
6. The 3D chip packaging structure according to any one of claims 1 to 5, wherein: the orthographic projection of the second plastic package layer on the upper surface of the first plastic package layer is positioned in the upper surface of the first plastic package layer; and the orthographic projection of the third plastic packaging layer on the upper surface of the second plastic packaging layer is positioned in the upper surface of the second plastic packaging layer.
7. the 3D chip packaging structure according to claim 6, wherein: the thickness of the second plastic packaging layer is smaller than that of the first plastic packaging layer and larger than that of the third plastic packaging layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920852233.2U CN209804639U (en) | 2019-06-06 | 2019-06-06 | 3D chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920852233.2U CN209804639U (en) | 2019-06-06 | 2019-06-06 | 3D chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209804639U true CN209804639U (en) | 2019-12-17 |
Family
ID=68833782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920852233.2U Active CN209804639U (en) | 2019-06-06 | 2019-06-06 | 3D chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209804639U (en) |
-
2019
- 2019-06-06 CN CN201920852233.2U patent/CN209804639U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10056350B2 (en) | Fan-out package structure, and manufacturing method thereof | |
| CN107706521B (en) | Fan-out type antenna packaging structure and preparation method thereof | |
| CN107180814B (en) | Electronic device | |
| US10276545B1 (en) | Semiconductor package and manufacturing method thereof | |
| WO2017049928A1 (en) | Chip packaging structure and packaging method therefor | |
| US10593641B2 (en) | Package method and package structure of fan-out chip | |
| CN106997855A (en) | Ic package and forming method thereof | |
| WO2017041519A1 (en) | Chip packaging method | |
| CN105374693A (en) | Semiconductor packages and methods of forming the same | |
| CN109285828B (en) | Fan-out antenna packaging structure with air cavity and preparation method thereof | |
| CN110783282A (en) | Packaging structure | |
| CN107706520A (en) | Fan-out-type antenna packages structure and preparation method thereof | |
| CN110137157B (en) | Semiconductor packaging structure and preparation method thereof | |
| CN111029263A (en) | Wafer level SIP module structure and preparation method thereof | |
| CN107195625A (en) | Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof | |
| US11735564B2 (en) | Three-dimensional chip packaging structure and method thereof | |
| CN209804637U (en) | Semiconductor packaging structure | |
| CN209804651U (en) | Semiconductor packaging structure | |
| CN114188227A (en) | Fan-out type packaging structure and packaging method | |
| CN112018047A (en) | Chip packaging structure and chip packaging method | |
| CN210182380U (en) | Semiconductor packaging structure | |
| CN206931602U (en) | The two-sided system-level laminated packaging structure of plastic packaging fan-out-type | |
| CN112054002A (en) | 3D chip packaging structure and preparation method thereof | |
| CN209804639U (en) | 3D chip packaging structure | |
| CN209929301U (en) | Semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |