CN209747502U - Chip substrate and packaged chip - Google Patents

Abstract

The application discloses chip base plate and encapsulation chip is equipped with a plurality of guide holes on this chip base plate, and the interval of the guide hole of the central point of chip base plate position is less than the interval of the guide hole of the marginal point of chip base plate position. The packaging chip comprises a bare chip and the chip substrate, wherein at least one groove is formed in the chip substrate, the bare chip is fixed in the groove, and the bare chip is electrically connected with the chip substrate. By means of the mode, the packaging yield of the chip can be improved, and the packaging cost of the chip is reduced.

Description

Chip substrate and packaged chip

Technical Field

The application relates to the technical field of chip packaging, in particular to a chip substrate and a packaged chip.

background

Along with the continuous development of integrated circuit technology, the performance of integrated circuit chips is continuously promoted, the heat dissipation problem of high-integration-level, high-performance and high-power chips becomes more and more important when the chips work, the working performance of devices can be influenced by the rise of the temperature of the chips, the service life of the devices is shortened, and even the devices are directly damaged due to high temperature. The design of high performance microprocessor packages is increasingly challenging.

In the long-term research and development process, the inventor of the present application finds that the shrinkage of the chip size is smaller than that of the chip substrate in the heating and cooling processes after the solder reflow because the thermal expansion coefficients of the chip material and the chip substrate at the soldering points are different, so that anisotropic stress can be generated on the soldering surface, the chip and the chip substrate are warped, and the working performance of the device can be affected.

Disclosure of Invention

The technical problem that this application mainly solved provides a chip base plate and encapsulation chip, can improve the encapsulation yield of chip, reduces the encapsulation cost of chip.

In order to solve the technical problem, the application adopts a technical scheme that: a plurality of guide holes are arranged on the chip substrate, and the distance between the guide holes in the center of the chip substrate is smaller than that between the guide holes in the edge of the chip substrate.

In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided a packaged chip comprising: a bare chip and the chip substrate; the chip substrate is provided with at least one groove, the bare chip is fixed in the groove, and the bare chip is electrically connected with the chip substrate.

Different from the prior art, the beneficial effects of the application are that: since the maximum stress usually occurs at the solder joints at the edge of the chip substrate, the present application provides the vias on the chip substrate in such a manner that the pitch of the vias at the center of the chip substrate is smaller than the pitch of the vias at the edge of the chip substrate. The utility model provides a guide hole density of chip substrate border position department is less than the guide hole density of central point department promptly, and the stress between the guide hole of dispersible border position department can effectively avoid peeling off, fracture scheduling problem with chip and chip substrate because of producing anisotropic stress and bringing on the face of weld, and then improves the reliability of product, improves the encapsulation yield of chip, reduces the encapsulation cost of chip.

drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a schematic structural diagram of an embodiment of a chip substrate according to the present application;

FIG. 2 is a schematic structural diagram of another embodiment of a chip substrate according to the present application;

FIG. 3 is a schematic structural diagram of a further embodiment of a chip substrate according to the present application;

FIG. 4 is a schematic structural diagram of a chip substrate according to yet another embodiment of the present application;

FIG. 5 is a partial schematic view of the chip substrate shown in FIG. 1 at the location of the via 11 according to an embodiment;

FIG. 6 is a partial schematic view of another embodiment of the chip substrate shown in FIG. 1 at the location of the via 11;

FIG. 7 is a schematic structural diagram of an embodiment of a packaged chip of the present application;

FIG. 8 is a schematic flow chart illustrating a method of fabricating a chip substrate according to an embodiment of the present disclosure;

fig. 9 is a schematic flow chart illustrating a method for fabricating a chip substrate according to another embodiment of the present disclosure;

FIG. 10 is a schematic flow chart diagram illustrating a method of fabricating a chip substrate according to yet another embodiment of the present invention;

Fig. 11 is a flowchart illustrating an embodiment of a chip packaging method according to the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the prior art, because the thermal expansion coefficients of the chip material and the chip substrate at the welding points are different, the shrinkage of the chip size is smaller than that of the chip substrate in the heating and cooling processes after the welding reflow, so that anisotropic stress can be generated on the welding surface, the chip and the chip substrate are warped, and the working performance of the device can be affected. The maximum stress usually occurs at the solder joints at the edge of the chip substrate, so that the solder joint connection at the edge of the chip substrate is easily damaged, even the chip and the chip substrate are peeled off and broken, which causes the failure of the chip device, resulting in the limitation of the packaging yield of the chip and the sharp increase of the packaging cost of the chip.

In order to solve the above technical problem, the present application provides a chip substrate. Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a chip substrate according to the present application. The chip substrate 10 is provided with a plurality of vias 11, and the pitch of the vias 11 at the center of the chip substrate 10 is smaller than the pitch of the vias 11 at the edge of the chip substrate 10. That is, in the present embodiment, the density of the via holes 11 at the center position of the chip substrate 10 is greater than the density of the via holes 11 at the edge position of the chip substrate 10 per unit area.

The shape of the plurality of guide holes 11 may be triangular, circular, square, or irregular. The position, shape, size and depth of the via hole 11 may be set according to the chip substrate 10 or actual requirements, and are not set herein. The guide hole 11 may be a blind hole having a half-through structure or a through hole.

Wherein, the chip substrate 10 can be a sheet with a thickness of more than 0.001mm, and has a flat and smooth surface, preferably a mirror surface; the shape may be various polygons such as a square and a hexagon, or a circle, an ellipse, a sector, or the like.

the chip substrate 10 is at least one of a composite metal chip substrate 10 and a plastic chip substrate 10, and various solid materials such as a conductor material (e.g., Au, Ag, Al, Cu, stainless steel, AlSiC, SiC, AlSi, NiCu, CuAl, carbon steel, etc.), or a semiconductor material (e.g., Si, Ge, GaAs, InP, etc.), or an insulating material (e.g., Al2O3, ceramic, glass, etc.), and a polymer material (e.g., rubber, plastic, polytetrafluoroethylene, etc.) may be used.

In this way, since the maximum stress usually occurs at the solder joints at the edge of the chip substrate 10, the present embodiment uses a distribution mode in which the pitch of the via holes 11 at the center of the chip substrate 10 is smaller than the pitch of the via holes 11 at the edge of the chip substrate 10, and the via holes 11 are provided on the chip substrate 10. That is, the density of the guide holes 11 at the edge of the chip substrate 10 is less than the density of the guide holes 11 at the center of the chip substrate in this embodiment, so that the stress between the guide holes 11 at the edge can be dispersed, and the problems of chip damage, peeling between the chip and the chip substrate 10, breakage and the like caused by the anisotropic stress generated on the bonding surface can be effectively avoided, thereby improving the reliability of the product, improving the packaging yield of the chip, and reducing the packaging cost of the chip.

Referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of a chip substrate according to the present application. In one embodiment, the spacing between the vias 11 gradually increases from the center of the chip substrate 10 to the edge of the chip substrate 10. The pitch between the plurality of via holes 11 refers to a value of a space between the center of each via hole 11 and the center of the adjacent via hole 11. For example. The pitch between the plurality of vias 11 at the center position of the chip substrate 10 is small, and the pitch between the plurality of vias 11 at the edge position of the chip substrate 10 is large.

As shown in fig. 2, in an embodiment, the plurality of guide holes at least form a first guide hole group 11A and a second guide hole group 11B, and in this embodiment, the first guide hole group 11A and the second guide hole group 11B are both linear and are arranged in a cross manner. It is to be understood that, in other embodiments, the first lead hole group 11A and the second lead hole group 11B may also have a curved shape. The pitch between the guide holes of the first guide hole group 11A gradually increases and the pitch between the guide holes of the second guide hole group 11B gradually increases from the center position to the edge position of the chip substrate. For example. The pitch between the plurality of guide holes of the first guide hole group 11A is small at the center position of the chip substrate, and the pitch between the plurality of guide holes of the first guide hole group 11A is large at the edge position of the chip substrate. The pitch between the plurality of guide holes of the second guide hole group 11B is small at the center position of the chip substrate, and the pitch between the plurality of guide holes of the second guide hole group 11B is large at the edge position of the chip substrate.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a chip substrate according to another embodiment of the present application. The plurality of guide holes can form a plurality of guide hole groups which are arranged in an equal-angle cross mode. For example, the plurality of guide holes may at least form four guide hole groups in a cross-shaped structure, the four guide hole groups are arranged in an equiangular manner, an included angle between a straight line where the center of a circle of a guide hole of each guide hole group is located and a straight line where the center of a circle of a guide hole of an adjacent guide hole group is located is 45 °, and the straight lines where the centers of circles of the guide holes of the four guide hole groups are located intersect at the same point. For another example, the plurality of guide holes may form at least three groups of guide holes, the three groups of guide holes are arranged in an equiangular cross manner, an included angle between a straight line where the center of a circle of a guide hole of each guide hole group is located and a straight line where the center of a circle of a guide hole of an adjacent guide hole group is located is 60 °, and the straight lines where the centers of circles of guide holes of the three groups of guide holes are located intersect at the same point.

Further, referring to fig. 4, fig. 4 is a schematic structural diagram of a chip substrate according to still another embodiment of the present application. The first guide hole group 11A and the second guide hole group 11B are perpendicular to each other. For example, two guide hole groups in a cross structure are perpendicular to each other, and an angle between a straight line where the center of a circle of a guide hole of the first guide hole group 11A is located and a straight line where the center of a circle of a guide hole of the second guide hole group 11B is located is 90 °.

referring to fig. 5, fig. 5 is a partial schematic view of an embodiment of the chip substrate in fig. 1 at the location of the via 11. At least a part of the inner wall of the via hole 11 is provided with a metal conductive layer 12, and the metal conductive layer 12 encloses a first cavity. The metal conductive layer 12 may be formed by an electroless plating or sputtering process. The first cavity is filled with a metal conductive material 120, and the metal conductive material 120 is selected from the group consisting of copper, tin, silver, platinum, gold, and combinations thereof.

Specifically, the metal conductive layer 12 may be formed on the inner wall of a part or all of the via hole 11 using a hot-melt process, an electroplating process, or a deposition process. For example, the metal conductive layer 12 may be formed on the wall of the via hole 11 by electroless plating, and the formation process of the metal conductive layer 12 is a hole metallization process. The metal conductive layer 12 completely covers the inner wall of the via 11 and encloses a first cavity, which can be used to fill the metal conductive material 120.

Referring to fig. 6, fig. 6 is a partial schematic view of another embodiment of the chip substrate in fig. 1 at the location of the via 11. At least a portion of the inner wall of the vias 11 may be provided with a metal heat conductive layer 13, the metal heat conductive layer 13 enclosing a second cavity. The metal heat conducting layer 13 may be formed by an electroless plating or sputtering process. The second cavity is filled with a metal heat conduction material 130, and the metal heat conduction material 130 is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and a combination thereof.

Specifically, the metal heat conductive layer 13 may be formed on the inner wall of a part or all of the via hole 11 by using a hot-melt process, an electroplating process, or a deposition process. For example, a metal layer may be formed on the hole wall of the via 11 by electroless plating, and the formation process of the metal heat conduction layer 13 is a hole metallization process. The metal heat conduction layer 13 completely covers the inner wall of the via hole 11 and encloses a second cavity which can be used to fill the above-mentioned metal heat conduction material 130. The graphene material has a very high in-plane thermal conductivity coefficient which can reach 5000W/m.K and is higher than that of carbon nanotubes and diamond, and the graphene is a thermal conductive material with optimal performance at present. The graphene is used as a thermal interface material, so that excellent heat dissipation performance is expected to be obtained, and the graphene has great market potential. Due to the physical properties of the graphene two-dimensional material, in order to obtain good heat dissipation performance, the graphene two-dimensional material needs to be vertically positioned between a heat source and a heat sink.

Referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment of a packaged chip according to the present application. The packaged chip 100 includes: a bare chip 20 and the chip substrate 10 of any of the above embodiments. Wherein, at least one groove is arranged on the chip substrate 10, the bare chip 20 is fixed in the groove, and the bare chip 20 is electrically connected with the chip substrate 10.

Specifically, the chip substrate 10 may be grooved by depth control milling, or by etching and laser ablation. A recess is formed in the chip substrate 10 for embedding a subsequent chip. The recess has a certain depth, and in this embodiment, the size of the recess is determined according to the size of the bare chip 20 to be embedded. The die 20 may be secured in the recess using an adhesive, which may be a die attach resin or a silver-based resin or other non-conductive adhesive that is capable of securing the die 20 in the recess, such that the die 20 is secured in the recess. When the chip substrate 10 needs to embed a plurality of chips with different thicknesses, the chips with different thicknesses are guaranteed to be kept coplanar after being packaged into the chip substrate 10, and the length and the width of the groove are at least larger than the size of the chip to be embedded, so that the groove can sufficiently accommodate the chip to be embedded.

further, a gap between the substrate 10 and the bare chip 20 may be filled with a filling material so that the groove is filled. The filling material is a material for semiconductor packaging, is usually liquid, has heat dissipation and insulation effects, and becomes solid at 120-300 ℃. It should be noted that the filling material may also be a material which is normally liquid, has heat dissipation and electric conduction functions, and becomes solid at 120-300 ℃, for example, if there is a bonding pad at the bottom of the bare chip 20, the material may be used to form an electrical connection with the bottom of the groove, and this is not limited herein.

The bare chip 20 includes a plurality of leads 21, and the leads 21 are connected to the metal conductive layer 12 or the metal conductive layer 13 in the vias 11 on the chip substrate 10 through conductive paste. In other embodiments, the bare chip 20 may be directly electrically connected to the chip substrate 10 through a filled conductive medium, thereby eliminating the need for leads or pins 21, etc.

Wherein, the packaged chip 100 is a chip 100 with power density of 350W/cm2 or/and hot spot of 10KW/cm2 or more.

When a large number of chips 100 with power density of more than 350W/cm2 or/and hot spots of more than 10KW/cm2 are used in the system, the controllable highest junction temperature of a radiator and a fan originally installed on the chip is only about 100 ℃, and the temperature of a chip packaging shell is required to be not more than 65 ℃ by design, if forced air cooling is adopted to solve the heat dissipation of the chip, the electronic product can be unstable in work. Therefore, the chip 100 is often overheated, and further, the shrinkage of the chip 100 is smaller than that of the chip substrate 10, so that an anisotropic stress is generated on the bonding surface, and the chip 100 and the chip substrate 10 are warped, thereby affecting the operation performance of the device. For such a chip 100, the chip substrate 10 in any of the above embodiments may be adopted, and the stress between the guide holes 11 at the edge position is dispersed, so that the problems of chip damage, peeling and fracture of the chip 100 and the chip substrate 10, and the like caused by the anisotropic stress generated on the bonding surface can be effectively avoided, and further, the reliability of the product is improved, the packaging yield of the chip 100 is improved, and the packaging cost of the chip 100 is reduced.

Referring to fig. 8, fig. 8 is a schematic flow chart illustrating a manufacturing method of a chip substrate according to an embodiment of the present disclosure. The manufacturing method comprises the following steps:

S11: a chip substrate is provided.

S12: a plurality of guide holes are formed on the chip substrate, and the distance between the guide holes at the center of the chip substrate is smaller than that at the edge of the chip substrate.

Specifically, a laser beam can be used to form a half-through blind via structure at a predetermined via hole position on one side of the chip substrate.

In step S12, the pitch between the vias is gradually increased from the center position of the chip substrate to the edge position of the chip substrate. The density of the guide holes at the edge position of the chip substrate is smaller than that at the center position, so that the stress between the guide holes at the edge position can be dispersed, the problems of chip damage, chip and chip substrate peeling, fracture and the like caused by the anisotropic stress generated on the welding surface can be effectively avoided, the reliability of products is improved, the packaging yield of the chips is improved, and the packaging cost of the chips is reduced.

Referring to fig. 9, fig. 9 is a schematic flow chart of a manufacturing method of a chip substrate according to another embodiment of the present disclosure. In one embodiment, the manufacturing method further includes:

S21: a chip substrate is provided.

s22: a plurality of guide holes are formed on the chip substrate, and the distance between the guide holes at the center of the chip substrate is smaller than that at the edge of the chip substrate.

S23: and electroplating a metal conductive layer on the inner wall of at least one part of the guide hole, wherein the metal conductive layer surrounds a first cavity.

S24: and filling the first cavity with a metal conductive material.

In the present embodiment, steps S21-S22 are the same as steps S11-S12 in the above embodiment, and for details, refer to the above embodiment and are not repeated herein.

Wherein the metal conductive material is selected from the group consisting of copper, tin, silver, platinum, gold, and combinations thereof. Specifically, a thermal melting process, an electroplating process or a deposition process may be used to form a metal conductive layer on the inner wall of at least a portion of the via. For example, a metal conductive layer may be formed on the wall of the via hole by electroless plating, and the formation process of the metal conductive layer is a hole metallization process. The metal conducting layer completely covers the inner wall of the guide hole and encloses a first cavity which can be used for filling the metal conducting material.

Referring to fig. 10, fig. 10 is a schematic flow chart of a manufacturing method of a chip substrate according to another embodiment of the present application. In one embodiment, the manufacturing method further includes:

S31: a chip substrate is provided.

s32: a plurality of guide holes are formed on the chip substrate, and the distance between the guide holes at the center of the chip substrate is smaller than that at the edge of the chip substrate.

S33: and electroplating a metal heat conduction layer on the inner wall of at least one part of the guide hole, wherein the metal heat conduction layer surrounds the second cavity.

S34: and filling the second cavity with a metal heat conduction material.

In the present embodiment, steps S31-S32 are the same as steps S11-S12 in the above embodiment, and for details, refer to the above embodiment and are not repeated herein.

Wherein the metal heat conducting material is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and combinations thereof. Specifically, the heat conductive layer may be formed on at least a portion of the inner wall of the via hole by a thermal melting process, an electroplating process, or a deposition process. For example, a metal heat conduction layer may be formed on the hole wall of the via hole by electroless plating, and the formation process of the metal heat conduction layer is a hole metallization process. The metal heat conduction layer completely covers the inner wall of the guide hole and encloses a first cavity which can be used for filling the metal heat conduction material.

for a detailed description of the chip substrate in the above method for manufacturing a chip substrate, please refer to the above chip substrate portion, which is not described herein.

Referring to fig. 11, fig. 11 is a schematic flowchart illustrating an embodiment of a chip packaging method according to the present application. The packaging method comprises the following steps:

S41: a chip substrate is provided.

s42: at least one groove is formed on the chip substrate.

Specifically, at least one groove is formed in the chip substrate to be embedded, and the groove may be formed in the chip substrate by depth control milling, or by etching and laser ablation, which is not limited herein. A groove is formed on the chip substrate so as to embed the subsequent chip. The recess has a certain depth, and in this embodiment, the size of the recess is determined according to the size of the chip to be embedded.

s43: and fixing the bare chip in the groove.

Specifically, the bare chip may be secured within the recess using glue. The bare chip is embedded in the groove, and the adhesive can be chip-attaching resin or silver-based resin or other non-conductive adhesive capable of fixing the chip in the groove, so that the bare chip is fixed in the groove.

S44: forming a plurality of guide holes on the chip substrate, and enabling the distance between the guide holes at the central position of the chip substrate to be smaller than the distance between the guide holes at the edge position of the chip substrate;

s45: and forming a metal conductive layer in at least one part of the guide hole, and electrically connecting the bare chip and the metal conductive layer.

specifically, a chip substrate with a bare chip mounted thereon is covered with an insulating resin laminate on one side thereof near the chip and then is subjected to vacuum hot pressing, and finally a blind via is laser-drilled by aligning a metal pad (i.e., an electrode of the chip, the thickness of which is generally 0.1 μm to 0.5 μm, for example, 0.1 μm, 0.2 μm, 0.4 μm or 0.5 μm) on the surface of the bare chip, and a conductive medium (e.g., a copper electrode) is formed through the blind via plating to electrically connect the chip and an external circuit.

The distance between the guide holes in the center of the chip substrate is smaller than that between the guide holes in the edge of the chip substrate.

Further, the bare chip includes a plurality of leads, and in step S45, the leads may be connected to the metal conductive layer through a conductive paste.

It should be noted that, for a detailed description of the chip in the above chip packaging method, please refer to the above chip packaging portion, which is not described herein again.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims (12)

1. A chip substrate is characterized in that a plurality of guide holes are arranged on the chip substrate, and the distance between the guide holes in the center of the chip substrate is smaller than that between the guide holes in the edge of the chip substrate;

at least one part of the inner wall of the guide hole is provided with a metal conducting layer or a metal heat conducting layer, the metal conducting layer surrounds a first cavity, and the metal heat conducting layer surrounds a second cavity.

2. the chip substrate according to claim 1, wherein a pitch between the plurality of vias gradually increases from a center position of the chip substrate to an edge position of the chip substrate.

3. The chip substrate according to claim 1, wherein the plurality of vias are formed into at least a first via group and a second via group, which are linear, and the first via group and the second via group are arranged in a crossing manner.

4. the chip substrate according to claim 3, wherein a pitch between the guide holes of the first guide hole group gradually increases and a pitch between the guide holes of the second guide hole group gradually increases from a center position to an edge position of the chip substrate.

5. The chip substrate according to claim 3, wherein the first and second via groups are linear and perpendicular to each other.

6. The chip substrate according to claim 1, wherein the first cavity is filled with a metal material selected from the group consisting of copper, tin, silver, platinum, gold, and combinations thereof.

7. The chip substrate according to claim 1, wherein the second cavity is filled with a metal heat conductive material selected from the group consisting of copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene, and combinations thereof.

8. The chip substrate according to claim 1, wherein the plurality of vias are circular or square in shape.

9. The chip substrate according to claim 1, wherein the chip substrate is at least one of a composite metal chip substrate and a plastic chip substrate.

10. A packaged chip, comprising: a bare chip and the chip substrate of any one of claims 1-9 above;

The chip substrate is provided with at least one groove, the bare chip is fixed in the groove, and the bare chip is electrically connected with the chip substrate.

11. The packaged chip of claim 10, wherein the bare chip comprises a plurality of leads, and the leads are connected to the metal conductive layer or the metal heat conductive layer in the vias on the chip substrate by a conductive adhesive.

12. The packaged chip of claim 10, wherein the packaged chip is a chip with a power density of 350W/cm2 or more and/or a hot spot of 10KW/cm2 or more.