CN111354684A - Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof - Google Patents
Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof Download PDFInfo
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- CN111354684A CN111354684A CN201811572176.9A CN201811572176A CN111354684A CN 111354684 A CN111354684 A CN 111354684A CN 201811572176 A CN201811572176 A CN 201811572176A CN 111354684 A CN111354684 A CN 111354684A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The application discloses a chip substrate and a manufacturing method thereof, a packaged chip and a packaging method thereof. The packaging chip comprises a bare chip and the chip substrate; at least one groove is arranged on the chip substrate, the bare chip is fixed in the groove, and the bare chip is electrically connected with the chip substrate. The manufacturing method of the chip substrate comprises the following steps: providing a chip substrate; a plurality of guide holes are formed on the chip substrate and distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes. By means of the mode, the packaging yield of the chip can be improved, and the packaging cost of the chip is reduced.
Description
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip substrate and a manufacturing method thereof, a packaged chip and a packaging method thereof.
Background
Along with the continuous development of integrated circuit technology, the performance of integrated circuit chips is continuously promoted, the heat dissipation problem of high integration degree and high performance of the chips during working becomes more and more important, the working performance of devices can be influenced by the rise of the temperature of the chips, the service life of the devices is shortened, and even the devices are directly damaged due to high temperature. The design of high performance microprocessor packages is increasingly challenging.
In the long-term research and development process, the inventor of the present application finds that the shrinkage of the chip size is smaller than that of the chip substrate in the heating and cooling processes after the solder reflow because the thermal expansion coefficients of the chip material and the chip substrate at the soldering points are different, so that anisotropic stress can be generated on the soldering surface, the chip and the chip substrate are warped, and the working performance of the device can be affected.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a chip substrate and a manufacturing method thereof, a packaged chip and a packaging method thereof, which can improve the packaging yield of the chip and reduce the packaging cost of the chip.
In order to solve the technical problem, the application adopts a technical scheme that: the chip substrate is provided with a plurality of guide holes, wherein the guide holes are rectangular guide holes, and the rectangular guide holes are distributed on the chip substrate in a rectangular array.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided a packaged chip comprising: a bare chip and the chip substrate; the chip substrate is provided with at least one groove, the bare chip is fixed in the groove, and the bare chip is electrically connected with the chip substrate.
In order to solve the above technical problem, the present application adopts another technical solution: a method for manufacturing a chip substrate is provided, which includes: providing a chip substrate; forming a plurality of guide holes on a chip substrate by adopting laser; the guide holes are rectangular guide holes which are distributed on the chip substrate in a rectangular array.
In order to solve the above technical problem, the present application adopts another technical solution that: a packaging method of a chip is provided, which comprises the following steps: providing a chip substrate; forming at least one groove on the chip substrate; fixing the bare chip in the groove; forming a plurality of guide holes on the chip substrate, and enabling the plurality of guide holes to be distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes; and forming a metal conductive layer in at least one part of the rectangular guide hole, and electrically connecting the bare chip and the metal conductive layer.
Different from the prior art, the beneficial effects of the application are that: rectangular guide holes with lower requirements on a laser drilling process are adopted, and the rectangular guide holes are arranged on the chip substrate in a rectangular array. The rectangular guide holes with larger sizes are adopted, so that the occupied area of the rectangular guide holes on the chip substrate is increased, the stress among the rectangular guide holes can be dispersed, the problems of chip damage, peeling between a bare chip and the chip substrate, breakage and the like caused by the anisotropic stress generated on a welding surface can be effectively avoided, the heat dissipation effect is increased, the reliability of a product is improved, the packaging yield of the chip is improved, and the packaging cost of the chip is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of an embodiment of a chip substrate according to the present application;
FIG. 2 is a partial schematic view of the chip substrate of FIG. 1 at the location of the rectangular via 11;
FIG. 3 is a partial schematic view of another embodiment of the chip substrate of FIG. 1 at the location of the rectangular via 11;
FIG. 4 is a schematic structural diagram of an embodiment of a packaged chip of the present application;
FIG. 5 is a schematic flow chart illustrating a method of fabricating a chip substrate according to an embodiment of the present disclosure;
fig. 6 is a schematic flow chart illustrating a method for manufacturing a chip substrate according to another embodiment of the present disclosure;
FIG. 7 is a schematic flow chart diagram illustrating a method of fabricating a chip substrate according to yet another embodiment of the present disclosure;
fig. 8 is a flowchart illustrating an embodiment of a chip packaging method according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to solve the above technical problem, the present application provides a chip substrate. Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a chip substrate according to the present application. The chip substrate 10 is provided with a plurality of vias 11, and the vias 11 are rectangular vias 11. The rectangular vias 11 are distributed in a rectangular array on the chip substrate.
Wherein the rectangular guide hole 11 has a side length of 0.3mm to 1mm, such as 0.3mm, 0.5mm, 0.7mm, 0.9mm or 1.0 mm. Preferably, the rectangular guide hole 11 has a side of 0.5 mm.
The hole center distance between two adjacent rectangular guide holes 11 is between 0.1mm and 0.5mm, such as 0.1mm, 0.2mm, 0.3mm, 0.4mm or 0.5 mm.
The rectangular guide hole 11 may be a blind hole having a half-through structure or a through hole.
Wherein, the chip substrate 10 can be a sheet with a thickness of more than 0.001mm, and has a flat and smooth surface, preferably a mirror surface; the shape may be various polygons such as a square and a hexagon, or various shapes such as a circle, an ellipse, and a sector.
The chip substrate 10 is at least one of a composite metal chip substrate 10 and a plastic chip substrate 10, and various solid materials such as a conductor material (e.g., Au, Ag, Al, Cu, stainless steel, AlSiC, AlSi, NiCu, CuAl, carbon steel, etc.), a semiconductor material (e.g., Si, Ge, GaAs, InP, etc.), or an insulating material (e.g., Al), can be used2O3Ceramic, glass, etc.), and polymeric materials (e.g., rubber, plastic, polytetrafluoroethylene, etc.).
Through the above manner, the present embodiment adopts the distribution manner of the rectangular guide holes with lower requirements on the laser drilling process, and the rectangular guide holes 11 are arranged on the chip substrate 10 in a rectangular array. The rectangular guide holes 11 with larger sizes are adopted, so that the occupied area of the rectangular guide holes 11 in the chip substrate 10 is increased, the stress among the rectangular guide holes 11 can be dispersed, the problems of chip damage, peeling and breakage of a bare chip and the chip substrate 10 and the like caused by anisotropic stress generated on a welding surface can be effectively avoided, the heat dissipation effect is increased, the reliability of a product is improved, the packaging yield of the chip is improved, and the packaging cost of the chip is reduced.
Referring to fig. 2, fig. 2 is a partial schematic view of the chip substrate in fig. 1 at a position of a rectangular via hole 11 according to an embodiment. At least a part of the inner wall of the via hole 11 is provided with a metal conductive layer 12, and the metal conductive layer 12 encloses a first cavity. The metal conductive layer 12 may be formed by an electroless plating or sputtering process. The first cavity is filled with a metal conductive material 120, and the metal conductive material 120 is selected from the group consisting of copper, tin, silver, platinum, gold, and combinations thereof.
Specifically, the metal conductive layer 12 may be formed on the inner wall of a part or all of the rectangular via hole 11 by using a hot-melt process, an electroplating process, or a deposition process. For example, the metal conductive layer 12 may be formed on the wall of the rectangular via 11 by electroless plating, and the formation process of the metal conductive layer 12 is a via metallization process. The metal conductive layer 12 completely covers the inner wall of the rectangular via hole 11 and encloses a first cavity, which can be used to fill the metal conductive material 120.
Referring to fig. 3, fig. 3 is a partial schematic view of another embodiment of the chip substrate in fig. 1 at the position of the rectangular via hole 11. At least a portion of the inner wall of the rectangular via 11 may be provided with a metal heat conductive layer 13, and the metal heat conductive layer 13 encloses a second cavity. The metal heat conducting layer 13 may be formed by an electroless plating or sputtering process. The second cavity is filled with a metal heat conduction material 130, and the metal heat conduction material 130 is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and a combination thereof.
Specifically, the metal heat conduction layer 13 may be formed on the inner wall of a part or all of the rectangular via hole 11 by using a hot-melt process, an electroplating process, or a deposition process. For example, a metal layer may be formed on the hole wall of the rectangular via 11 by electroless plating, and the formation process of the metal heat conduction layer 13 is a hole metallization process. The metal heat conduction layer 13 completely covers the inner wall of the rectangular via hole 11 and encloses a second cavity which can be used to fill the metal heat conduction material 130. The graphene material has a very high in-plane thermal conductivity coefficient which can reach 5000W/m.K and is higher than that of carbon nanotubes and diamond, and the graphene is a thermal conductive material with optimal performance at present. The graphene is used as a thermal interface material, so that excellent heat dissipation performance is expected to be obtained, and the graphene has great market potential. Due to the physical properties of the graphene two-dimensional material, in order to obtain good heat dissipation performance, the graphene two-dimensional material needs to be vertically positioned between a heat source and a heat sink.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a packaged chip according to the present application. The packaged chip 100 includes: a bare chip 20 and the chip substrate 10 of any of the above embodiments. Wherein, at least one groove is arranged on the chip substrate 10, the bare chip 20 is fixed in the groove, and the bare chip 20 is electrically connected with the chip substrate 10.
Specifically, the chip substrate 10 may be grooved by depth control milling, or by etching and laser ablation. A recess is formed in the chip substrate 10 for embedding a subsequent chip. The recess has a certain depth, and in this embodiment, the size of the recess is determined according to the size of the bare chip 20 to be embedded. The die 20 may be secured in the recess using an adhesive, which may be a die attach resin or a silver-based resin or other non-conductive adhesive that is capable of securing the die 20 in the recess, such that the die 20 is secured in the recess. When the chip substrate 10 needs to embed a plurality of chips with different thicknesses, the chips with different thicknesses are guaranteed to be kept coplanar after being packaged into the chip substrate 10, and the length and the width of the groove are at least larger than the size of the chip to be embedded, so that the groove can sufficiently accommodate the chip to be embedded.
Further, the gap between the substrate 10 and the bare chip 20 may be filled with a filling material such that the groove is filled, and the filling material may be a material for semiconductor packaging, typically a liquid, which has heat dissipation, insulation effects, and becomes solid at 120 ℃ -300 ℃. It should be noted that the filling material may also be a material which is normally liquid, has heat dissipation and electric conduction functions, and becomes solid at 120-300 ℃, for example, if there is a bonding pad at the bottom of the bare chip 20, the material may be used to form an electrical connection with the bottom of the groove, and this is not limited herein.
The bare chip 20 includes a plurality of leads 21, and the leads 21 are connected to the metal conductive layer 12 or the metal conductive layer 13 in the vias 11 on the chip substrate 10 through conductive paste. In other embodiments, the bare chip 20 may be directly electrically connected to the chip substrate 10 through a filled conductive medium, thereby eliminating the need for leads or pins 21, etc.
Wherein, the power density of the packaged chip 100 reaches 350W/cm2The above or/and hot spot reaches 10KW/cm2The above chip 100.
When the system uses a large amount of power, the density reaches 350W/cm2The above or/and hot spot reaches 10KW/cm2In the above chip 100, the controllable highest junction temperature of the original heat sink and fan of the chip is only about 100 ℃, and the temperature of the package shell of the chip is not more than 65 ℃ as required by the design, and if the heat dissipation of the chip is solved by adopting forced air cooling, the electronic product can be unstable in operation. Therefore, the chip 100 is often overheated, and further, the shrinkage of the chip 100 is smaller than that of the chip substrate 10, so that an anisotropic stress is generated on the bonding surface, and the chip 100 and the chip substrate 10 are warped, thereby affecting the operation performance of the device. For such a chip 100, the chip substrate 10 in any of the above embodiments may be adopted, and the stress between the vias 11 is dispersed, so that the problems of chip damage, peeling and fracture of the chip 100 and the chip substrate 10, and the like caused by the anisotropic stress generated on the bonding surface can be effectively avoided, and further the reliability of the product is improved, the packaging yield of the chip 100 is improved, and the packaging cost of the chip 100 is reduced.
Referring to fig. 5, fig. 5 is a schematic flow chart of an embodiment of a method for manufacturing a chip substrate according to the present application. The manufacturing method comprises the following steps:
s11: a chip substrate is provided.
S12: a plurality of guide holes are formed on the chip substrate and distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes.
Specifically, a laser beam can be used to form a half-through blind via structure at a predetermined via hole position on one side of the chip substrate. Wherein the rectangular guide hole 11 has a side length of 0.3mm to 1mm, such as 0.3mm, 0.5mm, 0.7mm, 0.9mm or 1.0 mm. Preferably, the rectangular guide hole 11 has a side of 0.5 mm. The hole center distance between two adjacent rectangular guide holes 11 is between 0.1mm and 0.5mm, such as 0.1mm, 0.2mm, 0.3mm, 0.4mm or 0.5 mm.
Through the mode, the rectangular guide hole with lower requirements on the laser drilling process is adopted in the embodiment, and the rectangular guide hole is arranged on the chip substrate in a rectangular array mode. The rectangular guide holes with larger sizes are adopted, so that the occupied area of the rectangular guide holes on the chip substrate is increased, the stress among the rectangular guide holes can be dispersed, the problems of chip damage, peeling of a bare chip and the chip substrate, breakage and the like caused by the anisotropic stress generated on a welding surface can be effectively avoided, the heat dissipation effect is increased, the reliability of a product is improved, the packaging yield of the chip is improved, and the packaging cost of the chip is reduced.
Referring to fig. 6, fig. 6 is a schematic flow chart of a manufacturing method of a chip substrate according to another embodiment of the present application. In one embodiment, the manufacturing method further includes:
s21: a chip substrate is provided.
S22: a plurality of guide holes are formed on the chip substrate and distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes.
S23: and electroplating a metal conductive layer on the inner wall of at least one part of the rectangular guide hole, wherein the metal conductive layer surrounds a first cavity.
S24: and filling the first cavity with a metal conductive material.
In the present embodiment, steps S21-S22 are the same as steps S11-S12 in the above embodiment, and for details, refer to the above embodiment and are not repeated herein.
Wherein the metal conductive material is selected from the group consisting of copper, tin, silver, platinum, gold, and combinations thereof.
Specifically, a thermal melting process, an electroplating process or a deposition process may be used to form a metal conductive layer on the inner wall of at least a portion of the via. For example, a metal conductive layer may be formed on the wall of the via hole by electroless plating, and the formation process of the metal conductive layer is a hole metallization process. The metal conducting layer completely covers the inner wall of the guide hole and encloses a first cavity which can be used for filling the metal conducting material.
Referring to fig. 7, fig. 7 is a schematic flow chart of a manufacturing method of a chip substrate according to another embodiment of the present disclosure. In one embodiment, the manufacturing method further includes:
s31: a chip substrate is provided.
S32: a plurality of guide holes are formed on the chip substrate and distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes.
S33: and electroplating a metal heat conduction layer on the inner wall of at least one part of the guide hole, wherein the metal heat conduction layer surrounds the second cavity.
S34: and filling the second cavity with a metal heat conduction material.
In the present embodiment, steps S31-S32 are the same as steps S11-S12 in the above embodiment, and for details, refer to the above embodiment and are not repeated herein.
Wherein the metal heat conducting material is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and combinations thereof.
Specifically, the heat conductive layer may be formed on at least a portion of the inner wall of the via hole by a thermal melting process, an electroplating process, or a deposition process. For example, a metal heat conduction layer may be formed on the hole wall of the via hole by electroless plating, and the formation process of the metal heat conduction layer is a hole metallization process. The metal heat conduction layer completely covers the inner wall of the guide hole and encloses a first cavity which can be used for filling the metal heat conduction material.
For a detailed description of the chip substrate in the above method for manufacturing a chip substrate, please refer to the above chip substrate portion, which is not described herein.
Referring to fig. 8, fig. 8 is a schematic flowchart illustrating an embodiment of a chip packaging method according to the present application. The packaging method comprises the following steps:
s41: a chip substrate is provided.
S42: at least one groove is formed on the chip substrate.
Specifically, at least one groove is formed in the chip substrate to be embedded, and the groove may be formed in the chip substrate by depth control milling, or by etching and laser ablation, which is not limited herein. A groove is formed on the chip substrate so as to embed the subsequent chip. The recess has a certain depth, and in this embodiment, the size of the recess is determined according to the size of the chip to be embedded.
S43: and fixing the bare chip in the groove.
Specifically, the bare chip may be secured within the recess using glue. The bare chip is embedded in the groove, and the adhesive can be chip-attaching resin or silver-based resin or other non-conductive adhesive capable of fixing the chip in the groove, so that the chip is fixed in the groove.
S44: a plurality of guide holes are formed on the chip substrate and distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes.
S45: and forming a metal conductive layer in at least one part of the rectangular guide hole, and electrically connecting the bare chip and the metal conductive layer.
Specifically, a chip substrate provided with a bare chip is covered with an insulating resin laminated plate on one surface close to the chip and then is subjected to vacuum hot pressing, finally, a blind hole is laser-drilled aiming at a metal bonding pad (namely an electrode of the chip, the thickness of the electrode is generally 0.3-0.5 μm) on the surface of the bare chip, and then a conductive medium (such as a copper electrode) is formed through the blind hole by electroplating so as to realize the electrical connection between the chip and an external circuit.
The guide holes are rectangular guide holes which are distributed on the chip substrate in a rectangular array. The rectangular guide hole 11 has a side between 0.3mm and 1mm, for example 0.3mm, 0.5mm, 0.7mm, 0.9mm or 1.0 mm. Preferably, the rectangular guide hole 11 has a side of 0.5 mm. The hole center distance between two adjacent rectangular guide holes 11 is between 0.1mm and 0.5mm, such as 0.1mm, 0.2mm, 0.3mm, 0.4mm or 0.5 mm.
Further, the bare chip includes a plurality of leads, and in step S45, the leads may be connected to the metal conductive layer through a conductive paste.
It should be noted that, for a detailed description of the chip in the above chip packaging method, please refer to the above chip packaging portion, which is not described herein again.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.
Claims (19)
1. The chip substrate is characterized in that a plurality of guide holes are formed in the chip substrate, wherein the guide holes are rectangular guide holes, and the rectangular guide holes are distributed on the chip substrate in a rectangular array.
2. The chip substrate according to claim 1, wherein the rectangular via has a side between 0.3mm and 1 mm.
3. The chip substrate according to claim 2, wherein the rectangular via has a side of 0.5 mm.
4. The chip substrate according to claim 2, wherein the hole center distance between two adjacent rectangular vias is between 0.1mm and 0.5 mm.
5. The chip substrate according to claim 1, wherein at least a portion of the inner walls of the rectangular vias are provided with a metal conductive layer, and the metal conductive layer encloses a first cavity.
6. The chip substrate according to claim 5, wherein the first cavity is filled with a metal conductive material selected from the group consisting of copper, tin, silver, platinum, gold, and combinations thereof.
7. The chip substrate according to claim 1, wherein at least a portion of the inner walls of the rectangular vias are provided with a metal heat conducting layer, and the metal heat conducting layer encloses the second cavity.
8. The chip substrate according to claim 7, wherein the second cavity is filled with a metal heat conductive material selected from the group consisting of copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene, and combinations thereof.
9. The chip substrate according to claim 1, wherein the substrate is at least one of a composite metal substrate and a plastic substrate.
10. A packaged chip, comprising: a bare chip and a chip substrate according to any one of claims 1 to 9;
the chip substrate is provided with at least one groove, the bare chip is fixed in the groove, and the bare chip is electrically connected with the chip substrate.
11. The packaged chip of claim 10, wherein the bare chip comprises a plurality of leads, and the leads are connected to the metal conductive layer or the metal heat conductive layer in the vias on the chip substrate by a conductive adhesive.
12. The packaged chip of claim 10, wherein the packaged chip has a power density of up to 350W/cm2The above or/and hot spot reaches 10KW/cm2The above chip.
13. A method for manufacturing a chip substrate, the method comprising:
providing a chip substrate;
and forming a plurality of guide holes on the chip substrate, and enabling the guide holes to be distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes.
14. The method of claim 13, wherein in the step of forming the plurality of vias on the chip substrate, the sides of the rectangular vias are between 0.3mm and 1 mm.
15. The method of claim 13, wherein in the step of forming the plurality of vias on the chip substrate, the sides of the rectangular vias are made 0.5 mm.
16. The method of manufacturing of claim 13, further comprising:
forming a metal conducting layer on the inner wall of at least one part of the rectangular guide hole, wherein the metal conducting layer surrounds a first cavity;
and filling a metal conductive material in the first cavity, wherein the metal conductive material is selected from copper, tin, silver, platinum, gold and a combination thereof.
17. The method of manufacturing of claim 13, further comprising:
forming a metal heat conduction layer on the inner wall of at least one part of the rectangular guide hole, wherein the metal heat conduction layer surrounds a second cavity;
and filling a metal heat conduction material in the second cavity, wherein the metal heat conduction material is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and a combination thereof.
18. A method for packaging a chip, the method comprising:
providing a chip substrate;
forming at least one groove on the chip substrate;
fixing a bare chip in the groove;
forming a plurality of guide holes on the chip substrate, and enabling the guide holes to be distributed on the chip substrate in a rectangular array, wherein the guide holes are rectangular guide holes;
and forming a metal conductive layer in at least one part of the rectangular guide hole, and electrically connecting the bare chip with the metal conductive layer.
19. The method of packaging of claim 18, wherein the die comprises a plurality of pins;
and in the step of forming a metal conductive layer in at least part of the guide hole and electrically connecting the bare chip and the metal conductive layer, the pin is connected with the metal conductive layer through a conductive adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811572176.9A CN111354684A (en) | 2018-12-21 | 2018-12-21 | Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811572176.9A CN111354684A (en) | 2018-12-21 | 2018-12-21 | Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof |
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| CN111354684A true CN111354684A (en) | 2020-06-30 |
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| CN201811572176.9A Pending CN111354684A (en) | 2018-12-21 | 2018-12-21 | Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112897451A (en) * | 2021-01-19 | 2021-06-04 | 潍坊歌尔微电子有限公司 | Sensor packaging structure, manufacturing method thereof and electronic equipment |
| CN114242798A (en) * | 2021-12-10 | 2022-03-25 | 湖南科莱特光电有限公司 | Frame structure and infrared detector |
-
2018
- 2018-12-21 CN CN201811572176.9A patent/CN111354684A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112897451A (en) * | 2021-01-19 | 2021-06-04 | 潍坊歌尔微电子有限公司 | Sensor packaging structure, manufacturing method thereof and electronic equipment |
| CN112897451B (en) * | 2021-01-19 | 2023-12-22 | 潍坊歌尔微电子有限公司 | Sensor packaging structure, manufacturing method thereof and electronic equipment |
| CN114242798A (en) * | 2021-12-10 | 2022-03-25 | 湖南科莱特光电有限公司 | Frame structure and infrared detector |
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