CN209571412U - A kind of multi-chip package transistor - Google Patents
A kind of multi-chip package transistor Download PDFInfo
- Publication number
- CN209571412U CN209571412U CN201920635406.5U CN201920635406U CN209571412U CN 209571412 U CN209571412 U CN 209571412U CN 201920635406 U CN201920635406 U CN 201920635406U CN 209571412 U CN209571412 U CN 209571412U
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- CN
- China
- Prior art keywords
- chip
- transistor
- pole
- pins
- pin
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A kind of multi-chip package transistor disclosed by the utility model, including several first pins and several second pins and a chip, it is etched at least more than two transistor units on the chip, each transistor unit has the first pole and the second pole, and the first pole of all transistor units is etched on the first face of the chip；Second pole of all transistor units is etched on the second face of the chip, one end of every one first pin and the first pole of a transistor unit are welded to connect, second pole of one end of each second pin and a transistor unit is welded to connect, one end of several first pins, chip, several second pins one end be all encapsulated by insulation colloid.For the utility model compared with existing dual chip is superimposed diode, thickness is thinner.And do not have to superposition during the preparation process, and the first pin and second pin can be struck out to frame structure, it realizes continuous production, improves production efficiency.
Description
Technical field
The utility model relates to transistor encapsulation technology field, in particular to a kind of multi-chip package transistor.
Background technique
Current transistor is typically all single die package, and performance and power are lower, is reached in some specific occasions
Less than requirement.For this purpose, applicant discloses a kind of dual chip superposition diode on June 29th, 2017, Fig. 1 is participated in figure
4, including the first bronze medal frame 1, the second bronze medal frame 2, third copper frame 3 and two chips 4,5, the first bronze medal frame 1, the second bronze medal frame
Between 2 be equipped with chip 4, between the second bronze medal frame 2 and third copper frame between be equipped with chip 5,4, the first bronze medal frame 1, the second bronze medal
Frame 2, third copper frame 3 and two chips 4,5 are successively close together, and chip 4,5 be encapsulated in protecting crust 6 it
Interior, two chips 4,5 of superposition can promote the function of diode, and performance is greatly improved.But such dual chip is folded
Adding diode to have a problem that is exactly that thickness is thicker, is not used in some thin type products.And this dual chip superposition two
Upper and lower chip superposition alignment is relatively difficult during the preparation process for pole pipe, also more troublesome, needs to take a long time to pair
Together.
Utility model content
Technical problem to be solved in the utility model is thicker for existing dual chip superposition diode thickness
Problem and provide a kind of thickness than relatively thin multi-chip package transistor.
Technical problem to be solved in the utility model can be achieved through the following technical solutions:
A kind of multi-chip package transistor.Including several first pins and several second pins and a chip, feature
Be, be etched at least more than two transistor units on the chip, each transistor unit have the first pole and
First pole of the second pole, all transistor units is etched on the first face of the chip；Second pole of all transistor units
It is etched on the second face of the chip, one end of every one first pin and the first pole of a transistor unit are welded to connect, often
One end of one second pin and the second pole of a transistor unit are welded to connect, one end of several first pins, chip, Ruo Gan
One end of two pins is all encapsulated by insulation colloid.
In a preferred embodiment of the utility model, the other end of the first all pins is electrically connected to each other.
In a preferred embodiment of the utility model, the other ends of all first pins and all second pins
The other end is bent to insulation colloid direction and is attached in the one side of the insulation colloid.
Due to using technical solution as above, the utility model is compared with existing dual chip is superimposed diode, thickness
It is thinner.And do not have to superposition during the preparation process, and the first pin and second pin can be struck out frame structure, it is real
Existing continuous production, improves production efficiency.
Detailed description of the invention
Fig. 1 is that existing dual chip is superimposed diode from the perspective view in terms of first direction.
Fig. 2 is that existing dual chip is superimposed diode from the perspective view in terms of second direction.
Fig. 3 is that existing dual chip is superimposed diode from the perspective view in terms of third direction.
Fig. 4 is that existing dual chip is superimposed diode from the perspective view in terms of fourth direction.
Fig. 5 is the utility model multi-chip package transistor from the perspective view in terms of second direction.
Fig. 6 is the utility model multi-chip package transistor from the perspective view in terms of second direction.
Fig. 7 is the utility model multi-chip package transistor from the perspective view in terms of third direction.
Fig. 8 is the utility model multi-chip package transistor from the perspective view in terms of fourth direction.
Fig. 9 is that the welding solid of the first pin, second pin and chip in the utility model multi-chip package transistor is shown
It is intended to.
Figure 10 is that the welding of the first pin, second pin and chip in the utility model multi-chip package transistor is overlooked
Figure.
Figure 11 is that the welding of the first pin, second pin and chip in the utility model multi-chip package transistor is faced
Figure.
Figure 12 is the left view of Figure 11.
Specific embodiment
The chip of the pair transistor provided below in conjunction with the drawings and specific embodiments further describes the utility model.
Referring to Fig. 5 to Fig. 8, a kind of multi-chip package transistor shown in figure.Including several first pins 100 and several
Second pin 200 and a chip 300.
There are two transistor units 310,320 for etching on chip 300, naturally it is also possible to etch on chip 300 more
A transistor unit.Two transistor units 310,320 all have the first pole 311,312,321,322, constitute a triode.
First pole 311,321 of two transistors 310,320 is etched on the first face 301 of chip 300, two transistors 310,320
The second pole be etched on the second face 302 of chip 300.
In conjunction with referring to Fig. 9 to Figure 12, in the preparation, the one of 300 corresponding two the first pins 100 of every group of chip, 100a
End 101,101a are electrically connected by a connection copper sheet 120, to form the base stage of triode.All connection copper sheets 120 are equal
As soon as being connected by copper bound item 130, the first all in this way pins 100,100a can form a bronze medal frame knot before welding
Structure is convenient for punch forming.
In the preparation, several second pins 200,200a one end 201a pass through one side copper bound item 210 and connect, this
All second pins 200 of sample can form a bronze medal frame structure before welding, be convenient for punch forming.
When welding, the first pole 311,321 of two transistor units 310,320 in every group of chip 300 is buckled in every group
On the other ends 102 of 300 corresponding two the first pins 100 of chip, 102a, then by every group chip 300 corresponding two
Two pins 200,200a the other end 202,202a be overlapped on of two transistor units 310,320 in every group of chip 300
On two poles 312,322.After chip 300 and the first pin 100, second pin 200 assemble, it is sent into soldering furnace welding, most
Make the another of the first pole 311,321 of two transistor units 310,320 in every group of chip 300 and two the first pins 100 eventually
One end 102,102a welding, the second pole 312,322 of two transistor units 310,320 in every group of chip 300 and two the
The other end 202 of two pins 200,202a welding.After welding is completed, places into and be molded insulating cement in encapsulating mould, it will be several
One end 101 of first pin 100,101a, chip 300, one end 210 of several second pins 200,201a are all by insulation colloid
400 are encapsulated.After packaged, copper bound item 130 and copper bound item 210 are cut, multi-chip package one by one can be formed
Transistor.
In addition to accurately chip 300 and the first pin 100, second pin 200 are assembled, in copper bound item 130 and copper
Edge strip 210, which fills, is formed with some location holes 131,211.
By the other end 102 of all first pins 100, the other end 202, the 202a of 102a and all second pins 200
It is bent and is attached in the one side 410 of insulation colloid 400 to insulation 400 direction of colloid, form patch type multi-chip package crystal
Pipe.
Claims (3)
1. a kind of multi-chip package transistor, including several first pins and several second pins and a chip, feature exist
In being etched at least more than two transistor units on the chip, each transistor unit has the first pole and the
First pole of two poles, all transistor units is etched on the first face of the chip；It loses second pole of all transistor units
It is engraved on the second face of the chip, one end of every one first pin and the first pole of a transistor unit are welded to connect, each
One end of second pin and the second pole of a transistor unit are welded to connect, one end of several first pins, chip, several second
One end of pin is all encapsulated by insulation colloid.
2. a kind of multi-chip package transistor as described in claim 1, which is characterized in that the other end of the first all pins
It is electrically connected to each other.
3. a kind of multi-chip package transistor as described in claim 1, which is characterized in that the other end of all first pins and
The other end of all second pins is bent to insulation colloid direction and is attached in the one side of the insulation colloid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920635406.5U CN209571412U (en) | 2019-05-06 | 2019-05-06 | A kind of multi-chip package transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920635406.5U CN209571412U (en) | 2019-05-06 | 2019-05-06 | A kind of multi-chip package transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209571412U true CN209571412U (en) | 2019-11-01 |
Family
ID=68336267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920635406.5U Active CN209571412U (en) | 2019-05-06 | 2019-05-06 | A kind of multi-chip package transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209571412U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034087A (en) * | 2019-05-06 | 2019-07-19 | 上海金克半导体设备有限公司 | A kind of multi-chip package transistor |
-
2019
- 2019-05-06 CN CN201920635406.5U patent/CN209571412U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034087A (en) * | 2019-05-06 | 2019-07-19 | 上海金克半导体设备有限公司 | A kind of multi-chip package transistor |
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