CN209516943U - A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC - Google Patents
A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC Download PDFInfo
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- CN209516943U CN209516943U CN201920407595.0U CN201920407595U CN209516943U CN 209516943 U CN209516943 U CN 209516943U CN 201920407595 U CN201920407595 U CN 201920407595U CN 209516943 U CN209516943 U CN 209516943U
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Abstract
Disclosed by the utility model is a kind of circuit system of anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC, DCDC control circuit includes output pin LX and at least two branches, delay driving circuit includes output port, output port, two branches of DCDC control circuit are separately connected delay driving circuit, it is depressured driving circuit, the output port of decompression driving circuit output port and delay driving circuit is connected with series connection of power tubes circuit respectively, the output port of delay driving circuit is connected with NMOS power tube, series connection of power tubes circuit, NMOS power tube is connected with the output pin LX of DCDC control circuit, NMOS power tube and all circuits have one end ground connection, synchronous commutation type DCDC can be integrated in the SOC of the even lower dimension process of 55nm by the utility model , improve the integrated level of SOC chip；Will not over-voltage breakdown cause yield to reduce；Woth no need to external DCDC, development cost is low.
Description
Technical field
The present invention relates to a kind of circuit systems of anti-over-voltage breakdown, more specifically say, are related to a kind of chip embedded same
The circuit system of the step rectification anti-over-voltage breakdown of DCDC, belongs to electric time-keeping field.
Background technique
The existing embedded DCDC switching power circuit of SOC, for using 55nm even smaller szie advanced technologies
When SOC, DCDC operating voltage reach technique maximum, hit since the switch overshoot of DCDC causes process devices to be easy to over-voltage
It wears, so that DCDC is difficult to be integrated into a SOC chip, and the scheme for solving DCDC switch overshoot breakdown device existing at present is big
Design cost is increased greatly, while limiting the flexibility of design.The design technology of specific CPU at present is generally 90nm, very
To using the lower thread technique of 55nm or 28nm, the voltage which requires is universal lower not higher than 3.3v, due to thin grid oxygen
Device voltage endurance capability is limited, and most of process devices meeting more than 3.3v because puncture, and the peculiar switching pulse of synchronous DC/DC
1V is often exceeded, therefore this synchronous rectification DC/DC is almost impossible is integrated into cpu chip.
The reason that synchronous rectification DC/DC is not integrated into ultralow thread technique is the following: 1, the work of low thread
Skill, grid oxygen is thin, and channel length is short, therefore the highest pressure resistance of technique is usually less than 3.3v, and slightly over-voltage can all lead to internal components
Breakdown is burnt；2, for save the cost, the power management of CPU associated circuit board generallys use DCDC, 3.3v turns that 12v turns 3.3v
It is other module for power supply that 1.2 DCDC and 3.3v, which turns the LDO such as 1.8/2.8, therefore, if the 3.3v DCDC for turning 1.2v integrated
Into SOC, which also must achieve the purpose that in this way save the cost, but the power supply of DCDC is defeated using 3.3v as input
Enter just to reach the maximum of technique requirement；3, in order to save product cost and increase power-efficient, usual DCDC can be using same
Rectification type DCDC is walked, however the distinctive switching pulse of synchronous commutation type DCDC can be more than supply voltage 1v or more.Due to above-mentioned original
Cause, it is distinctive when synchronous commutation type DCDC is integrated into low thread technique, and input voltage reaches technique ceiling voltage 3.3v
DCDC switching pulse will lead to device and generate avalanche breakdown, to damage chip, chip failure caused by DCDC substantially reduces whole
The yields of a chip, to greatly increase the cost of chip finished product.In addition to this, hot carrier's effect caused by over-voltage also can
Substantially reduce the service life of chip.
In existing chip design, technique thread is being determined, when determining operating voltage, the scheme of current embedded DCDC is such as
Under:
1, power supply using diode decompression as chip input, the program reduce chip voltage, therefore reduce breakdown can
It can property；
2, improve gate oxide thickness, reduce the source and drain and injection doping of mos device, process devices can be improved in this way
Pressure resistance；
3, the embodiment for turning 1.2v as the 3.3v of chip using LDO does not switch arteries and veins since LDO work is static state
It breaks through, not will lead to device failure, the program is also frequently utilized in low thread chip；
4, using asynchronous DCDC, external freewheeling diode, the program can substantially reduce the amplitude of switching pulse, but still
The presence of over-voltage phenomenon is so had, but the probability of chip breakdown can be substantially reduced.
Above method or efficiency is reduced, increases and product development is difficult to realize or increased in power consumption or technique
Cost.Therefore it needs to design a kind of method when embedded DCDC operating voltage reaches technique maximum, both guarantees circuit device
The safety of part, high yield, and do not increase development cost.
Utility model content
The present invention is in view of the above problems, provide a kind of circuit system of anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC
System, it is therefore an objective to overcome the problems, such as that small size technique SOC existing in the prior art inexpensive can not be compatible with DCDC, having can prevent
Synchronous commutation type DCDC works under mos device voltage rating leads to over-voltage breakdown, and SOC integrated level can be improved and SOC power supply is simultaneous
Content reduces product development cost, improves the technical characterstics such as chip whole competitiveness.
To achieve the goals above, the technical solution adopted by the present invention is that:
A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC, including DCDC control circuit, delay
Driving circuit, decompression driving circuit, series connection of power tubes circuit and NMOS power tube, the DCDC control circuit includes output pin
LX and at least two branches, delay driving circuit include output port, output port, two branch of the DCDC control circuit
Road is separately connected delay driving circuit, decompression driving circuit, the decompression driving circuit output port and delay driving circuit
Output port is connected with series connection of power tubes circuit respectively, and the output port of the delay driving circuit is connected with NMOS power tube,
The series connection of power tubes circuit, NMOS power tube are connected with the output pin LX of DCDC control circuit, NMOS power tube and institute
Having circuit has one end ground connection.
As an improvement the series connection of power tubes circuit includes power tube, power tube, the power tube and power tube string
Connection, the power tube are parallel with resistance, and power tube is parallel with resistance, and the output port of the delay driving circuit connects power tube
Grid, it is described decompression driving circuit output port be connected with the grid of power tube, the delay driving circuit output port
It is connected with the grid of NMOS power tube, the source electrode of the power tube, the anode of resistance are respectively connected with 3.3V power supply, the leakage of power tube
Pole, the negative terminal of resistance, power tube source electrode be connected with the anode of resistance；The drain electrode of power tube, the negative terminal of resistance, NMOS power
The drain electrode of pipe is connected with the output pin LX of DCDC control circuit, the source electrode ground connection of NMOS power tube.
As an improvement delay adjustment mechanism is provided in the delay driving circuit, in the decompression driving circuit
It is provided with reduction regulation mechanism.
As an improvement the DCDC control circuit, delay driving circuit, decompression driving circuit, series connection of power tubes electricity
Road and NMOS power tube are integrated in inside System on Chip/SoC.
The beneficial effects of the present invention are: compared with prior art, having following advantages:
1, synchronous commutation type DCDC can be integrated in the SOC of the even lower dimension process of 55nm, improve the collection of SOC chip
Cheng Du；
2, synchronous commutation type DCDC may operate in the maximum rated voltage that low thread technique requires, and will not be because of DCDC
Switching pulse over-voltage breakdown causes yield to reduce, to improve entire product-level power compatibility；
3, external DCDC is not needed, to reduce entire product-level development cost.
Detailed description of the invention
Fig. 1 is the system structure diagram of this utility model.
Specific embodiment
Below in conjunction with attached drawing, the present invention is described in detail with specific embodiment, but should not be understood as to the application
Limitation.
System on Chip/SoC often uses 3.3v 90nm and process below, and power management scheme requires a DCDC reality
Existing 12v turns 3.3v, and the synchronous rectification DC/DC an of low-cost high-efficiency is needed to realize that 3.3v turns 1.2v, needs to turn 3.3v at present
The synchronous DC/DC of 1.2v is integrated into the technique, input voltage 3.3v, reaches the maximum rated voltage of technique requirement, due to same
The distinctive switching pulse of DCDC is walked, leads to power tube over-voltage, so that chip is damaged, so needing to provide a kind of electricity solved the problems, such as
Road system.
It is as shown in Figure 1 a kind of specific implementation of the circuit system of chip embedded anti-over-voltage breakdown of synchronous rectification DC/DC
Example, a kind of circuit system of the chip embedded anti-over-voltage breakdown of synchronous rectification DC/DC of the embodiment, including DCDC control circuit 1,
Delay driving circuit 2, decompression driving circuit 3, series connection of power tubes circuit 4 and NMOS power tube N1, the DCDC control circuit 1 are wrapped
Output pin LX and at least two branches are included, delay driving circuit 2 includes output port D1, output port D2, the DCDC
Two branches of control circuit 1 are separately connected delay driving circuit 2, decompression driving circuit 3, and the decompression driving circuit 3 exports
The output port D1 of port D3 and delay driving circuit is connected with series connection of power tubes circuit 4 respectively, the delay driving circuit 2
Output port D2 is connected with NMOS power tube N1, the series connection of power tubes circuit 4, NMOS power tube N1 with DCDC control circuit
1 output pin LX is connected, and NMOS power tube N1 and all circuits have one end ground connection, and the series connection of power tubes circuit 4 includes
Power tube P1, power tube P2, the power tube P1 connect with power tube P2, and the power tube P1 is parallel with resistance R1, power tube
P2 is parallel with resistance R2, the grid P1_G of the output port D1 connection power tube P1 of the delay driving circuit, and the decompression is driven
The grid P2_G of the output port D3 and power tube P2 of dynamic circuit are connected, the delay driving circuit output port D2 and NMOS function
The grid N1_G of rate pipe N1 is connected, and the source electrode P1_S of the power tube P1, the anode R1_P of resistance R1 are respectively connected with 3.3V power supply,
Power tube P1 drain electrode P1_D, the negative terminal R1_N of resistance R1, power tube P2 source electrode P2_S with the anode R2_P phase of resistance R2
Even；Power tube P2 drain electrode P2_D, resistance R2 negative terminal R2_N, NMOS power tube N1 drain electrode N1_D with the efferent duct of DCDC
Foot LX is connected, and the source electrode N1_S of NMOS power tube is grounded VSS.
The utility model delay driving circuit 2 and decompression driving circuit 3 cooperate, and pass through series connection of power tubes circuit 4
In two power tubes P1, P2 and two resistance series connection R1, R2 partial pressure, guarantee that power tube P1 and power tube P2 switchs wink in DCDC
Between do not exceed pressure voltage, thus prevent power tube P1, power tube P2 bear be more than 3.3v pulse voltage and damage, work as delay
When output port D1, D2 of driving circuit 2 and the output port D3 for being depressured driving circuit are low level, power tube P1 and power tube
P2 conducting, NMOS power tube N1 are closed, and the output pin LX output of DCDC control circuit is height；When switching process, when prolonging
When driving circuit output port D2 be it is low, the output port D1 of delay driving circuit is height, is depressured the output end of driving circuit
When mouth D3 is low, power tube P1 is closed, and power tube P2 is still connected, and NMOS power tube N1 is closed, DCDC control circuit
Output pin LX no current is released, and due to inductive effect, the output pin LX of DCDC control circuit will occur being lower than the pulse of 0v,
Even it is reduced to -1v；The rational design of delay driving circuit 2, so that the output pin LX of DCDC control circuit is being down to 0 mistake
Cheng Zhong, certain time-delay just will appear the output port D3 of decompression driving circuit after the output port D1 of delay driving circuit is got higher
Get higher, be then depressured driving circuit output port D3 become height during so that the source S of P2 is also gradually increased,
So that the source-drain voltage of P2 is not higher than 3.3v, and the source-drain voltage of P1 is not also high during LX becomes the switching pulse of -1v
In 3.3v, simultaneously because the rational design of decompression driving circuit, when so that D3 becomes high, the high level of D3 is lower than 3.3v,
So that the voltage between the grid P2_G and drain electrode P2_D of power tube P2 is below 3.3v；When the output port of delay driving circuit
After D1, D2 and the output port D3 for being depressured driving circuit become height, power tube P1 and power tube P2 are closed, NMOS power tube
N1 conducting, the voltage of the output pin LX of DCDC control circuit are down near 0v, since resistance R1 and resistance R2 series connection partial pressure is led
It causes between the source electrode P2_S of the voltage between the source electrode P1_S of power tube P1 and drain electrode P1_D and power tube P2 and drain electrode P2_D
Voltage is no more than 3.3v, so that power tube P1, power tube P2 be in entire handoff procedure, not over-voltage.
It is provided with delay adjustment mechanism in the delay driving circuit 2, decompression is provided in the decompression driving circuit 3 and is adjusted
Mechanism is saved, by the synergistic effect of delay driving circuit 2, decompression driving circuit 3 and series connection of power tubes circuit 3, so that power tube
P1 and power tube P2 during completing entire switching cycle, source electrode, drain and gate voltage between any two be below
3.3v.If the series connection of synergistic effect and P2 pipe without this three's circuit, power tube P1 switched alone bear
The output pin LX of DCDC control circuit becomes 0v even all voltages of -1v pulse in journey, and it has been more than 3.3v that this, which is crossed and is pressed in instantaneously,
Even up to 4.3v, so as to cause over-voltage breakdown, the DCDC control circuit 1, delay driving circuit 2, decompression driving circuit 3,
Series connection of power tubes circuit 4 and NMOS power tube N1 are integrated in inside System on Chip/SoC.
The utility model can integrate synchronous rectification DC/DC in the SOC of the even lower thread technique of 90nm, improve
Integrated level, can also safety work in the maximum permissible voltage of chip, improve yield, while also ensuring synchronous rectification
The performances such as the high efficiency low ripple of type DCDC, allow DCDC normally to play a role, and drop significantly from field of power management in this way
The low development cost of the even lower thread technique SOC of 90nm.
Finally it should be noted that the utility model is not limited to above embodiments, can also there are many variations, this field
All deformations that technical staff directly can export or associate from the utility model disclosure, are considered as guarantor of the invention
Protect range.
Claims (4)
1. a kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC, including DCDC control circuit (1), delay
Driving circuit (2), decompression driving circuit (3), series connection of power tubes circuit (4) and NMOS power tube (N1), it is characterised in that: described
DCDC control circuit (1) includes output pin LX and at least two branches, and delay driving circuit (2) includes output port
(D1), output port (D2), two branches of the DCDC control circuit (1) are separately connected delay driving circuit (2), decompression is driven
The output port (D1) of dynamic circuit (3), decompression driving circuit (3) output port and delay driving circuit respectively with power tube
Series circuit (4) is connected, and the output port (D2) of the delay driving circuit (2) is connected with NMOS power tube (N1), the function
Rate pipe series circuit (4), NMOS power tube (N1) are connected with the output pin LX of DCDC control circuit (1), NMOS power tube
(N1) there is one end ground connection with all circuits.
2. a kind of circuit system of chip embedded anti-over-voltage breakdown of synchronous rectification DC/DC according to claim 1, special
Sign is: the series connection of power tubes circuit (4) includes power tube (P1), power tube (P2), the power tube (P1) and power tube
(P2) it connects, the power tube (P1) is parallel with resistance (R1), and power tube (P2) is parallel with resistance (R2), the delay and running electricity
The grid of output port (D1) connection power tube (P1) on road, the output port and power tube (P2) of the decompression driving circuit
Grid is connected, and the delay driving circuit output port (D2) is connected with the grid of NMOS power tube (N1), the power tube
(P1) anode of source electrode, resistance (R1) is respectively connected with 3.3V power supply, the drain electrode of power tube (P1), resistance (R1) negative terminal, function
The source electrode of rate pipe (P2) is connected with the anode of resistance (R2), the drain electrode of power tube (P2), the negative terminal of resistance (R2), NMOS power
The drain electrode of pipe (N1) is connected with the output pin LX of DCDC, the source electrode ground connection of NMOS power tube.
3. a kind of circuit system of chip embedded anti-over-voltage breakdown of synchronous rectification DC/DC according to claim 1 or 2,
It is characterized in that: being provided with delay adjustment mechanism in the delay driving circuit (2), be provided in the decompression driving circuit (3)
Reduction regulation mechanism.
4. a kind of circuit system of chip embedded anti-over-voltage breakdown of synchronous rectification DC/DC according to claim 1, special
Sign is: the DCDC control circuit (1), delay driving circuit (2), decompression driving circuit (3), series connection of power tubes circuit (4)
It is integrated in inside System on Chip/SoC with NMOS power tube (N1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920407595.0U CN209516943U (en) | 2019-03-28 | 2019-03-28 | A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920407595.0U CN209516943U (en) | 2019-03-28 | 2019-03-28 | A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC |
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| Publication Number | Publication Date |
|---|---|
| CN209516943U true CN209516943U (en) | 2019-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920407595.0U Withdrawn - After Issue CN209516943U (en) | 2019-03-28 | 2019-03-28 | A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC |
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| CN (1) | CN209516943U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109861535A (en) * | 2019-03-28 | 2019-06-07 | 杭州雄迈集成电路技术有限公司 | A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC |
-
2019
- 2019-03-28 CN CN201920407595.0U patent/CN209516943U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109861535A (en) * | 2019-03-28 | 2019-06-07 | 杭州雄迈集成电路技术有限公司 | A kind of circuit system of the anti-over-voltage breakdown of chip embedded synchronous rectification DC/DC |
| CN109861535B (en) * | 2019-03-28 | 2023-08-25 | 杭州雄迈集成电路技术股份有限公司 | Circuit system for preventing overvoltage breakdown of chip embedded synchronous rectification DCDC |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 311400 4th floor, building 9, Yinhu innovation center, No. 9, Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee after: Hangzhou xiongmai integrated circuit technology Co.,Ltd. Address before: 311422 four floor, 9 floor, Silver Lake innovation centre, 9 Fu Fu Road, Fuyang Lake District, Hangzhou, Zhejiang. Patentee before: HANGZHOU XIONGMAI INTEGRATED CIRCUIT TECHNOLOGY Co.,Ltd. |
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| CP03 | Change of name, title or address | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20191018 Effective date of abandoning: 20230825 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20191018 Effective date of abandoning: 20230825 |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |