CN209496872U - A kind of memory - Google Patents
A kind of memory Download PDFInfo
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- CN209496872U CN209496872U CN201920515020.0U CN201920515020U CN209496872U CN 209496872 U CN209496872 U CN 209496872U CN 201920515020 U CN201920515020 U CN 201920515020U CN 209496872 U CN209496872 U CN 209496872U
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- floating gate
- underlay substrate
- groove structure
- active area
- shallow trench
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- 230000015654 memory Effects 0.000 title claims abstract description 44
- 238000007667 floating Methods 0.000 claims abstract description 122
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 238000000926 separation method Methods 0.000 claims abstract description 42
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 238000005265 energy consumption Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 238000000034 method Methods 0.000 description 15
- 238000002360 preparation method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The utility model discloses a kind of memories, comprising: underlay substrate, underlay substrate include multiple active areas and multiple shallow trench isolation regions, and active area and shallow trench isolation region interval are arranged；Separation layer positioned at the corresponding underlay substrate side in shallow trench isolation region is formed with groove structure in separation layer；The first floating gate positioned at the corresponding underlay substrate side of active area；The second floating gate on the first floating gate and groove structure inner wall surface, the second floating gate are disconnected in the basal surface position of groove structure；Dielectric layer on the second floating gate, dielectric layer cover the separation layer being exposed to outside the second floating gate；Control gate on dielectric layer.Memory provided by the embodiment of the utility model has advantage low in energy consumption.
Description
Technical field
The utility model embodiment is related to technical field of manufacturing semiconductors more particularly to a kind of memory.
Background technique
Traditional flash storage is using self-aligned technology production floating gate (Floating Gate, FG), although technique is simple
Singly and cost is relatively low, but effective contact area of floating gate and control gate (Control Grid, CG) are relatively low, and CG-FG is caused to couple
Capacitor is relatively low, and then causes control gate that higher operation voltage is needed to carry out erasable operation to floating gate, to cause memory
The power consumption of part is higher.
Utility model content
The utility model provides a kind of memory, to increase the contact area of floating gate and control gate, and then reduces memory
Power consumption.
In a first aspect, the utility model embodiment provides a kind of memory, comprising:
Underlay substrate, the underlay substrate include multiple active areas and multiple shallow trench isolation regions, the active area and described
The setting of shallow trench isolation region interval；
Separation layer positioned at the corresponding underlay substrate side in the shallow trench isolation region is formed in the separation layer recessed
Slot structure；
The first floating gate positioned at the corresponding underlay substrate side of the active area；
The second floating gate on first floating gate and the groove structure inner wall surface, second floating gate is described
The basal surface position of groove structure disconnects；
Dielectric layer on second floating gate, dielectric layer covering be exposed to outside second floating gate it is described every
Absciss layer；
Control gate on the dielectric layer.
Optionally, along the direction of the vertical underlay substrate, the upper surface of the corresponding underlay substrate of the active area
Where place plane is located at the bottom surface of the groove structure on plane.
Optionally, along the direction of the vertical underlay substrate, first floating gate with a thickness of D1, wherein 100nm≤D1
≤200nm。
Optionally, along the direction of the vertical underlay substrate, second floating gate with a thickness of D2, wherein 5nm≤D2≤
20nm。
Optionally, the direction of the shallow trench isolation region is directed toward along the active area, the opening width of the groove structure is
D3, wherein 30nm≤D3≤80nm；
Along the direction of the vertical underlay substrate, the opening depth of the groove structure is D4, wherein 50nm≤D4≤
100nm。
Optionally, the direction of the shallow trench isolation region is directed toward along the active area, between two neighboring second floating gate
Distance be L1, wherein L1 >=10nm.
The utility model embodiment is being located at the corresponding substrate base of active area by the way that groove structure is arranged in separation layer
The second floating gate is set on the first floating gate and groove structure inner wall surface of plate side, so that floating gate and the effective of control gate connect
Contacting surface product increases, and then operation voltage needed for reduction control gate, reduces the power consumption of memory.
Detailed description of the invention
Fig. 1 is a kind of existing structural schematic diagram of memory；
Fig. 2 is a kind of structural schematic diagram of memory provided by the embodiment of the utility model；
Fig. 3 is a kind of flow diagram of the preparation method of memory provided by the embodiment of the utility model；
Fig. 4 is the flow diagram of the preparation method of another memory provided by the embodiment of the utility model；
Fig. 5-Figure 13 is the schematic diagram of each step of preparation method of memory provided by the embodiment of the utility model.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawings and examples.It is understood that herein
Described specific embodiment is used only for explaining the utility model, rather than the restriction to the utility model.It further needs exist for
It is bright, part relevant to the utility model is illustrated only for ease of description, in attached drawing rather than entire infrastructure.
Fig. 1 is a kind of existing structural schematic diagram of memory.Referring to Fig. 1, which includes: underlay substrate 11, lining
Substrate 11 includes multiple active areas 110 and multiple shallow trench isolation regions 111, and active area 110 and the interval of shallow trench isolation region 111 are set
It sets.Memory further includes the separation layer 12 for filling shallow trench isolation region 111, the floating gate 13 on active area 110, is located at table on floating gate 13
The dielectric layer 14 and the control gate 15 on dielectric layer 14 of 12 upper surface of face and separation layer.
As described in background, the floating gate 13 of the memory and effective contact area of control gate 15 are relatively low, lead to CG-
FG coupled capacitor is relatively low, and then causes control gate 15 that higher operation voltage is needed to carry out erasable operation to floating gate 13, thus
Cause the power consumption of memory device higher.
Based on this, the utility model embodiment provides a kind of memory, including underlay substrate, and underlay substrate includes multiple having
Source region and multiple shallow trench isolation regions, active area and the setting of shallow trench isolation region interval；Positioned at the corresponding underlay substrate in shallow trench isolation region
The separation layer of side is formed with groove structure in separation layer；The first floating gate positioned at the corresponding underlay substrate side of active area；Position
In the second floating gate on the first floating gate and groove structure inner wall surface, the second floating gate is disconnected in the basal surface position of groove structure to be connected
It connects；Dielectric layer on the second floating gate, dielectric layer cover the separation layer being exposed to outside the second floating gate；Control on dielectric layer
Grid processed.By adopting the above technical scheme, groove structure is set in separation layer, and is being located at the corresponding underlay substrate side of active area
The first floating gate and groove structure inner wall surface on the second floating gate is set so that effective contact area of floating gate and control gate
Increase, and then operation voltage needed for reduction control gate, reduces the power consumption of memory.
It is the core concept of the utility model above, the following will be combined with the drawings in the embodiments of the present invention, to this reality
It is clearly and completely described with the technical solution in new embodiment.Based on the embodiments of the present invention, this field is general
Without making creative work, every other embodiment obtained belongs to the utility model to logical technical staff
The range of protection.
Fig. 2 is a kind of structural schematic diagram of memory provided by the embodiment of the utility model, as shown in Fig. 2, this is practical new
The memory that type embodiment provides includes: underlay substrate 11, and underlay substrate 11 includes multiple active areas 110 and multiple shallow-trench isolations
Area 111, active area 110 and the setting of the interval of shallow trench isolation region 111；Positioned at corresponding 11 side of underlay substrate in shallow trench isolation region 111
Separation layer 12, be formed with groove structure 121 in separation layer 12；Positioned at the of corresponding 11 side of underlay substrate of active area 110
One floating gate 131；The second floating gate 132 in 121 inner wall surface of the first floating gate 131 and groove structure, the second floating gate 132 is recessed
The basal surface position of slot structure 121 disconnects；Dielectric layer 14 on the second floating gate 132, dielectric layer covering are exposed to second
Separation layer 12 outside floating gate 132；Control gate 15 on dielectric layer 14.
The utility model embodiment is corresponded to by the way that groove structure 121 is arranged in separation layer 12, and being located at active area 110
11 side of underlay substrate 121 inner wall surface of the first floating gate 131 and groove structure on the second floating gate 132 is set so that
Effective contact area of floating gate and control gate 15 increases, and then operation voltage needed for reduction control gate 15, reduces memory
Power consumption.
With continued reference to shown in Fig. 2, optionally, along the direction of vertical substrates substrate 11, the corresponding underlay substrate of active area 110
Plane where 11 upper surface is located on the bottom surface place plane of groove structure 121 so that the depth of groove structure 121 compared with
Greatly, to increase effective contact area of the second floating gate 132 and control gate 15.
With continued reference to shown in Fig. 2, optionally, along the direction of vertical substrates substrate 11, the first floating gate 131 with a thickness of D1,
Wherein, the thickness of 100nm≤D1≤200nm, the first floating gate 131 are smaller, and the first floating gate 131 and control gate 15 are in vertical direction
Laminated thickness is smaller, so that subsequent filling insulating medium layer is more easier, to improve the yields of memory, but first is floating
The thickness of grid 131 is too small, then can be easily broken.Therefore the thickness of the first floating gate 131 is rationally arranged in the utility model embodiment, both
It can reduce the first floating gate 131 and control gate 15 laminated thickness in vertical direction, while the first floating gate 131 can also be taken into account
Stability avoids rupturing.
With continued reference to shown in Fig. 2, optionally, along the direction of vertical substrates substrate 11, the second floating gate 132 with a thickness of D2,
Wherein, the thickness of 5nm≤D2≤20nm, the second floating gate 132 are smaller, and the second floating gate 132 and control gate 15 are folded in vertical direction
Thickness degree is smaller, so that subsequent filling insulating medium layer is more easier, to improve the yields of memory, but the second floating gate
132 thickness is too small, then can be easily broken.Therefore the thickness of the second floating gate 132 is rationally arranged in the utility model embodiment, both may be used
To reduce the second floating gate 132 and control gate 15 laminated thickness in vertical direction, while the steady of the second floating gate 132 can also be taken into account
It is qualitative, it avoids rupturing.
With continued reference to shown in Fig. 2, optionally, the direction of shallow trench isolation region 111, groove structure 121 are directed toward along active area 110
Opening width be D3, wherein 30nm≤D3≤80nm；Along the direction of vertical substrates substrate, the opening depth of groove structure 121
For D4, wherein 50nm≤D4≤100nm is open wider, and effective contact area of the second floating gate 132 and control gate 15 is bigger, but
Wide meeting be open so that the side wall of groove structure 121 is excessively thin, is easily broken；It is open deeper, the second floating gate 132 and control gate 15
Effective contact area is bigger, but the too deep meeting that is open is easily broken so that the bottom of groove structure 121 is excessively thin.Therefore this is practical new
The opening width and opening depth of groove structure 121 is rationally arranged in type embodiment, can both increase the second floating gate 132 and control gate
15 effective contact area, while the stability of groove structure 121 can also be taken into account, it avoids rupturing.
With continued reference to shown in Fig. 2, optionally, it is directed toward the direction of shallow trench isolation region 111 along active area 110, two neighboring the
The distance between two floating gates 132 are L1, wherein L1 >=10nm, L1 are smaller, and the second floating gate 132 is effectively contacted with control gate 15
Area is bigger, but L1 is too small, is easy to make the second floating gate 132 corresponding to two neighboring active area 110 to be connected.Therefore this is practical new
The size of the distance between second floating gate 132 L1 corresponding to two neighboring active area 110 is rationally arranged in type embodiment, both can be with
Increase effective contact area of the second floating gate 132 and control gate 15, while can also guarantee that memory works normally.
With continued reference to shown in Fig. 2, optionally, it is provided with and mixes between the underlay substrate 11 of active area 110 and the first floating gate 131
Diamicton 16 and tunneling oxide layer 17, doped layer 16 and tunneling oxide layer 17 can adjust the threshold voltage of storage unit in memory,
To avoid because memory cell size it is too small caused by short-channel effect, improve memory performance.
Optionally, the material of separation layer 12 includes silica material, on the one hand silica plays protection 131 He of the first floating gate
On the other hand the effect of second floating gate 132 avoids storage unit from generating leakage current.
Optionally, dielectric layer 14 includes the stepped construction of silica, silicon nitride and silicon oxide layer, for the second floating gate to be isolated
132 and control gate 15, wherein silicon nitride layer can capture charge to inhibit leakage current, silica, silicon nitride and silicon oxide layer
Stepped construction have higher critical electric field and lower defect concentration.
Optionally, the material of the first floating gate 131, the second floating gate 132 and control gate 15 is polysilicon.
Based on same inventive concept, the utility model embodiment additionally provides a kind of preparation method of memory, is used for
Any memory provided by the above embodiment is prepared, the explanation of same as the previously described embodiments or corresponding structure and term is herein
It repeats no more, Fig. 3 is a kind of flow diagram of the preparation method of memory provided by the embodiment of the utility model, such as Fig. 3 institute
Show, this method comprises the following steps:
Step 210 provides underlay substrate and forms multiple active areas and multiple shallow trench isolation regions on the underlay substrate,
The active area and shallow trench isolation region interval setting.
Step 220 fills separation layer in the shallow trench isolation region.
Step 230 prepares the first floating gate in the corresponding underlay substrate side of the active area.
Step 240 prepares groove structure in the separation layer.
Step 250 prepares the second floating gate on first floating gate and the groove structure inner wall surface, and described second is floating
Grid are disconnected in the basal surface position of the groove structure.
Step 260, the preparation media layer on second floating gate, the dielectric layer covering are exposed to outside second floating gate
The separation layer.
Step 270 prepares control gate on the dielectric layer.
The preparation method of memory provided by the embodiment of the utility model by preparing groove structure in separation layer, and
The second floating gate is prepared on the first floating gate of the corresponding underlay substrate side of active area and groove structure inner wall surface, to make
The effective contact area for obtaining floating gate and control gate increases, and then operation voltage needed for reduction control gate, reduces the function of memory
Consumption.
Fig. 4 is the flow diagram of the preparation method of another memory provided by the embodiment of the utility model, this is practical
New embodiment is on the basis of the technical solution that a upper embodiment provides, respectively to step 210, step 220, step 230
With the further refinement of step 240, details are not described herein for the explanation of same as the previously described embodiments or corresponding term.
Optionally, multiple active areas and multiple shallow trench isolation regions are formed on the underlay substrate, comprising:
The first bed course and the second bed course are successively made on underlay substrate.
Underlay substrate described in etched portions, first bed course and second bed course, form multiple shallow trench isolation regions,
Underlay substrate described in non-etched portions, first bed course and second bed course form multiple active areas.
Optionally, separation layer is filled in the shallow trench isolation region, comprising:
Separation layer is filled in the shallow trench isolation region.
The separation layer is ground using cmp technology, the separation layer and second mat surface
It flushes.
Optionally, the first floating gate is prepared in the corresponding underlay substrate side of the active area, comprising:
First bed course and second bed course are removed, the corresponding underlay substrate of the active area is exposed.
Doped layer is prepared in the upper surface of the corresponding underlay substrate of the active area using Plasma inpouring technology.
Tunnel oxide is prepared on the doped layer.
The first floating gate is prepared on the tunnel oxide.
Optionally, groove structure is prepared in the separation layer, comprising:
The separation layer is performed etching using dry etch process, prepares groove structure.
Based on above-mentioned refinement, as shown in figure 4, the preparation method of memory provided by the embodiment of the utility model, can wrap
Include following steps:
Step 301 provides underlay substrate and successively makes the first bed course and the second bed course on underlay substrate.
Underlay substrate described in step 302, etched portions, first bed course and second bed course are formed multiple shallow
Slot isolated area, underlay substrate, first bed course and second bed course described in non-etched portions form multiple active areas, institute
State active area and shallow trench isolation region interval setting.
Step 303 fills separation layer in the shallow trench isolation region.
Step 304 grinds the separation layer using cmp technology, the separation layer and described second
Mat surface flushes.
Step 305 removes first bed course and second bed course, exposes the corresponding substrate of the active area
Substrate.
Step 306 is prepared using Plasma inpouring technology in the upper surface of the corresponding underlay substrate of the active area
Doped layer.
Step 307 prepares tunnel oxide on the doped layer.
Step 308 prepares the first floating gate on the tunnel oxide.
Step 309 performs etching the separation layer using dry etch process, prepares groove structure.
Step 310 prepares the second floating gate on first floating gate and the groove structure inner wall surface, and described second is floating
Grid are disconnected in the basal surface position of the groove structure.
Step 311, the preparation media layer on second floating gate, the dielectric layer covering are exposed to outside second floating gate
The separation layer.
Step 312 prepares control gate on the dielectric layer.
Fig. 5-Figure 13 is the schematic diagram of each step of preparation method of memory provided by the embodiment of the utility model, reference
Shown in Fig. 5-Figure 13, underlay substrate 11 is provided and successively makes the first bed course 21 and the second bed course 22 on underlay substrate 11, it can
Choosing, underlay substrate 11 be silicon materials, the first bed course 21 be silicon oxide layer, silicon oxide layer with a thickness of D5, the second bed course 22 is
Silicon nitride layer, silicon nitride layer with a thickness of D6, wherein 5nm≤D5≤15nm, 50nm≤D6≤200nm.
Etched portions underlay substrate 11, the first bed course 21 and the second bed course 22, form multiple shallow trench isolation regions 111, not
Etched portions underlay substrate 11, the first bed course 21 and the second bed course 22 form multiple active areas 110, active area 110 and shallow slot
The interval of isolated area 111 setting, wherein can be using photoetching technique to section substrate substrate 11, the first bed course 21 and the second pad
Layer 22 performs etching.
Separation layer 12 is filled in shallow trench isolation region 111, separation layer 12 is ground using cmp technology (CMP)
Mill, so that separation layer 12 is flushed with 22 surface of the second bed course.
The first bed course 21 and the second bed course 22 are removed, the corresponding underlay substrate 11 of active area 110 is exposed, wherein can be with
Using the first bed course 21 and second bed course 22 of wet etching technique removal active area 110.
Doped layer 16 is prepared in the upper surface of the corresponding underlay substrate 11 of active area 110 using Plasma inpouring technology,
Tunnel oxide 17 is prepared on doped layer 16, wherein Plasma inpouring technology can be used to the corresponding substrate base of active area 110
Storage unit threshold voltage infusion (cell VT implant) is injected in the upper surface of plate 11, to form doped layer 16, and uses
The method of boiler tube growth, prepares tunnel oxide 17 on doped layer 16.
The first floating gate 131 is prepared on tunnel oxide 17, wherein can be using the method for boiler tube growth in tunnel oxide
Layer 17 on prepare the first floating gate 131, and can be used cmp technology (CMP) make 131 upper surface of the first floating gate with every
12 upper surface of absciss layer is concordant.Optionally, the first floating gate 131 with a thickness of D1, wherein 100nm≤D1≤200nm.
Separation layer 12 is performed etching using dry etch process, groove structure 121 is prepared, using dry etch process energy
It is enough so that the side wall of the first floating gate 131 and active area 110 there are separation layers 12, to play the work of the first floating gate 131 of protection
With, and storage unit is avoided to generate leakage current.
The second floating gate 132 is prepared in 121 inner wall surface of the first floating gate 131 and groove structure, the second floating gate 132 is in groove
The basal surface position of structure 121 disconnects, wherein can be using the method for boiler tube growth in the first floating gate 131 and groove structure
The second floating gate of flood 132 is prepared in 121 inner wall surfaces, it is then corresponding using photoetching process removal 111 part of shallow trench isolation region
The second floating gate of part 132.Optionally, the distance between second floating gate 132 corresponding to two neighboring active area 110 is L1,
In, L1 >=10nm.
The preparation media layer 14 on the second floating gate 132, dielectric layer 14 cover the separation layer being exposed to outside the second floating gate 132
12, for the second floating gate 132 and control layer 15 to be isolated, wherein the method for boiler tube growth table on the second floating gate 132 can be used
12 upper surface preparation media layer 14 of face and separation layer.Optionally, dielectric layer 14 includes the layer of silica, silicon nitride and silicon oxide layer
Stack structure, wherein the thickness of silicon oxide layer and silicon nitride layer is respectively 1nm-10nm.
Control gate 15 is prepared on dielectric layer 14, wherein can prepare on dielectric layer 14 using the method for boiler tube growth
Control gate 15.Optionally, control gate 15 with a thickness of D7, wherein 100nm≤D7≤200nm.
Optionally, the material of the first floating gate 131, the second floating gate 132 and control gate 15 is polysilicon.
The preparation method of memory provided by the embodiment of the utility model by preparing groove structure in separation layer, and
The second floating gate is prepared on the first floating gate of the corresponding underlay substrate side of active area and groove structure inner wall surface, to make
The effective contact area for obtaining floating gate and control gate increases, and then operation voltage needed for reduction control gate, reduces the function of memory
Consumption.
Note that above are only the preferred embodiment and institute's application technology principle of the utility model.Those skilled in the art's meeting
Understand, the utility model is not limited to specific embodiment described here, is able to carry out for a person skilled in the art various bright
Aobvious variation, readjustment and substitution is without departing from the protection scope of the utility model.Therefore, although passing through above embodiments
The utility model is described in further detail, but the utility model is not limited only to above embodiments, is not departing from
It can also include more other equivalent embodiments in the case that the utility model is conceived, and the scope of the utility model is by appended
Scope of the claims determine.
Claims (6)
1. a kind of memory characterized by comprising
Underlay substrate, the underlay substrate include multiple active areas and multiple shallow trench isolation regions, the active area and the shallow slot
Isolation region is every setting；
Separation layer positioned at the corresponding underlay substrate side in the shallow trench isolation region, the separation layer is interior to form fluted knot
Structure；
The first floating gate positioned at the corresponding underlay substrate side of the active area；
The second floating gate on first floating gate and the groove structure inner wall surface, second floating gate is in the groove
The basal surface position of structure disconnects；
Dielectric layer on second floating gate, the dielectric layer cover the isolation being exposed to outside second floating gate
Layer；
Control gate on the dielectric layer.
2. memory according to claim 1, which is characterized in that described active along the direction of the vertical underlay substrate
Where plane where the upper surface of the corresponding underlay substrate in area is located at the bottom surface of the groove structure on plane.
3. memory according to claim 1, which is characterized in that along the direction of the vertical underlay substrate, described first
Floating gate with a thickness of D1, wherein 100nm≤D1≤200nm.
4. memory according to claim 1, which is characterized in that along the direction of the vertical underlay substrate, described second
Floating gate with a thickness of D2, wherein 5nm≤D2≤20nm.
5. memory according to claim 1, which is characterized in that be directed toward the side of the shallow trench isolation region along the active area
To the opening width of the groove structure is D3, wherein 30nm≤D3≤80nm；
Along the direction of the vertical underlay substrate, the opening depth of the groove structure is D4, wherein 50nm≤D4≤100nm.
6. memory according to claim 1, which is characterized in that be directed toward the side of the shallow trench isolation region along the active area
To the distance between two neighboring described second floating gate is L1, wherein L1 >=10nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920515020.0U CN209496872U (en) | 2019-04-16 | 2019-04-16 | A kind of memory |
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|---|---|---|---|
| CN201920515020.0U CN209496872U (en) | 2019-04-16 | 2019-04-16 | A kind of memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109935592A (en) * | 2019-04-16 | 2019-06-25 | 上海格易电子有限公司 | A kind of memory and preparation method thereof |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109935592A (en) * | 2019-04-16 | 2019-06-25 | 上海格易电子有限公司 | A kind of memory and preparation method thereof |
| CN109935592B (en) * | 2019-04-16 | 2023-12-01 | 上海格易电子有限公司 | Memory and preparation method thereof |
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Address after: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20191015 Effective date of abandoning: 20231201 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20191015 Effective date of abandoning: 20231201 |