CN209461442U - A kind of chip-packaging structure of integrated passive device - Google Patents
A kind of chip-packaging structure of integrated passive device Download PDFInfo
- Publication number
- CN209461442U CN209461442U CN201920129660.8U CN201920129660U CN209461442U CN 209461442 U CN209461442 U CN 209461442U CN 201920129660 U CN201920129660 U CN 201920129660U CN 209461442 U CN209461442 U CN 209461442U
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- China
- Prior art keywords
- chip
- passive device
- lead frame
- dao
- utility
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a kind of chip-packaging structures of integrated passive device, including lead frame, chip, passive device and for encapsulating lead, chip, passive device plastic packaging material, the lead frame includes Ji Dao and pin, the passive device is arranged on the Ji Dao, the chip is arranged on passive device, and the chip is connected by the pin of gold thread and lead frame.The utility model is designed using stacked package, realize the system module encapsulation of lead frame Ji Dao, passive device and chip are consecutively connected on the Ji Dao of lead frame, both it had been able to achieve lead frame base island small-sized package, it can solve integrity problem caused by insufficient filling problem of flexible printed circuit board Ji Dao again, simultaneously, improve production efficiency, improve the utilization rate of lead frame frame and plastic packaging material material, in addition, chip and passive device are connected using the pin of lead frame and Ji Dao, reduction can be with the impedance of package module, avoid signal transmission interference problem.
Description
Technical field
The utility model relates to chip encapsulation technology field more particularly to a kind of chip package knots of integrated passive device
Structure.
Background technique
In the prior art, lead frame base island QFN encapsulating products, most of is only chip package, not by passive device
It combining and is packaged with chip, passive device and chip are combined product by minority, using planar package mode,
Cause product size that can greatly increase, be difficult to meet the requirement of small-sized package, therefore, passive device and chip combine
Encapsulation be substantially using flexible printed circuit board and realize, but this class wrapper exist again passive device bottom space very little (<
50um), plastic package process will appear the insufficient filling in passive device bottom, cause product reliability problem.
Utility model content
The integrated passive device of small, high reliablity that the purpose of this utility model is to provide a kind of sizes, high production efficiency
Chip-packaging structure.
The utility model is realized in this way: a kind of chip-packaging structure of integrated passive device, including lead frame, core
Piece, passive device and for encapsulating lead, chip, passive device plastic packaging material, the lead frame include Ji Dao and
Pin, the passive device are arranged on the Ji Dao, and the chip is arranged on passive device, the chip by gold thread with
The pin of lead frame connects.
Wherein, the Ji Dao is to empty design, and Ji Dao is equipped with through-hole for accommodating plastic packaging material.
Wherein, the chip bottom is additionally provided with load film.
Wherein, the chip size is greater than the size of passive device.
Wherein, the passive device is fixed on Ji Dao by conducting resinl.
The utility model has the following beneficial effects: the chip-packaging structure of integrated passive device described in the utility model uses heap
Folded encapsulation design realizes the system module encapsulation of lead frame Ji Dao, passive device and chip is consecutively connected to lead frame
On the island Jia Ji, it was not only able to achieve lead frame base island small-sized package, but also can solve the insufficient of flexible printed circuit board Ji Dao and fill out
Integrity problem caused by problem is filled, meanwhile, production efficiency is improved, the utilization of lead frame frame and plastic packaging material material is improved
Rate, in addition, connect chip and passive device using the pin of lead frame and Ji Dao, reduce can with the impedance of package module,
Signal transmission interference problem is avoided, product can be applied to the high-end smart field of electronics, such as clock module, signaling module etc..
Detailed description of the invention
Fig. 1 is the sectional view of the chip-packaging structure embodiment of integrated passive device described in the utility model；
Fig. 2 is schematic perspective view of the chip-packaging structure when not being molded plastic packaging material；
Fig. 3 is top view passive device being connected to after lead frame；
Fig. 4 is the top view after connecting the die to passive device.
Wherein, 1, lead frame；11, Ji Dao；111, through-hole；12, pin；2, chip；3, passive device；4, plastic packaging material；
5, gold thread；6, load film；7, conducting resinl.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
The embodiment of chip-packaging structure as integrated passive device described in the utility model, as shown in Figures 1 to 4,
Including lead frame 1, chip 2, passive device 3 and for encapsulating lead 1, chip 2, passive device 3 plastic packaging material 4,
The lead frame 1 includes base island 11 and pin 12, and the passive device 3 is arranged on the base island 11, and the chip 2 is arranged
On passive device 3, the chip 2 is connect by gold thread 5 with the pin 12 of lead frame 1.
The utility model designs the characteristic of combined leads frame Ji Dao and flexible printed circuit board, in the Ji Dao of lead frame
The mode that passive device stacked chips are designed on 11, as one embodiment, the plastic packaging material compares non-heap having a size of 4*4mm
The folded minimum 8*4mm of traditional design size, size are kept to traditional 50%, substantially reduce product size.
In the present embodiment, the utility model can using the design packaged type of lead frame base island passive device stacked chips
The chip 2 for being greater than passive device 3 is supported to be stacked on passive device 3, the structure of the peripheral hanging type of chip 2 still can be welded normally
Line, 2 thickness of chip can be as thin as 100um, it may not be necessary to other special secondary requirements.When the size of chip 2 is greater than the quilt of support
When the size of dynamic element 3, load film 6 can also be also set in 2 bottom of chip, load film 6 can increase the support strength to chip 2
And bearing area.
In the present embodiment, the base island 11 is to empty design, and base island 11 is equipped with through-hole 111 for accommodating plastic packaging material 4.
So that the bottom of passive device 3 there are enough spaces, solves production caused by insufficient filling with flexible printed circuit board Ji Dao
Product integrity problem improves the reliability of product.
In the present embodiment, the passive device 3 is fixed on base island 11 by conducting resinl 7, is realized electrical connection and is fixed.
The utility model uses the design packaged type of lead frame base island passive device stacked chips, makes plastic packaging UPH
(units per hour) is increased to 32.4K, is 16.8K compared to the non-stacking design UPH of traditional design, and the UPH of plastic packaging is improved
93%, effect greatly improves；Usage amount reduces in terms of material, and the utility model improves the utilization rate of lead frame (with lead frame
For 240x74mm, lead frame utilization rate is 240% originally), plastic packaging material usage amount reduces 42%(traditional design one
Mould product quantity is 336, and one mould of the utility model is 810)
The chip-packaging structure of integrated passive device described in the utility model is designed using stacked package, realizes lead frame
The system module on the island Jia Ji encapsulates, and passive device 3 and chip 2 are consecutively connected on the base island 11 of lead frame 1, were both able to achieve
11 small-sized package of base island of lead frame, but can solve can caused by insufficient filling problem of flexible printed circuit board Ji Dao
By property problem, meanwhile, production efficiency is improved, the utilization rate of lead frame and plastic packaging material material is improved, in addition, using lead
The pin 12 of frame and base island 11 connect chip 2 and passive device 3, and reduction can avoid signal from passing with the impedance of package module
Defeated interference problem, product can be applied to the high-end smart field of electronics, such as clock module, signaling module etc..
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model
Protection scope within.
Claims (5)
1. a kind of chip-packaging structure of integrated passive device, which is characterized in that including lead frame, chip, passive device with
And for encapsulating lead, chip, passive device plastic packaging material, the lead frame includes Ji Dao and pin, described passive
Element is arranged on the Ji Dao, and the chip is arranged on passive device, and the chip is drawn by gold thread and lead frame
Foot connection.
2. chip-packaging structure according to claim 1, which is characterized in that the Ji Dao is to empty design, is set on Ji Dao
There is through-hole for accommodating plastic packaging material.
3. chip-packaging structure according to claim 1, which is characterized in that the chip bottom is additionally provided with load film.
4. chip-packaging structure according to claim 3, which is characterized in that the chip size is greater than the ruler of passive device
It is very little.
5. chip-packaging structure according to claim 1, which is characterized in that the passive device is fixed on by conducting resinl
On Ji Dao.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920129660.8U CN209461442U (en) | 2019-01-24 | 2019-01-24 | A kind of chip-packaging structure of integrated passive device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920129660.8U CN209461442U (en) | 2019-01-24 | 2019-01-24 | A kind of chip-packaging structure of integrated passive device |
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| Publication Number | Publication Date |
|---|---|
| CN209461442U true CN209461442U (en) | 2019-10-01 |
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| CN201920129660.8U Active CN209461442U (en) | 2019-01-24 | 2019-01-24 | A kind of chip-packaging structure of integrated passive device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712948A (en) * | 2019-01-24 | 2019-05-03 | 广东气派科技有限公司 | A kind of chip-packaging structure of integrated passive device |
-
2019
- 2019-01-24 CN CN201920129660.8U patent/CN209461442U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712948A (en) * | 2019-01-24 | 2019-05-03 | 广东气派科技有限公司 | A kind of chip-packaging structure of integrated passive device |
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