CN101764127B - Semiconductor package without outer pins and stacked structure thereof - Google Patents
Semiconductor package without outer pins and stacked structure thereof Download PDFInfo
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- CN101764127B CN101764127B CN2008102075717A CN200810207571A CN101764127B CN 101764127 B CN101764127 B CN 101764127B CN 2008102075717 A CN2008102075717 A CN 2008102075717A CN 200810207571 A CN200810207571 A CN 200810207571A CN 101764127 B CN101764127 B CN 101764127B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention discloses a semiconductor package without outer pins and a stacked structure thereof. A first package is formed by arranging at least one chip on a lead frame and carrying out a potting procedure. The two ends of a plurality of contacts are exposed out of the first package, so at least one second package is connected with one of the ends of the contacts. Thus, a POP (package on package) novel multi-chip module structure is made by taking the lead frame of a QFN (quad flat non-leaded) package structure as the base frame.
Description
[technical field]
The invention relates to a kind of semiconductor package body and stacked structure thereof that does not have outer pin, particularly relevant for a kind of square flat outer-pin-free (QFN) packaging structure and stacked structure thereof in order to stacked package body (POP) on the formation packaging body.
[background technology]
Now; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the packaging structure that various different types gradually, (system in package, SIP) design concept is usually used in framework high-density packages structure to wherein various system in package.Generally speaking, system in package can be divided into multi-chip module (multi chip module, MCM), stacked package body on the packaging body (package on package, stacked package body POP) and in the packaging body (package in package, PIP) etc.Said multi-chip module (MCM) is meant lays several chips on same substrate; After chip is set; Utilize same all chips of packing colloid embedding again, and can it be subdivided into again according to the arrangements of chips mode and stack chip (stacked die) encapsulation or chip (side-by-side) encapsulation side by side.Moreover; The structure of stacked package body (POP) is meant that completion one earlier has first packaging body of substrate on the said packaging body; Then stack another second complete packaging body in the packing colloid upper surface of first packaging body again; Second packaging body can see through suitable switching element (for example tin ball) and be electrically connected on the substrate of first packaging body, thereby becomes a compound packaging structure.In comparison; The structure of stacked package body (PIP) then is further to utilize another packing colloid that embedding such as the former encapsulation colloid of second packaging body, switching element and first packaging body etc. together is fixed on the substrate of first packaging body in the said packaging body, thereby becomes a compound packaging structure.
(multi chip module, MCM) all be is that the basis comes framework to go out the high-density packages structure with the substrate to above-mentioned multi-chip module.In addition; Please with reference to shown in Figure 1A and the 1B; Also exist a kind of square flat non-pin packaging structure (quad flat no-lead package, QFN), it belongs to a kind of packaging structure of miniaturization; Shown in Figure 1A be a kind of single-chip square flat non-pin packaging structure with single winding point wherein, it has the advantage of volume miniaturization; And shown in Figure 1B is a kind of single-chip square flat non-pin packaging structure with many winding points, and it further has the advantage that improves contact layout density, so the high-density packages effect that is reached similar in appearance to the said system encapsulation can be provided.
Please with reference to shown in Figure 1A and the 1B, the single-chip square flat non-pin packaging structure with single group or many winding points mainly comprises a lead frame (leadframe) 11, a chip 12, several wires 13 and a packing colloid 14.Said lead frame 11 comprises a chip bearing 111 and several contacts 112, wherein said several contacts 112 with single group or many prescriptions formula be arranged around said chip bearing 111 around.Said chip 12 is arranged on the said chip bearing 111, and said chip 12 utilizes said several wires 13 to be electrically connected to respectively on said several contacts 112.Said packing colloid 14 is protected the part surface of said chip 12, lead 13 and said lead frame 11 in order to embedding, only exposes the lower surface of said chip bearing 111 and said several contacts 112 at the lower surface of said packing colloid 14.Therefore, the lower surface of said several contacts 112 can be as the input/output terminal of square flat non-pin packaging structure through after suitably handling.
Though the single-chip square flat non-pin packaging structure shown in Figure 1B helps reaching high pin density encapsulation purpose because of having many winding points 112; But when the group number of said contact 112 (that is row's number) greater than 4 groups or more for a long time; With making routing (wire bonding) program of said lead 13 become complicated and difficult; Have just that said lead is 13 long, plain conductor 13 required inflection points become the technical problems such as the complicacy that is staggered between many and the said lead 13, and make consumption cost and difficult design degree improve.Simultaneously, when the sealing of carrying out said packing colloid 14 (molding) program, mobile encapsulating material will promote long lead 13 easily, cause adjacent said lead 13 to contact with each other and will cause short circuit, thereby improve the problem of defective products.
So, be necessary to provide a kind of semiconductor package body and stacked structure thereof that does not have outer pin, existing high-density packages problem when being applied in the multi-chip module field to solve existing square flat non-pin (QFN) encapsulation technology.
[summary of the invention]
Main purpose of the present invention is to provide a kind of semiconductor package body and stacked structure thereof that does not have outer pin; It is that the lead frame with square flat non-pin (QFN) packaging structure is the brand-new multi-chip module structure that architecture goes out stacked package body (POP) on the packaging body, and then enlarges the range of application of square flat non-pin (QFN) packaging structure and meet the demand of high-density packages.
Secondary objective of the present invention is to provide a kind of semiconductor package body and stacked structure thereof that does not have outer pin, and it is on lead frame, to place at least one chip, and sealing forms one first packaging body.Two ends of exposed several contacts of said first packaging body; Connect at least one second packaging body and the optional line style from of said chip (wire bonding) chip or flip chip type (flipchip so that utilize a wherein end of said contact to stack; Thereby increase the design margin of high-density packages and promote the yields (yield) of high-density packages FC).
For reaching aforementioned purpose of the present invention, the present invention provides a kind of semiconductor package body of not having outer pin, it is characterized in that: the semiconductor package body of the outer pin of said nothing comprises: a lead frame, at least one chip, several electric connection element and packing colloids.Said lead frame has at least one group first contact and at least one group second contact.Said chip utilizes said electric connection element to electrically connect one first end of said first contact.The said chip of said packing colloid embedding, said electric connection element, said first contact and said second contact; One first end of wherein said second contact is exposed to a first surface of said packing colloid, and one second end of said first contact and one second end of said second contact are exposed to a second surface of said packing colloid.
In one embodiment of this invention, said lead frame comprises a chip bearing in addition, to carry said chip.
In one embodiment of this invention, said electric connection element is selected from lead or projection.
In one embodiment of this invention, first end of said first contact and/or second end have the layer that helps of one deck at least.
In one embodiment of this invention, first end of said second contact and/or second end have the layer that helps of one deck at least.
In one embodiment of this invention, said help layer be selected from nickel, gold, tin, silver, organic solderability preservative (organic solderability preservatives, OSP) or its composite bed.
Moreover the present invention provides a kind of stacked structure that does not have the semiconductor package body of outer pin, it is characterized in that: the stacked structure of the semiconductor package body of the outer pin of said nothing comprises: one first packaging body and one second packaging body.Said first packaging body comprises a lead frame, at least one chip, several electric connection element and packing colloids.Said lead frame has at least one group first contact and at least one group second contact.Said chip utilizes said electric connection element to electrically connect one first end of said first contact.The said chip of said packing colloid embedding, said electric connection element, said first contact and said second contact; One first end of wherein said second contact is exposed to a first surface of said packing colloid, and one second end of said first contact and one second end of said second contact are exposed to a second surface of said packing colloid.Said second packaging body utilizes several switching elements, and said switching element is in order to be electrically connected at first end of said second contact.
In addition, the present invention provides the another kind of stacked structure that does not have the semiconductor package body of outer pin, it is characterized in that: the stacked structure of the semiconductor package body of the outer pin of said nothing comprises: one first packaging body and one second packaging body.Said first packaging body comprises a lead frame, at least one chip, several electric connection element and packing colloids.Said lead frame has at least one group first contact and at least one group second contact.Said chip utilizes said electric connection element to electrically connect one first end of said first contact.The said chip of said packing colloid embedding, said electric connection element, said first contact and said second contact; One first end of wherein said second contact is exposed to a first surface of said packing colloid, and one second end of said first contact and one second end of said second contact are exposed to a second surface of said packing colloid.Said second packaging body utilizes several switching elements, and said switching element is in order to second end that is electrically connected at said second contact and second end of said first contact.
In one embodiment of this invention, said switching element is the tin ball.
In one embodiment of this invention, said lead frame comprises a chip bearing in addition, to carry said chip.
In one embodiment of this invention, said electric connection element is selected from lead or projection.
In one embodiment of this invention, first end of said first contact and/or second end have the layer that helps of one deck at least.
In one embodiment of this invention, first end of said second contact and/or second end have the layer that helps of one deck at least.
In one embodiment of this invention, the said layer that helps is selected from nickel, gold, tin, silver, organic solderability preservative (OSP) or its composite bed.
[description of drawings]
Figure 1A and 1B are existing sketch mapes with single-chip square flat non-pin packaging structure of single group or many winding points.
Fig. 2 A, 2B, 2C and 2D are the semiconductor package body of the outer pin of the nothing of first embodiment of the invention and the manufacturing process sketch map of stacked structure thereof.
Fig. 3 is the semiconductor package body of the outer pin of the nothing of second embodiment of the invention and the sketch map of stacked structure thereof.
Fig. 4 is the semiconductor package body of the outer pin of the nothing of third embodiment of the invention and the sketch map of stacked structure thereof.
Fig. 5 is the semiconductor package body of the outer pin of the nothing of fourth embodiment of the invention and the sketch map of stacked structure thereof.
Fig. 6 is the semiconductor package body of the outer pin of the nothing of fifth embodiment of the invention and the sketch map of stacked structure thereof.
[embodiment]
Present embodiment will combine diagram that the present invention is described in detail.The explanation of following each embodiment is graphic with reference to what add, can be in order to the specific embodiment of implementing in order to illustration the present invention.The direction term that the present invention mentioned, for example " on ", D score, " preceding ", " back ", " left side " or " right side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is to be used for the aid illustration relative configurations, but not is used for limiting the present invention.
Please with reference to shown in Fig. 2 A, 2B, 2C, 2D and the 2E; The semiconductor package body of the outer pin of nothing of its announcement first embodiment of the invention and the manufacturing process sketch map of stacked structure thereof; It is in order to the semiconductor package body of the outer pin of nothing that illustrates first embodiment of the invention and the possible manufacturing approach of stacked structure thereof; But the semiconductor package body and the stacked structure thereof of the outer pin of nothing of the present invention still possibly prepared by other manufacturing approaches, are not limited to this, in this close chat earlier bright.
Please with reference to shown in Fig. 2 A; The semiconductor package body of the outer pin of the nothing of first embodiment of the invention and the manufacturing approach first step of stacked structure thereof are: prepare a metallic plate 2; And process said metallic plate 2, to form at least one group first contact 21, at least one group second contact 22 and a chip bearing 23.In this step, said metallic plate 2 is preferably the plate body of being processed by copper, nickel, aluminium, equivalent metal or its alloy, and the present invention can form the semiconductor package body of pin outside several nothings synchronously on same metallic plate 2.The present invention's existing photoresist program capable of using forms the photoresist (not illustrating) of a patterning at the upper surface of said metallic plate 2; Utilize the said metallic plate 2 of suitable etching solution etching and processing again, with etching form several grooves (indicating) in order to distinguish at a distance from and said first contact 21 of definition, said second contact 22 and said chip bearing 23.Just, the present invention can be through implementing for several times different patterning photoresist programs, to define the differing heights of said first contact 21, said second contact 22 and said chip bearing 23 one by one.Perhaps, the present invention also can define the differing heights of said first contact 21, said second contact 22 and said chip bearing 23 through the mode of forging and pressing (forging) or casting (casting).In the present embodiment, the height of said first contact 21 is less than the height of said second contact 22, but the height of said first contact 21 is preferably greater than the height of said chip bearing 23.The group number of said first contact 21 is 1 group, but is not limited thereto.The group number of said second contact 22 is 1 or 2 group, but is not limited thereto.Said first contact 21 and second contact 22 are convexly equipped with and are formed on the said metallic plate 2, said first contact 21 around be arranged in said chip bearing 23 around, and said second contact 22 around be arranged in said first contact 21 around.In addition, in some product, said metallic plate 2 can omit said chip bearing 23 is set, and only is to reserve a upper surface ditch slot space (not illustrating) as a chip rest area.
Please refer again to shown in Fig. 2 B; The semiconductor package body of the outer pin of the nothing of first embodiment of the invention and manufacturing approach second step of stacked structure thereof are: at least one chip 3 is placed on the said metallic plate 2, and utilizes several to electrically connect one first end 211 (that is top) that element 4 electrically connects said first contact 21.In this step,, then said chip 3 is placed on the said chip bearing 23 through liquid viscose or solid-state adhesive tape (not indicating) if said metallic plate 2 is provided with said chip bearing 23; If said metallic plate 2 do not establish said chip bearing 23, on the metallic plate 2 of the ditch slot space that then said chip 3 is utilized similar approach to be placed on to form between said first contact 21 (do not illustrate, that is chip rest area).In the present embodiment, said electric connection element 4 is selected from lead, for example gold thread or copper cash etc.The height of first end 211 of said first contact 21 preferably equals the height on the active surface (not indicating) of said chip 3.Said electric connection element 4 is connected between first end 211 of several weld pads (not illustrating) and said first contact 21 on active surface of said chip 3.After electric connection, the maximum height of said electric connection element 4 must be controlled to be the height that is not more than said second contact 22.
Please refer again to shown in Fig. 2 B, the semiconductor package body of the outer pin of the nothing of first embodiment of the invention and the manufacturing approach third step of stacked structure thereof are: utilize the said chip of a packing colloid 5 embeddings 3, said electric connection element 4, said first contact 21 and said second contact 22.In this step, it is glue material or other equivalent packing materials on basis that said packing colloid 5 can be selected from epoxy resin.After accomplishing the sealing program, first end 211 of said first contact 21 is by 5 embeddings of said packing colloid, and one first end 221 (that is top) of said second contact 22 is also temporarily by 5 embeddings of said packing colloid.At the lower surface of whole semi-finished product packaging structure, then be to expose said metallic plate 2.
Please with reference to shown in Fig. 2 C; The semiconductor package body of the outer pin of the nothing of first embodiment of the invention and manufacturing approach the 4th step of stacked structure thereof are: remove the redundance of said metallic plate 2, with one second end 212 (that is bottom) of exposed said first contact 21 and one second end 222 (that is bottom) of said second contact 22; And remove the redundance of said first packing colloid 5, with first end 221 of exposed said second contact 22.In this step, the treatment step of said metallic plate 2 and said packing colloid 5 is selectivity to exchange in proper order.The present invention can remove the redundance of said metallic plate 2 through the mode of mechanical lapping or chemical etching, that is metallic plate 2 parts of said first contact 21 of undefined one-tenth, said second contact 22 and said chip bearing 23.In addition, the present invention can remove the redundance of said packing colloid 5 through the mode of mechanical lapping, that is covers packing colloid 5 parts on first end 221 of said second contact 22.Behind the redundance of removing said metallic plate 2; Can define second end 212 of said first contact 21 and second end 222 of said second contact 22; And electrically separate said first contact 21, said second contact 22 and said chip bearing 23, and form a lead frame 20 by said first contact 21, said second contact 22 and the 23 common definition of said chip bearing.Behind the redundance of removing said packing colloid 5, then can expose first end 221 of said second contact 22.In addition, if utilize chemical etching to remove the redundance of said metallic plate 2, second end 212 of then said first contact 21 and second end 222 of said second contact 22 possibly slightly protrude from the basal surface of said packing colloid 5.
Please with reference to shown in Fig. 2 C; After accomplishing the 4th step; What second end 212 that the present invention also can be chosen in said first contact 21 and first end 221 of said second contact 22 and second end 222 further formed one deck at least helps layer 24; The said layer 24 that helps can be selected from nickel, gold, tin, silver, organic solderability preservative (organic solderability preservatives; OSP) or its composite bed, for example be selected from electroless nickel layer, electrogilding layer, electroless nickel platingization gold layer (electroless Ni/Au), immersion silver (immersion silver), immersion tin (immersion tin), organic solderability preservative or its composite bed etc., but be not limited to this.Then,, then need cut above-mentioned semi-finished product packaging structure, to separate into several semiconductor package body of not having outer pin (below be called first packaging body 200) if be on same metallic plate 2, to define several lead frames 20 at the beginning.When cutting, can cut said packing colloid 5 through modes such as machinery knives, laser (laser) or high-pressure water knifes, to separate into several first packaging bodies 200.Therefore, the present invention can once make simultaneously and accomplish several said first packaging bodies 200, for the follow-up packaging body (of the 5th step) that combines other identical or different types that stacks.In the present embodiment, first packaging body 200 of the present invention comprises: a lead frame 20, at least one chip 3, several electrically connect element 4 and packing colloids 5.Said lead frame 20 has at least one group first contact 21 and at least one group second contact 22.Said chip 3 utilizes said electric connection element 4 to electrically connect one first end 211 of said first contact 21.The said chip of said packing colloid 5 embeddings 3, said electric connection element 4, said first contact 21 and said second contact 22; One first end 211 of wherein said second contact 22 is exposed to a first surface (that is end face) of said packing colloid 5, and one second end of said first contact and one second end of said second contact are exposed to a second surface (that is bottom surface) of said packing colloid.Through above-mentioned framework, second end 212 of said chip 3 said first contacts 21 capable of using is as the I/O end, so that electrically connect an exterior electrical components (not illustrating), and motherboard etc. for example.
Please with reference to shown in Fig. 2 D, the semiconductor package body of the outer pin of the nothing of first embodiment of the invention and manufacturing approach the 5th step of stacked structure thereof are: utilize several switching elements 61 to electrically connect first end 221 of second contact 22 of said first packaging body 200 at least one second packaging body 600.In this step, that the quantity of said second packaging body 600 can be is single, two or more than.For example; In the present embodiment; Second packaging body 600 of the present invention is single baii grid array packaging structure (ball gridarray; BGA); Said second packaging body 600 has said several switching elements 61, a base plate for packaging 62, at least one chip 63, several electrically connect element 64 and packing colloids 65, and wherein said at least one chip 63 utilizes said several to electrically connect several weld pads (not illustrating) that elements 64 are electrically connected at the upper surface of said base plate for packaging 62, and it is optional from lead (for example gold thread or copper cash) or projection (for example tin projection or golden projection) that said several electrically connect elements 64.In the present embodiment, the quantity of said at least one chip 63 is single, but is not limited thereto.Said second packaging body 600 is that said several switching elements 61 that possess through itself electrically connect first end 221 of second contact 22 of said first packaging body 200, thereby said second packaging body 600 is stacked above said first packaging body 200.In the present embodiment, said switching element 61 is the tin ball, but different according to the kind of said second packaging body 600, said switching element 61 also can change thereupon.Moreover except being selected from the packaging structure with substrate, said second packaging body 600 also can be selected from the packaging structure with lead frame, and the present invention will give in addition in following other embodiment and illustrate the possible execution mode of second packaging body 600 of the present invention.Through above-mentioned framework; The chip 3 of said first packaging body 200 and the chip 63 of said second packaging body 600 can utilize second end 222 of second end 212 and said second contact 22 of said first contact 21 as the I/O end respectively; So that electrically connect an exterior electrical components (not illustrating), motherboard etc. for example.
Please with reference to shown in Figure 3, it discloses semiconductor package body and the sketch map of stacked structure thereof of the outer pin of nothing of second embodiment of the invention.Second embodiment of the invention is approximately identical to first embodiment of the invention; It is continued to use same reference numbers and can be made by similar manufacturing approach, but the difference characteristic of the second embodiment of the invention and first embodiment is: the lead frame 20 of first packaging body 200 of second embodiment of the invention can omit said chip bearing 23 is set; The quantity of said chip 3 is two, but also can be single, three or more than; Said first contact 21 has two groups, but also can be single group, three groups or more than.Moreover at least one second packaging body 700 is to be selected from square flat non-pin (QFN) packaging structure, and the quantity of said second packaging body 700 is single, but also can be two or more than.Said second packaging body 700 has several switching elements 71, a lead frame 72, at least one chip 73, several electrically connect element 74 and packing colloids 75, and wherein said several switching elements 71 are selected from the tin ball.Said lead frame 72 has an at least one winding point 721 and a chip bearing 722.In the present embodiment, the quantity of said chip 73 is two, but also can be single, three or more than; Said contact 721 has two groups, but also can be single group, three groups or more than.It is optional from lead that said several electrically connect element 74, for example gold thread or copper cash.Said chip 73 is electrically connected to the contact 721 of said lead frame 72 respectively through said electric connection element 74 (lead), be electrically connected to first end 221 of second contact 22 of said first packaging body 200 again via said switching element 71.Through above-mentioned framework; The chip 3 of said first packaging body 200 and the chip 73 of said second packaging body 700 can utilize second end 222 of second end 212 and said second contact 22 of said first contact 21 as the I/O end respectively; So that electrically connect an exterior electrical components (not illustrating), motherboard etc. for example.
Please with reference to shown in Figure 4, it discloses semiconductor package body and the sketch map of stacked structure thereof of the outer pin of nothing of third embodiment of the invention.Third embodiment of the invention is approximately identical to the present invention first and two embodiment; It is continued to use same reference numbers and can be made by similar manufacturing approach; But the difference characteristic of third embodiment of the invention and first and two embodiment is: first packaging body 200 of third embodiment of the invention is to be upside down setting up and down, so that electrically connect and stack with 700 formation of at least one second packaging body.Said second packaging body 700 is selected from square flat non-pin (QFN) packaging structure equally; Said second packaging body 700 has several switching elements 71, a lead frame 72, at least one chip 73, several electrically connect element 74 and packing colloids 75, and wherein said several switching elements 71 are selected from the tin ball.Said lead frame 72 has an at least one winding point 721 and a chip bearing 722.In the present embodiment, said contact 721 has three groups, but is not limited thereto.It is optional from lead that said several electrically connect element 74, for example gold thread or copper cash.Said chip 73 is electrically connected to the contact 721 of said lead frame 72 respectively through said electric connection element 74 (lead), be electrically connected to first end 221 of second contact 22 of said first packaging body 200 again via said switching element 71.Moreover the chip 3 of said first packaging body 200 takes back said second contact 22 through said electric connection element 4, said first contact 21, said switching element 71, said contact 721, said electric connection element 74, said chip 73, said electric connection element 74 and said switching element 71 in regular turn again.Through above-mentioned framework; The chip 3 of said first packaging body 200 and the chip 73 of said second packaging body 700 can utilize second end 222 of said second contact 22 as the I/O end respectively; So that electrically connect an exterior electrical components (not illustrating), motherboard etc. for example.
Please with reference to shown in Figure 5, it discloses semiconductor package body and the sketch map of stacked structure thereof of the outer pin of nothing of fourth embodiment of the invention.Fourth embodiment of the invention is approximately identical to second embodiment of the invention; It is continued to use same reference numbers and can be made by similar manufacturing approach; But the difference characteristic of the fourth embodiment of the invention and second embodiment is: at least one chip 3 ' of first packaging body 200 of fourth embodiment of the invention is to be selected from flip chip type (flip chip; FC), wherein said electric connection element 4 ' is selected from projection (bump), for example tin projection or golden projection etc.The quantity of said chip 3 ' be single, two or more, if two or more for a long time, abutment capable of using is arranged on the said electric connection element 4 '.At this moment, said lead frame 20 omits said chip bearing 23 is set.In addition; In some product; At least one chip 73 of said second packaging body 700 also possibly be selected from flip chip type (not illustrating); Wherein said electric connection element 74 is selected from projection, and this moment, said chip 73 utilized said electric connection element 74 to be set directly at first end, 221 tops of said second contact 22.Through above-mentioned framework; The chip 73 of the chip 3 ' of said first packaging body 200 and said second packaging body 700 can utilize second end 222 of second end 212 and said second contact 22 of said first contact 21 as the I/O end respectively; So that electrically connect an exterior electrical components (not illustrating), motherboard etc. for example.
Please with reference to shown in Figure 6, it discloses semiconductor package body and the sketch map of stacked structure thereof of the outer pin of nothing of fifth embodiment of the invention.Fifth embodiment of the invention is approximately identical to third embodiment of the invention; It is continued to use same reference numbers and can be made by similar manufacturing approach; But the difference characteristic of fifth embodiment of the invention and the 3rd embodiment is: first packaging body 200 of fifth embodiment of the invention is to be upside down setting up and down; And at least one chip 3 ' of said first packaging body 200 is to be selected from flip chip type (FC), and wherein said electric connection element 4 ' is selected from projection, for example tin projection or golden projection etc.The quantity of said chip 3 ' be single, two or more, if two or more for a long time, abutment capable of using is arranged on the said electric connection element 4 '.At this moment, said lead frame 20 omits said chip bearing 23 is set.In addition; In some product; At least one chip 73 of said second packaging body 700 also possibly be selected from flip chip type (not illustrating); Wherein said electric connection element 74 is selected from projection, and this moment, said chip 73 utilized said electric connection element 74 to be set directly at first end, 211 tops of first end 221 and said first contact 21 of said second contact 22.Through above-mentioned framework; The chip 73 of the chip 3 ' of said first packaging body 200 and said second packaging body 700 can utilize second end 222 of said second contact 22 as the I/O end respectively; So that electrically connect an exterior electrical components (not illustrating), motherboard etc. for example.
As stated; Limit because of the routing that receives lead compared to existing single-chip square flat non-pin packaging structure with many winding points; And can't further improve pin group number again; Cause being unfavorable for promoting the yields of high pin density encapsulation; The present invention of the 2nd to 6 figure is the brand-new multi-chip module structure that architecture goes out to be similar to stacked package body (POP) on the packaging body with the lead frame 20 of square flat non-pin (QFN) packaging structure, the demand that it helps enlarging the range of application of square flat non-pin packaging structure really and meets high-density packages.Moreover the present invention places at least one chip 3 on said lead frame 20, and sealing forms one first packaging body 200.First end 221 and second end 222 of said first packaging body, 200 exposed several second contacts 22; Connect at least one second packaging body 600 or 700 so that utilize second end 222 of said second contact 22 to stack; And said chip 3,73 optional chip of line style from or flip chip types; Thereby not only can increase the design margin of high-density packages, and also help promoting the yields of high-density packages.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is merely the example of embodiment of the present invention.Must be pointed out that disclosed embodiment does not limit scope of the present invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in scope of the present invention.
Claims (11)
1. the semiconductor package body of the outer pin of a nothing, it is characterized in that: the semiconductor package body of the outer pin of said nothing comprises:
One lead frame has at least one group first contact and at least one group second contact of being formed by same metallic plate definition, and the height of said first contact is less than the height of said second contact;
At least one chip;
Several electrically connect element, electrically connect one first end of said at least one chip and said first contact; And
One packing colloid; The said chip of embedding, said electric connection element, said first contact and said second contact; One first end of wherein said second contact is exposed to a first surface of said packing colloid, and one second end of said first contact and one second end of said second contact are exposed to a second surface of said packing colloid.
2. the semiconductor package body of the outer pin of nothing as claimed in claim 1, it is characterized in that: said lead frame comprises a chip bearing in addition, to carry said chip.
3. the semiconductor package body of the outer pin of nothing as claimed in claim 1, it is characterized in that: said electric connection element is selected from lead or projection.
4. the semiconductor package body of the outer pin of nothing as claimed in claim 3, it is characterized in that: said electric connection element is a lead, and the height of first end of said first contact equals an active surface height of said chip.
5. the semiconductor package body of the outer pin of nothing as claimed in claim 1 is characterized in that: at least one first end that layer is formed at said first contact or first end or second end of second end or said second contact of helping.
6. the stacked structure of the semiconductor package body of the outer pin of a nothing, it is characterized in that: the stacked structure of the semiconductor package body of the outer pin of said nothing comprises:
One first packaging body comprises;
One lead frame has at least one group first contact and at least one group second contact of being formed by same metallic plate definition, and the height of said first contact is less than the height of said second contact;
At least one chip;
Several electrically connect element, electrically connect one first end of said at least one chip and said first contact; And
One packing colloid; The said chip of embedding, said electric connection element, said first contact and said second contact; One first end of wherein said second contact is exposed to a first surface of said packing colloid, and one second end of said first contact and one second end of said second contact are exposed to a second surface of said packing colloid; And
One second packaging body utilizes several switching elements to be electrically connected at first end of said second contact.
7. the stacked structure of the semiconductor package body of the outer pin of nothing as claimed in claim 6, it is characterized in that: said lead frame comprises a chip bearing in addition, to carry said chip.
8. the stacked structure of the semiconductor package body of the outer pin of nothing as claimed in claim 6, it is characterized in that: said electric connection element is selected from lead or projection; Said switching element is the tin ball.
9. the stacked structure of the semiconductor package body of the outer pin of a nothing, it is characterized in that: the stacked structure of the semiconductor package body of the outer pin of said nothing comprises:
One first packaging body comprises;
One lead frame has at least one group first contact and at least one group second contact of being formed by same metallic plate definition, and the height of said first contact is less than the height of said second contact;
At least one chip;
Several electrically connect element, electrically connect one first end of said at least one chip and said first contact; And
One packing colloid; The said chip of embedding, said electric connection element, said first contact and said second contact; One first end of wherein said second contact is exposed to a first surface of said packing colloid, and one second end of said first contact and one second end of said second contact are exposed to a second surface of said packing colloid; And
One second packaging body utilizes several switching elements to be electrically connected at second end of said second contact and second end of said first contact.
10. the stacked structure of the semiconductor package body of the outer pin of nothing as claimed in claim 9, it is characterized in that: said lead frame comprises a chip bearing in addition, to carry said chip.
11. the stacked structure of the semiconductor package body of the outer pin of nothing as claimed in claim 9, it is characterized in that: said electric connection element is selected from lead or projection; Said switching element is the tin ball.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008102075717A CN101764127B (en) | 2008-12-23 | 2008-12-23 | Semiconductor package without outer pins and stacked structure thereof |
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| CN2008102075717A CN101764127B (en) | 2008-12-23 | 2008-12-23 | Semiconductor package without outer pins and stacked structure thereof |
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| Publication Number | Publication Date |
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| CN101764127A CN101764127A (en) | 2010-06-30 |
| CN101764127B true CN101764127B (en) | 2012-01-04 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9412689B2 (en) * | 2012-01-24 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and method |
| CN102769005A (en) * | 2012-06-28 | 2012-11-07 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and manufacture method thereof |
| CN102832139B (en) * | 2012-08-10 | 2015-05-06 | 华为技术有限公司 | Flat packaging body without pins around, and packaging method of flat packaging body |
| CN104659004A (en) * | 2014-12-30 | 2015-05-27 | 华天科技（西安）有限公司 | Pop structure and manufacture method thereof |
| CN104505382A (en) * | 2014-12-30 | 2015-04-08 | 华天科技（西安）有限公司 | Wafer-level fan-out PoP encapsulation structure and making method thereof |
| CN105827268A (en) * | 2015-01-23 | 2016-08-03 | 联发科技股份有限公司 | Wireless communication device |
| CN104952857B (en) * | 2015-06-30 | 2017-12-26 | 通富微电子股份有限公司 | A kind of DNAcarrier free semiconductor laminated encapsulating structure |
| CN105161424A (en) * | 2015-07-30 | 2015-12-16 | 南通富士通微电子股份有限公司 | Semiconductor stacked packaging method |
| CN105161425A (en) * | 2015-07-30 | 2015-12-16 | 南通富士通微电子股份有限公司 | Semiconductor stacked packaging method |
| CN105097569A (en) * | 2015-07-30 | 2015-11-25 | 南通富士通微电子股份有限公司 | Semiconductor lamination packaging method |
| CN109817597A (en) * | 2017-11-21 | 2019-05-28 | 比亚迪股份有限公司 | A kind of battery protection chip encapsulating structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1153997A (en) * | 1995-12-29 | 1997-07-09 | Lg半导体株式会社 | Improved integrated chip package with reduced dimensions |
| CN101226929A (en) * | 2008-02-20 | 2008-07-23 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1153997A (en) * | 1995-12-29 | 1997-07-09 | Lg半导体株式会社 | Improved integrated chip package with reduced dimensions |
| CN101226929A (en) * | 2008-02-20 | 2008-07-23 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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