CN209418491U - 一种超薄块型封装结构 - Google Patents

一种超薄块型封装结构 Download PDF

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CN209418491U
CN209418491U CN201821685347.4U CN201821685347U CN209418491U CN 209418491 U CN209418491 U CN 209418491U CN 201821685347 U CN201821685347 U CN 201821685347U CN 209418491 U CN209418491 U CN 209418491U
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chip
encapsulating structure
ultra
thickness
metal pins
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陈建华
陆鸿兴
赵亮
游志文
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Siliconware Technology SuZhou Co Ltd
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Siliconware Technology SuZhou Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

本实用新型揭示了一种超薄块型封装结构,该超薄块型封装结构包括芯片、金属引脚、金属引线和塑封体,所述芯片的四周间隙设置有金属引脚,所述芯片与金属引脚之间通过金属引线电性连接,芯片的上表面与金属引脚的四周均被塑封体覆盖,芯片的下表面外露。所述芯片的厚度为50~300μm,所述塑封体厚度为200~800um。本技术方案提供了一种厚度更薄的封装结构,大大地降低了现有封装结构积体电路体积,节省了终端应用空间。

Description

一种超薄块型封装结构
技术领域
本实用新型涉及一种超薄块型封装结构,可用于半导体封装技术领域。
背景技术
传统的块型地图型四方平面无脚封装结构积体电路主要采用金属基岛支撑上方芯片,这种传统封装结构的不足点在于:金属基岛及基岛与芯片间粘结物质自身有一定厚度,该厚度会影响整个封装体厚度,后续封装过程中需考量这一厚度。芯片通过导电或不导电粘结物质与金属基岛相连,芯片表面用金属线与金属线路板管脚连接信号互通,此设计集成电路塑封体厚度高。
实用新型内容
本实用新型的目的就是为了解决现有技术中存在的上述问题,提出一种超薄块型封装结构。
本实用新型的目的将通过以下技术方案得以实现:一种超薄块型封装结构,包括芯片、金属引脚、金属引线和塑封体,所述芯片的四周间隙设置有金属引脚,所述芯片与金属引脚之间通过金属引线电性连接,芯片的上表面与金属引脚的四周均被塑封体覆盖,芯片的下表面外露。
优选地,所述芯片的厚度为50~300μm。
优选地,所述塑封体厚度为200~800um。
优选地,所述线路板为铜板、单层树脂线路板或多层树脂线路板。
优选地,所述金属引线为金线、银线、铜线或其他合金线。
优选地,所述金属引脚的厚度为0.1~0.2mm。
优选地,所述金属引脚的厚度为0.05~0.15mm。
本实用新型技术方案的优点主要体现在:本技术方案提供了一种厚度更薄的封装结构,大大地降低了现有块型地图型四方平面无脚封装结构积体电路体积,节省了终端应用空间。
该方案可以应用在一般的封装体及封装工艺使其成为超薄胶体集成电路,如MQFN可以成为ST-MQFN/BGA可以成为ST-BGA/FPS可以成为ST-FPS……减少集成电路在终端印刷板电路所占用体积。
附图说明
图1为本实用新型的一种超薄块型封装结构的示意图。
图2为本实用新型的一种超薄块型封装结构的示意图。
图3为图1、图2的俯视图。
图中附图标记:1---金属引脚,2---芯片,6---金属引线,4---塑封体。
具体实施方式
本实用新型的目的、优点和特点,将通过下面优选实施例的非限制性说明进行图示和解释。这些实施例仅是应用本实用新型技术方案的典型范例,凡采取等同替换或者等效变换而形成的技术方案,均落在本实用新型要求保护的范围之内。
本实用新型揭示了一种超薄块型封装结构,如图1、图2和图3所示,该超薄块型封装结构包括金属引脚1、芯片2、金属引线6和塑封体4,所述芯片的四周间隙设置有金属引脚1,所述芯片2与金属引脚1之间通过金属引线6电性连接,芯片2的上表面与金属引脚的四周均被塑封体覆盖,芯片2的下表面外露,芯片的下表面为散热面。
实施例1:图1中,金属引脚厚度为金属引线框架即有厚度,金属引脚的厚度为0.1~0.2mm,在本技术方案中,金属引脚的厚度优选为0.2mm,金属引线会打在此高度引脚上方。
所述芯片2的厚度为50~300μm,所述塑封体4的厚度为200~800um。所述线路板为铜板、单层树脂线路板或多层树脂线路板。所述金属引线6为金线、银线、铜线或其他合金线。该方案取消了金属基岛和粘接物质,芯片的背面为外露状态,芯片背面外露更利于散热。
实施例2:图2中,金属引脚1的厚度为0.05~0.15mm,在本技术方案中,金属引脚1的厚度优选为0.1mm。该金属引脚的厚度用蚀刻或其他方法将厚度变为实施例1金属引脚厚度的一半或更小,此时金属引线打在此处可使金属引线高度再降低,从而使整个封装体厚度做到更薄。
在封装过程中先以有机膜承载芯片,有机膜有黏性,在塑封体将芯片及金属引脚都固定住后将有机膜撕除,最终芯片背面外露起到散热效果。
本技术方案取消了金属基岛及基岛与芯片间粘结物质,以塑封体全包裹芯片及金属引脚,降低整体积体电路厚度,解决了目前块型地图型四方平面无脚封装结构积体电路厚度过高问题,使现有的封装结构变的更薄,适合在产业上推广使用。
本实用新型尚有多种实施方式,凡采用等同变换或者等效变换而形成的所有技术方案,均落在本实用新型的保护范围之内。

Claims (6)

1.一种超薄块型封装结构,其特征在于:包括芯片、金属引脚、金属引线和塑封体,所述芯片的四周间隙设置有金属引脚,所述芯片与金属引脚之间通过金属引线电性连接,芯片的上表面与金属引脚的四周均被塑封体覆盖,芯片的下表面外露。
2.根据权利要求1所述的一种超薄块型封装结构,其特征在于:所述芯片的厚度为50~300μm。
3.根据权利要求1所述的一种超薄块型封装结构,其特征在于:所述塑封体厚度为200~800um。
4.根据权利要求1所述的一种超薄块型封装结构,其特征在于:所述金属引线为金线、银线、铜线或其他合金线。
5.根据权利要求1所述的一种超薄块型封装结构,其特征在于:所述金属引脚的厚度为0.1~0.2mm。
6.根据权利要求1所述的一种超薄块型封装结构,其特征在于:所述金属引脚的厚度为0.05~0.15mm。
CN201821685347.4U 2018-10-17 2018-10-17 一种超薄块型封装结构 Active CN209418491U (zh)

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