CN208923108U - Smt用防短路dfn器件封装结构 - Google Patents
Smt用防短路dfn器件封装结构 Download PDFInfo
- Publication number
- CN208923108U CN208923108U CN201821959629.9U CN201821959629U CN208923108U CN 208923108 U CN208923108 U CN 208923108U CN 201821959629 U CN201821959629 U CN 201821959629U CN 208923108 U CN208923108 U CN 208923108U
- Authority
- CN
- China
- Prior art keywords
- heat dissipation
- bonding pad
- chip
- dissipation bonding
- separation trough
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
本实用新型公开一种SMT用防短路DFN器件封装结构,包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述芯片位于散热焊盘上,且所述芯片与散热焊盘之间设有银浆层,位于散热焊盘周边设有若干个导电焊盘,所述导电焊盘和芯片通过一引线连接,所述散热焊盘远离芯片的一侧开有分隔槽,所述分隔槽宽度为0.1‑0.3mm,所述分隔槽将散热焊盘远离芯片的一侧等分分隔形成至少2块焊盘单体,所述分隔槽中填充有导热绝缘条。本实用新型通过分隔槽和导热绝缘条的设置,不仅能够减小锡膏使用量,降低发生短路的概率,还能保证散热焊盘的散热效果不受影响。
Description
技术领域
本实用新型涉及SMT用防短路DFN器件封装结构,属于无引脚封装技术领域。
背景技术
DFN封装在PCB板中应用很广,DFN封装的应用极大的推动了电子技术的发展。DFN封装具有优异的热性能,主要是因为封装底部有大面积散热焊,为了能有效地将热量从芯片传导到PCB上,PCB底部必须设计与之相对应的散热焊盘以及散热过孔,散热焊盘提供了可靠的焊接面积,散热过孔提供了散热途径;常规的DFN封装在PCB中的设计通常有一个大面积的散热焊盘,这个散热焊盘通常接地,虽然这个散热焊盘可以起到芯片散热的作用,但往往由于焊盘过大,在贴片(SMT)过程中刷锡过多会导致这个DFN封装中央大的散热焊盘与其他的小的导电焊盘的短路现象。
实用新型内容
本实用新型的目的是提供SMT用防短路DFN器件封装结构,通过分隔槽和导热绝缘条的设置,不仅能够减小锡膏使用量,降低发生短路的概率,还能保证散热焊盘的散热效果不受影响。
为达到上述目的,本实用新型采用的技术方案是:一种SMT用防短路DFN器件封装结构,包括位于环氧绝缘体中的散热焊盘、芯片和导电焊盘,所述芯片位于散热焊盘上,且所述芯片与散热焊盘之间设有银浆层,位于散热焊盘周边设有若干个导电焊盘,所述导电焊盘和芯片通过一引线连接,所述散热焊盘远离芯片的一侧开有分隔槽,所述分隔槽宽度为0.1-0.3mm,所述分隔槽将散热焊盘远离芯片的一侧等分分隔形成至少2块焊盘单体,所述分隔槽中填充有导热绝缘条。
上述技术方案中进一步改进的方案如下:
1. 上述方案中,所述导热绝缘条厚度不大于分隔槽槽深。
2. 上述方案中,所述导热绝缘条厚度小于分隔槽槽深。
3. 上述方案中,所述焊盘单体的面积不小于0.3*0.3mm2。
4. 上述方案中,所述导电焊盘和散热焊盘的间距为0.3mm。
由于上述技术方案的运用,本实用新型与现有技术相比具有下列优点:
1、本实用新型SMT用防短路DFN器件封装结构,在远离芯片一侧的散热焊盘表面上开设分隔槽,通过不同形状的分隔槽将散热焊盘远离芯片的一部分等分分割成至少两块焊盘单体,在划分成多个焊盘单体后,焊盘单体远离芯片一侧的表面积小于原散热焊盘远离芯片一侧的表面积,从而减少锡膏的使用量,进而有效控制散热焊盘和导电焊盘之间的短路现象;同时,在分隔槽中填充设置上导热绝缘条后,分隔槽部分不会填充上导热效果较差的环氧绝缘树脂,以保证散热焊盘部分的散热功能不受影响;另外,随着锡膏使用量的减少,还能降低贴片成本。
2、本实用新型SMT用防短路DFN器件封装结构,将导热绝缘条的厚度设置为小于分隔槽槽深,使得导热绝缘条不能充满分隔槽,从而在导热绝缘条远离芯片的一侧预留部分空间,此时,在进行贴片操作时,多余的部分锡膏能够进入分隔槽中,从而避免多余的锡膏向散热焊盘四周蔓延,而接触到导电焊盘,引起短路。
附图说明
附图1为本实用新型实施例1的DFN器件封装结构的结构示意图;
附图2为本实用新型实施例2的DFN器件封装结构的结构示意图。
以上附图中:1、散热焊盘;11、分隔槽;111、导热绝缘条;12、焊盘单体;2、银浆层;3、芯片;4、导电焊盘;5、引线;6、环氧绝缘体。
具体实施方式
实施例1:SMT用防短路DFN器件封装结构,参照附图1,包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4,所述芯片3位于散热焊盘1上,且所述芯片3与散热焊盘1之间设有银浆层2,位于散热焊盘1周边设有若干个导电焊盘4,所述导电焊盘4和芯片3通过一引线5连接,所述散热焊盘1远离芯片3的一侧开有分隔槽11,所述分隔槽11宽度为0.1-0.3mm,优选为0.2mm,所述分隔槽11将散热焊盘1远离芯片3的一侧等分分隔形成至少2块焊盘单体12,所述分隔槽11中填充有导热绝缘条111。
上述导热绝缘条111厚度等于分隔槽11槽深;
上述焊盘单体12的面积不小于0.3*0.3mm2,优选为0.3*0.3mm2;
上述导电焊盘4和散热焊盘1的间距为0.3mm。
实施例2:SMT用防短路DFN器件封装结构,参照附图2,包括位于环氧绝缘体6中的散热焊盘1、芯片3和导电焊盘4,所述芯片3位于散热焊盘1上,且所述芯片3与散热焊盘1之间设有银浆层2,位于散热焊盘1周边设有若干个导电焊盘4,所述导电焊盘4和芯片3通过一引线5连接,所述散热焊盘1远离芯片3的一侧开有分隔槽11,所述分隔槽11宽度为0.1-0.3mm,优选为0.2mm,所述分隔槽11将散热焊盘1远离芯片3的一侧等分分隔形成至少2块焊盘单体12,所述分隔槽11中填充有导热绝缘条111。
上述导热绝缘条111厚度小于分隔槽11槽深;
上述焊盘单体12的面积不小于0.3*0.3mm2,优选为0.3*0.3mm2;
上述导电焊盘4和散热焊盘1的间距为0.3mm。
采用上述SMT用防短路DFN器件封装结构时,其通过分隔槽11的设置,使散热焊盘1远离芯片3的一侧表面等分分隔形成多块焊盘单体12,减少了散热焊盘1部分贴片时与PCB的接触面积,从而减少了锡膏的使用量;随着锡膏使用量的减少,一方面,降低了锡膏从散热焊盘1蔓延到导电焊盘4的概率,有效的控制了焊盘单体12与导电焊盘4之间的短路现象,另一方面,还能降低贴装成本。
另外,由于分隔槽11的设置,在注塑封装时,环氧绝缘树脂会填充进分隔槽11中,导致散热焊盘1与PCB的接触导热面积缩小,而影响到其导热效果,因此,通过导热绝缘条111的设置,在保证散热焊盘1导热效果的同时,还能利用预留的分隔槽11部分容纳多余的部分锡膏,进一步降低发生短路的概率,改善贴片质量。
上述实施例只为说明本实用新型的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本实用新型的内容并据以实施,并不能以此限制本实用新型的保护范围。凡根据本实用新型精神实质所作的等效变化或修饰,都应涵盖在本实用新型的保护范围之内。
Claims (5)
1.一种SMT用防短路DFN器件封装结构,包括位于环氧绝缘体(6)中的散热焊盘(1)、芯片(3)和导电焊盘(4),所述芯片(3)位于散热焊盘(1)上,且所述芯片(3)与散热焊盘(1)之间设有银浆层(2),位于散热焊盘(1)周边设有若干个导电焊盘(4),所述导电焊盘(4)和芯片(3)通过一引线(5)连接,其特征在于:所述散热焊盘(1)远离芯片(3)的一侧开有分隔槽(11),所述分隔槽(11)宽度为0.1-0.3mm,所述分隔槽(11)将散热焊盘(1)远离芯片(3)的一侧等分分隔形成至少2块焊盘单体(12),所述分隔槽(11)中填充有导热绝缘条(111)。
2.根据权利要求1所述的SMT用防短路DFN器件封装结构,其特征在于:所述导热绝缘条(111)厚度不大于分隔槽(11)槽深。
3.根据权利要求2所述的SMT用防短路DFN器件封装结构,其特征在于:所述导热绝缘条(111)厚度小于分隔槽(11)槽深。
4.根据权利要求1所述的SMT用防短路DFN器件封装结构,其特征在于:所述焊盘单体(12)的面积不小于0.3*0.3mm2。
5.根据权利要求4所述的SMT用防短路DFN器件封装结构,其特征在于:所述导电焊盘(4)和散热焊盘(1)的间距为0.3mm。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201821959629.9U CN208923108U (zh) | 2018-11-27 | 2018-11-27 | Smt用防短路dfn器件封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201821959629.9U CN208923108U (zh) | 2018-11-27 | 2018-11-27 | Smt用防短路dfn器件封装结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN208923108U true CN208923108U (zh) | 2019-05-31 |
Family
ID=66712457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201821959629.9U Active CN208923108U (zh) | 2018-11-27 | 2018-11-27 | Smt用防短路dfn器件封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN208923108U (zh) |
-
2018
- 2018-11-27 CN CN201821959629.9U patent/CN208923108U/zh active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7960827B1 (en) | Thermal via heat spreader package and method | |
JP2019517735A (ja) | モールド経由の冷却チャネルを有する半導体デバイスアセンブリ | |
TWI590392B (zh) | 電子封裝件及其製法 | |
CN204834611U (zh) | 引线框架及其单元、半导体封装结构及其单元 | |
KR102284598B1 (ko) | 패키징된 반도체 다이에 대한 내열 확산을 위한 장치 및 방법 | |
WO2017041689A1 (zh) | 传感芯片封装组件和具有该传感芯片封装组件的电子设备 | |
US7153725B2 (en) | Strip-fabricated flip chip in package and flip chip in system heat spreader assemblies and fabrication methods therefor | |
CN103426839A (zh) | 半导体封装 | |
CN105489571A (zh) | 一种带散热片的半导体封装及其封装方法 | |
CN109585396A (zh) | 热耦合的层叠封装半导体封装 | |
CN101360393B (zh) | 嵌埋半导体芯片的电路板结构及其制法 | |
CN208970506U (zh) | 防短路的qfn封装结构 | |
CN208923108U (zh) | Smt用防短路dfn器件封装结构 | |
US11776917B2 (en) | Electronic package | |
CN203774286U (zh) | 一种带散热装置的pop封装 | |
CN208923104U (zh) | 基于qfn的芯片封装结构 | |
US8786075B1 (en) | Electrical circuit with component-accommodating lid | |
CN103413802B (zh) | 一种大功耗芯片封装结构 | |
CN208923105U (zh) | 表面贴装式半导体器件 | |
CN103560090B (zh) | 一种用于PoP封装的散热结构的制作方法 | |
CN206595249U (zh) | 承载大电流的sop器件封装结构 | |
CN205609518U (zh) | 一种超薄3d封装的半导体器件以及超薄3d封装的半导体器件的半成品 | |
US20050184365A1 (en) | High density lead arrangement package structure | |
CN203826369U (zh) | 一种半导体引线框架 | |
CN206532770U (zh) | 芯片封装的新型sop结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |