CN208806250U - A kind of semiconductor packages sealing structure - Google Patents
A kind of semiconductor packages sealing structure Download PDFInfo
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- CN208806250U CN208806250U CN201821628257.1U CN201821628257U CN208806250U CN 208806250 U CN208806250 U CN 208806250U CN 201821628257 U CN201821628257 U CN 201821628257U CN 208806250 U CN208806250 U CN 208806250U
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Abstract
The utility model discloses a kind of semiconductor packages sealing structures, including chip layer, substrate layer and board layer, the upper surface of the chip layer is fixedly connected with conductive layer, the upper surface of the conductive layer is fixedly connected with the lower surface of substrate layer, the lower surface of the chip layer is fixedly connected with heat-conducting layer, top in the middle part of the board layer is fixedly connected with heat dissipation electric connection layer, the upper surface of the heat dissipation electric connection layer is fixedly connected with the lower surface of heat-conducting layer, bottom on the substrate layer close to its end is fixedly connected with leg, functional electric connection layer is fixedly connected at the top of its end on the board layer, the upper surface of the function electric connection layer is mutually bonded with the lower surface of leg.The utility model improves the heat dissipation effect in encapsulating structure by the cooperation of above structure, prevents the temperature of chip interior and surrounding excessively high, guarantees the reliable and effective operation of chip.
Description
Technical field
The utility model relates to technical field of semiconductors, specially a kind of semiconductor packages sealing structure.
Background technique
With the fast development of wireless communication, automotive electronics and other consumer electronics products, microelectronic packaging technology to
Multi-functional, miniaturization, portable, high speed, low-power consumption and high reliability direction develop.Wherein, system in package (SIP,
SystemInaPackage) it is a kind of novel encapsulation technology, package area, existing multi-functional SIP envelope can be effectively reduced
Cartridge chip includes being bonded on one or more chips on the surface of the substrate.With the highly integrated of chip is encapsulated, the function of chip is encapsulated
The problem of rate is increasing, therefore chip cooling must be taken into consideration as one in encapsulation process.The heat that chip itself generates, is removed
It radiates outward at least partially through bottom substrate and weld pad outer, major heat is radiated by chip surface.Cause
This, existing chip package designs add heat dissipating housing generally on chip, and heat dissipating housing is pasted onto chip and base by Heat Conduction Material
On plate, encapsulation structure is formed.But since chip is surrounded by heat dissipating housing, chip is in sealed environment, heat dissipating housing
Not only has the function of heat dissipation, heat dissipating housing also has the function of assembling the heat that chip generates, and is not transferred to the external world by heat dissipating housing
Heat concentrate on heat dissipating housing encirclement sealed environment in, cause temperature with higher around chip, influence the work of chip
Performance.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor packages sealing structures, and it is simple, easy to use to have structure
The advantages of, solve the problems, such as that prior art heat dissipation effect is bad.
To achieve the above object, the utility model provides the following technical solutions: a kind of semiconductor packages sealing structure, including
Chip layer, substrate layer and board layer, the upper surface of the chip layer are fixedly connected with conductive layer, the upper surface of the conductive layer
It is fixedly connected with the lower surface of substrate layer, the lower surface of the chip layer is fixedly connected with heat-conducting layer, the board layer middle part
Top be fixedly connected with heat dissipation electric connection layer, the upper surface of the heat dissipation electric connection layer and lower surface of heat-conducting layer is fixed connects
It connects, the bottom on the substrate layer close to its end is fixedly connected with leg, the top of its close end on the board layer
It is fixedly connected with functional electric connection layer, the upper surface of the function electric connection layer is mutually bonded with the lower surface of leg.
Preferably, the board layer is pcb board.
Preferably, the conductive layer is for realizing being electrically connected between chip layer and substrate layer.
Preferably, the substrate layer is rigid substrate or transparent substrates.
Preferably, the rigid substrate is PCB substrate, glass substrate, metal substrate, semiconductor substrate or polymer matrix
Plate.
Preferably, the transparent substrates are unorganic glass substrate, pmma substrate or filter glass substrate.
Preferably, being electrically connected between the substrate layer and board layer may be implemented in the leg.
Compared with prior art, the utility model has the beneficial effects that the utility model passes through setting chip layer, substrate
Layer, board layer, conductive layer, heat-conducting layer, heat dissipation electric connection layer, leg and function electric connection layer, chip layer are arranged in substrate layer
On, chip layer top surface is opposite with substrate layer, has heat-conducting layer on chip layer bottom surface, can will be inside chip layer by heat-conducting layer
Heat is conducted into external environment or component, to effectively reduce chip layer internal heat, prevents chip layer from overheating, and is solved
The problem of heat dissipating housing surrounds chip layer in the prior art, and the heat that chip layer generates does not distribute not go out.
Detailed description of the invention
Fig. 1 is the structural schematic diagram that the utility model substrate layer overlooks axonometric drawing；
Fig. 2 is the structural schematic diagram that the utility model substrate layer looks up axonometric drawing；
Fig. 3 is the structural schematic diagram of the utility model substrate layer front view；
Fig. 4 is the structural schematic diagram of the utility model leg and function electric connection layer front view.
In figure: 1- chip layer, 2- substrate layer, 3- board layer, 4- conductive layer, 5- heat-conducting layer, 6- heat dissipation electric connection layer, 7-
Leg, 8- function electric connection layer.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
The utility model provides a kind of technical solution referring to FIG. 1 to FIG. 4: a kind of semiconductor packages sealing structure, including
Chip layer 1, substrate layer 2 and board layer 3, chip layer 1 with a thickness of 100~200 microns, substrate layer 2 is rigid substrate or thoroughly
Photopolymer substrate, rigid substrate are PCB substrate, glass substrate, metal substrate, semiconductor substrate or polymeric substrates, and transparent substrates are
Unorganic glass substrate, pmma substrate or filter glass substrate, board layer 3 are pcb board, and the upper surface of chip layer 1 is solid
Surely be connected with conductive layer 4, conductive layer 4 with a thickness of 10 microns~20 microns, the upper surface of conductive layer 4 and the following table of substrate layer 2
Face is fixedly connected, and for realizing being electrically connected between chip layer 1 and substrate layer 2, the lower surface of chip layer 1 is fixed to be connected conductive layer 4
Be connected to heat-conducting layer 5, heat-conducting layer 5 with a thickness of 3 microns~8 microns, when the work of chip layer 1 causes to generate heat inside chip layer 1
When, heat-conducting layer 5 can conduct 1 internal heat of chip layer into external environment or other devices, so that chip layer 1
Internal heat reduces, and avoids the occurrence of the problem of chip layer 1 overheats, and the top at 3 middle part of board layer is fixedly connected with heat dissipation and is electrically connected
Layer 6 is connect, the upper surface of heat dissipation electric connection layer 6 is fixedly connected with the lower surface of heat-conducting layer 5, the heat warp generated inside chip layer 1
It is transferred in heat dissipation electric connection layer 6 by heat-conducting layer 5, therefore the heat generated inside chip layer 1 can be carried out via board layer 3
Heat dissipation, the good heat dissipation effect of board layer 3 guarantee to guarantee that the heat inside chip layer 1 is timely and effectively conducted
Chip layer 1 is effectively run, and the material of heat dissipation electric connection layer 6 is one of tin, gold or tungsten or a variety of, function electric connection layer 8
Material be also one of tin, gold or tungsten or a variety of, in the present embodiment, heat dissipation electric connection layer 6 material be tin, heat-conducting layer 5
It is in contact by way of eutectic bond with heat dissipation electric connection layer 6, the bottom on substrate layer 2 close to its end is fixedly connected with weldering
Foot 7, leg 7 with a thickness of 150~250 microns, be fixedly connected with functional electrical connection at the top of its end on board layer 3
Layer 8, the material of electric connection layer 6 is identical can also be different for the material of function electric connection layer 8 and heat dissipation, and in the present embodiment, heat dissipation is electric
The material of articulamentum 6 is tin, and the upper surface of function electric connection layer 8 is mutually bonded with the lower surface of leg 7, specifically, passes through welding
Bonding technology, so that heat-conducting layer 5 is bonded with heat dissipation 6 phase of electric connection layer, needs so that institute's leg 7 is bonded with 8 phase of function electric connection layer
To illustrate that can also realize that heat-conducting layer 5 is electrically connected with heat dissipation using the methods of ultrasonic thermocompression, thermal compression welding or ultrasonic wire bonding
The bonding of 6 phase of layer is connect, so that heat-conducting layer 5 is in contact with heat dissipation electric connection layer 6, so that between heat-conducting layer 5 and heat dissipation electric connection layer 6
Bonded interface has excellent heating conduction, and leg 7 may be implemented being electrically connected between substrate layer 2 and board layer 3, carry out
Before solder bonds technique, flushed at the top of 8 top of function electric connection layer and heat dissipation electric connection layer 6, and be higher than at the top of leg 7 thermally conductive
5 top of layer；During being bonded leg 7 with 8 phase of function electric connection layer by solder bonds technique, the thickness meeting of leg 7
Reduce, therefore when leg 7 is electrically connected with function electric connection layer 8, phase between heat-conducting layer 5 and heat dissipation electric connection layer 6 may be implemented
Bonding, i.e. heat-conducting layer 5 are in contact with heat dissipation electric connection layer 6.
Working principle: the semiconductor packages sealing structure is in use, pass through setting chip layer 1, substrate layer 2, board layer
3, conductive layer 4, heat-conducting layer 5, heat dissipation electric connection layer 6, leg 7 and function electric connection layer 8, chip layer 1 are arranged on substrate layer 2,
1 top surface of chip layer and substrate layer 2 are opposite, have heat-conducting layer 5 on 1 bottom surface of chip layer, can will be in chip layer 1 by heat-conducting layer 5
The heat in portion is conducted into external environment or component, to effectively reduce 1 internal heat of chip layer, prevents 1 mistake of chip layer
Heat solves in the prior art the problem of heat dissipating housing surrounds chip layer 1, and the heat that chip layer 1 generates does not distribute not go out.
While there has been shown and described that the embodiments of the present invention, for the ordinary skill in the art,
It is understood that these embodiments can be carried out with a variety of variations in the case where not departing from the principles of the present invention and spirit, repaired
Change, replacement and variant, the scope of the utility model is defined by the appended claims and the equivalents thereof.
Claims (7)
1. a kind of semiconductor packages sealing structure, it is characterised in that: including chip layer (1), substrate layer (2) and board layer (3),
The upper surface of the chip layer (1) is fixedly connected with conductive layer (4), under the upper surface and substrate layer (2) of the conductive layer (4)
Surface is fixedly connected, and the lower surface of the chip layer (1) is fixedly connected with heat-conducting layer (5), the top in the middle part of the board layer (3)
Portion is fixedly connected with heat dissipation electric connection layer (6), and the upper surface of heat dissipation electric connection layer (6) and the lower surface of heat-conducting layer (5) are solid
Fixed to connect, the bottom on the substrate layer (2) close to its end is fixedly connected with leg (7), close on the board layer (3)
It is fixedly connected at the top of its end functional electric connection layer (8), upper surface and leg (7) of the function electric connection layer (8)
Lower surface is mutually bonded.
2. a kind of semiconductor packages sealing structure according to claim 1, it is characterised in that: the board layer (3) is
Pcb board.
3. a kind of semiconductor packages sealing structure according to claim 1, it is characterised in that: the conductive layer (4) is used for
Realize being electrically connected between chip layer (1) and substrate layer (2).
4. a kind of semiconductor packages sealing structure according to claim 1, it is characterised in that: the substrate layer (2) is hard
Property substrate or transparent substrates.
5. a kind of semiconductor packages sealing structure according to claim 4, it is characterised in that: the rigid substrate is PCB
Substrate, glass substrate, metal substrate, semiconductor substrate or polymeric substrates.
6. a kind of semiconductor packages sealing structure according to claim 4, it is characterised in that: the transparent substrates are inorganic
Glass substrate, pmma substrate or filter glass substrate.
7. a kind of semiconductor packages sealing structure according to claim 1, it is characterised in that: the leg (7) can be real
Being electrically connected between the existing substrate layer (2) and board layer (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821628257.1U CN208806250U (en) | 2018-10-08 | 2018-10-08 | A kind of semiconductor packages sealing structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821628257.1U CN208806250U (en) | 2018-10-08 | 2018-10-08 | A kind of semiconductor packages sealing structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208806250U true CN208806250U (en) | 2019-04-30 |
Family
ID=66238824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821628257.1U Active CN208806250U (en) | 2018-10-08 | 2018-10-08 | A kind of semiconductor packages sealing structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208806250U (en) |
-
2018
- 2018-10-08 CN CN201821628257.1U patent/CN208806250U/en active Active
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