CN208795371U - A kind of multi-photon coincidence counting device - Google Patents

Abstract

The utility model discloses a kind of multi-photon coincidence counting devices, the device concurrently carries out time label and event matches to the pulse in each channel using multi-phase clock TDC and numerical aperture comparator, and it is screened in real time to result is met, to mitigate subsequent data transmissions, storage and the pressure of analysis, at the same also devise Channel scan and to partially meet result carry out real-time statistic analysis function.These designs are most of to be realized inside a piece of FPGA, and the port number for supporting the two dimension in time and channel to meet, and can support reaches up to a hundred, and compatibility and scalability are good.

Description

A kind of multi-photon coincidence counting device

Technical field

The utility model relates to photon coincidence counting field more particularly to a kind of multi-photon coincidence counting devices.

Background technique

It is a kind of peculiar quantum appearance that multi-photon, which tangles, in research quantum simulator, quantum error correction and quantum mould It is all indispensable resource in quasi- research.Number of photons is more, and the freedom degree of single photon is bigger, multi-photon system processing letter The ability of breath is stronger, and in newest experiment progress, ten tangling for photon are achieved.On the other hand, photon is also real A kind of very promising medium of existing quantum computer, light quantum computer also become the research direction of an awfully hot door, especially Be by Bose sample for the purpose of the computing capability of light quantum computer have been over early stage classic computer, the photon being related to Number has reached 5.It tangles and in the light quantum information researches such as light quantum calculating, is required to logical from multiple detections in multi-photon The photon signal in road carries out photon statistics analysis, and common is exactly coincidence counting.

It is tangled in experiment in multi-photon, this Quantum Properties will be tangled and be converted into the amount needs that our world of experience can be observed To number of photons carry out counting statistics, due to tangle be a kind of more bodies process, so count be coincidence counting.Coincidence counting device Function is that meeting between two or more signals is judged and counted.Multi-photon tangles and light quantum calculating field The coincidence counting technique requirement signal input channel being related to is very more, and the type sum met is very big and will be to all symbols Closing situation will be counted, and have very big difference with traditional.Recently as the rapid advances of light quantum information research, Also there are many new multi-photon coincidence counting techniques, to solve various new problems.

2005, Gaertner et al. proposed the scheme of address of cache, and shown in structural block diagram such as Fig. 1 (a), system is by according with Close probe unit, fifo buffer (FIFO), microcontroller (Micro controller) and on piece random access Memory (RAM) composition.Meet shown in probe unit detailed structure view such as Fig. 1 (b), is patrolled its working principle is that input signal is taken Volume or after signal as sample trigger, the pattern that samples as counter address caching to FIFO.

2015, BYUNG KWON PARK et al. also achieved the counter that eight bodies meet with door on FPGA.Its is whole Shown in body scenario-frame block diagram such as Fig. 2 (a), the system integration is on FPGA, wherein include time delay module (Internal Delay), Pulse shaping module (Pulse Reshaping) meets signal generator (Coincidence Signal Generator), meter Number device (Counter) and processor (Processor), FPGA turn USB by serial ports and communicate with PC.Meet the knot of signal generator Shown in structure such as Fig. 2 (b), principle is to gate multi input and door by Port Multiplier to determine to meet configuration, each multi input and door Corresponding one kind meets type.

With the fast development of experimental technique, number, photon detection port number and the light-source brightness of entangled photons all can not It is disconnected to increase.The experiment channel number of eight photon entanglements has reached 16, meets type up to 2¹⁶- 1, reject some meaningless symbols It closes, meeting type at least is also to increase with number of photons and be in geometric growth；Meanwhile the brightness of entangled light source is (in the unit time The number of entangled photons) also reach single channel counting rate megahertz, the level that ten megahertzs of system event rate.2016, patent CN201610961414.X discloses a kind of multi-photon coincidence counting device based on programmable logic device, the great Rong based on DDR Amount, can support to multiple coincidence type while count, and using shunting mechanism solve DDR read or write speed not enough ask Topic, improves the incident rate for meeting system.

However, technological progress be it is very fast, carried out number of photons at present and reached more than ten, photon detection channel The light quantum experiment that number is up to a hundred.And there is a kind of new experimental program to need to make full use of the Quantum Properties of photon now Realize the coincidence counting being distributed between the photon that multiple moment reach on different channels, this is not only needed as under classical scenario Met between different channels, also requires to define different time windows on each channel, between these time windows Met, that is to say, that meet generation on time and two, space dimension, we term it two dimensions to meet, at present also Which kind of multi-photon to meet technology without can be well solved this problem.

In addition, these multi-photon coincidence counting techniques before require to solve the problems, such as one it is common, seek into The light pulse arrival time on all channels is aligned together before row coincidence counting, alignment precision, which is less than, meets window Size, and if the device on signal link has been replaced, it is necessary to re-start alignment.The photon of current multi-photon experiment Detection channels number has reached dozens of, and meeting window also will be to nanosecond even magnitude of subnanosecond, the work of pulse daley alignment More seem difficult and important.A long time ago, when port number is also fewer, people are by adjusting cable length and with showing Wave device, which is tested, can complete the work of pulse daley alignment, and later people joined fine adjustable prolong on each channel Shi Danyuan to allow this work to carry out automatically in program-controlled mode, and adjustable time delay unit has temperature drift problems, and Many logical resources can be consumed.

Coincidence Logic Unit product from Universal Quantum Devices (UQD) company is adopted Technology is met based on time label (Time tagged) with a kind of, it may not be necessary to fine delay alignment.By to using The analysis of handbook may can be by the upgrading of software in PC machine although it does not have perfect two dimension and meets ability now On realize off-line manner and be distributed in meeting between the photon that multiple moment reach on different channels and count.But it is used Time-to-digit converter (TDC) consume excessive logical resource, port number is limited, is currently only 16 channels, and future is also difficult full The demand in nearly hundred channel of foot.In addition it, which meets and counts, is realized in PC machine, is not easy to see reality when testing When as a result, being debugged to the optical path before testing and system mode monitoring when testing is all unfavorable.Photon can be detected To losing before, so having many meets event comprising a small amount of photon, their time label can occupy a large amount of Transmission bandwidth and memory space usually need to filter them in real time when testing, and the UQD seen at present is produced Product do not accomplish this point well.Using the filtering method traded off, i.e., the photon time in the regular hour marks for they Reach some quantity just to be transmitted later.This filter method is not direct according to result progress is met, it is possible that having Mistake when meeting in particular for progress two dimension, and cannot achieve some more complicated filterings.In short, this production Product do not meet scene exclusively for two dimension and do that more consideration is given to and its implementation is not disclosed.

Utility model content

The purpose of the utility model is to provide a kind of multi-photon coincidence counting devices, are distributed in realization more on different channels The coincidence counting between photon that a moment reaches, and eliminate and largely lack the time label that body meets as caused by photon loss To the occupation problem of transmission bandwidth and memory space, it is provided simultaneously with certain real time monitoring capa, port number is allow to compare appearance Easily reach channels up to a hundred.

The purpose of this utility model is achieved through the following technical solutions:

A kind of multi-photon coincidence counting device, comprising: input processing module, time mark module, data cache module, thing Part meets module, result treatment module and control module；Wherein:

Input processing module, time mark module and data cache module are sequentially connected；The data cache module and thing Part meets module and result treatment module is connected；The event matches module is also connected with result treatment module；At the result Reason module is connected with control module.

Time measurement function in the time mark module is used to be realized based on multi-phase clock TDC scheme, or is used High speed serial parallel exchange device is realized；

According to multi-phase clock TDC scheme is based on, then it includes the N number of more of quantity identical as input processing module port number Phase clock TDC and a phaselocked loop, the phaselocked loop are connected with each multi-phase clock TDC.

The data cache module includes N number of fifo module, and the event matches module includes that N number of numerical aperture compares Device；The multi-phase clock TDC, the fifo module and the one-to-one connection of numerical aperture comparator.

The input processing module is by one piece or the realization of muti-piece sub-circuit board, the time mark module, the data The piece of cache module, the event matches module and the result treatment module all by the FPGA on one piece of main control board is domestic-investment It realizes in source；

It realizes one piece of input processing module or muti-piece sub-circuit board is directly inserted on the main control board or logical Backboard is crossed to link together with the main control board；If input processing module is realized by muti-piece sub-circuit board, muti-piece electricity Signal connection between road plate and main control board uses star structure；

The control module is realized using embedded processing unit or PC.

The result treatment module includes: data multiplexer, the first count control module, the first dual port RAM, the first screening Device, the second screening washer, the second count control module, the second dual port RAM, WISHBONE bus and transmission control module；Wherein:

The data multiplexer first port is connected with the data cache module, the second end of the data multiplexer The first port of mouth, first count control module and first dual port RAM is sequentially connected；

The first port of first screening washer and the first port of second screening washer with the event matches mould Block is connected, the first end of the second port of second screening washer, second count control module and second dual port RAM Mouth is sequentially connected；

The second port of first dual port RAM, the second port of second dual port RAM and first screening washer Second port be connected by the WISHBONE bus with the first port of the transmission control module；

The second port of the transmission control module is connected with control module.

It mainly has the advantages that it can be seen from above-mentioned technical solution provided by the utility model

1) the time label that pulse is realized using multi-phase clock TDC or high speed serial parallel exchange, so that the increase of port number Consumption to resource is simultaneously few, is very suitable to the scene more than port number.

2) functions such as all time labels, event matches and result treatment, monitoring, mirror can be realized in monolithic FPGA Increasing very rich with I/O pin in fpga logic resource capacity, this is very suitable to, and photon detection channel is very more to answer With can support channels up to a hundred.

3) functions such as all time labels, event matches and result treatment, monitoring, mirror can be realized in monolithic FPGA Increasing very rich with I/O pin in fpga logic resource capacity, this is very suitable to, and photon detection channel is very more to answer With current technology level can support channels up to a hundred.

4) it uses sub-circuit board to be responsible for input processing, be responsible for the framework met by the main control board of core of FPGA, it is non- Often it is suitble to system expanding to channels up to a hundred, and upgrades very convenient, there is good scalability and reliability.

5) fpga logic used by can realize have fine in the various mainstream fpga chips of major FPGA manufacturer Compatibility.

Detailed description of the invention

It, below will be to required in embodiment description in order to illustrate more clearly of the technical solution of the utility model embodiment The attached drawing used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the utility model Example, for those of ordinary skill in the art, without creative efforts, can also be according to these attached drawings Obtain other accompanying drawings.

Fig. 1 is the address-mapping schemes schematic diagram that the utility model background technique provides；Wherein, (a) is structural block diagram； It (b) is to meet probe unit detailed structure view；

Fig. 2 be the utility model background technique provide on FPGA with door realize eight body coincidence counting devices signal Figure；Wherein, (a) is overall plan structural block diagram；It (b) is to meet signal generator structure chart；

Fig. 3 is a kind of schematic diagram of multi-photon coincidence counting device provided by the embodiment of the utility model；

Fig. 4 is for multi-photon coincidence counting device provided by the embodiment of the utility model and its in a typical quantum optices Application scenarios schematic diagram in experiment.

Specific embodiment

Below with reference to the attached drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out clear Chu is fully described by, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole realities Apply example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work The every other embodiment obtained, belongs to the protection scope of the utility model.

The utility model embodiment provides a kind of multi-photon coincidence counting device, as shown in figure 3, it specifically includes that input Processing module, time mark module, data cache module, event matches module, result treatment module and control module；Wherein:

Input processing module, time mark module and data cache module are sequentially connected；The data cache module and thing Part meets module and result treatment module is connected；The event matches module is also connected with result treatment module；At the result Reason module is connected with control module.

Further, the time measurement function in the time mark module is used is realized based on multi-phase clock TDC scheme, Or it is realized using high speed serial parallel exchange device；

According to multi-phase clock TDC scheme is based on, then it includes the N number of more of quantity identical as input processing module port number Phase clock TDC and a phaselocked loop, the phaselocked loop are connected with each multi-phase clock TDC.

Further, the data cache module includes N number of fifo module, and the event matches module includes N number of number Window comparator；The multi-phase clock TDC, the fifo module and the one-to-one connection of numerical aperture comparator.

Further, the input processing module is realized by one piece or muti-piece sub-circuit board, the time mark module, The data cache module, the event matches module and the result treatment module are all by the FPGA on one piece of main control board Piece in resource realize；

It realizes one piece of input processing module or muti-piece sub-circuit board is directly inserted on the main control board or logical Backboard is crossed to link together with the main control board；If input processing module is realized by muti-piece sub-circuit board, muti-piece electricity Signal connection between road plate and main control board uses star structure；

The control module is realized using embedded processing unit or PC.

Further, the result treatment module includes: data multiplexer, the first count control module, the first twoport RAM, the first screening washer, the second screening washer, the second count control module, the second dual port RAM, WISHBONE bus and transmission control Module；Wherein:

The data multiplexer first port is connected with the data cache module, the second end of the data multiplexer The first port of mouth, first count control module and first dual port RAM is sequentially connected；

The first port of first screening washer and the first port of second screening washer with the event matches mould Block is connected, the first end of the second port of second screening washer, second count control module and second dual port RAM Mouth is sequentially connected；

The second port of first dual port RAM, the second port of second dual port RAM and first screening washer Second port be connected by the WISHBONE bus with the first port of the transmission control module；

The second port of the transmission control module is connected with control module.

The structure of above-mentioned apparatus in order to facilitate understanding, below for the specific implementation of the modules in above-mentioned apparatus And its function and principle do detailed introduction；However, it is desirable to which, it is emphasized that the introduction below for function or principle is intended merely to It is easy to understand, specific restriction not is done to modules.It will be understood by those skilled in the art that the modules to be introduced It can be realized by conventional device or circuit, the utility model only protects the composed structure of above-mentioned apparatus, specific module Inside composed structure, but the function of device, each module is not protected.

1, input processing module.

In the utility model embodiment, the input processing module, for completing pretreatment operation in all input channels, It exports pulse and is connected to the time mark module.The input processing module is realized by one piece or muti-piece sub-circuit board.

2, time mark module.

In the utility model embodiment, the time measurement function in the time mark module, which uses, is based on multi-phase clock TDC scheme is realized, or is realized using high speed serial parallel exchange device；

According to based on multi-phase clock TDC (multi-phase clock when it is m- number conversion) scheme, then it includes with input processing The N number of multi-phase clock TDC and a phaselocked loop of the identical quantity of module channels number；The phaselocked loop is for believing periodic markings Number several frequencys multiplication are carried out, obtains the multi-phase clock of high frequency, each multi-phase clock TDC is under the action of the multi-phase clock, to input The rising edge arrival time of signal does not measure with the difference with particular reference to the moment, obtains digitized timestamp data； It is described at the time of with reference to the moment be periodic markings signal or some fixation, require when measurement the dead time to be less than setting mark Standard, and the useful pulse continuously reached cannot be missed.

Multi-phase clock TDC is a kind of common Method Of Time Measurement.In the utility model embodiment, it is by fpga chip Internal phaselocked loop carries out 4 frequencys multiplication to externally input 76MHz reference clock, and generates 8 phase clocks, is then used in 8 phase clocks Input pulse is sampled, equivalent sample rate is 76MHz × 4 × 8=2432MHz, and the sampling interval is less than 0.5ns, is met The requirement of common light quantum experiment.The multi-phase clock TDC largest benefit realized in this way is to occupy considerably less money Source can reach a medium time resolution, it is easy to can be achieved in the FPGA of a common intermediate density Hundred channels are highly suitable for meeting based on the multi-photon that the time marks.The multi-phase clock TDC's realized in this way Another is advantageous in that the dead time is the sampling interval, is less than 0.5ns in this example, this is very beneficial for handling answering for high incident rate With the maximum incident rate for enabling system to handle usually is determined by data transfer bandwidth, and in this case, it is the available bands of USB interface It is wide.The TDC realized in this way is also an advantage that be exactly that can carry out time mark to rising edge of a pulse and failing edge Note.

3, data cache module.

In the utility model embodiment, the data cache module includes N number of fifo module, is mainly used for from each Timestamp data on channel is cached.

4, event matches module.

In the utility model embodiment, the event matches module can be defined for each channel relative to the reference moment One or more time window, and will from the timestamp data of the data cache module pass through numerical aperture comparator It is compared respectively with these time windows, to obtain relative in same each time window with reference to each channel at moment Whether there is pulse along occurring as a result, namely meeting result；Result will be met to encode with required rule uniquely to know Not every kind meets as a result, then the result that meets after coding is given the result treatment module and handled.

The event matches module includes N number of numerical aperture comparator.

In the utility model embodiment, the multi-phase clock TDC, the fifo module, the numerical aperture comparator Quantity is all consistent with port number, i.e., be between each channel it is independent, can independently and concurrently carry out time label, buffering and Time window meets.

5, result treatment module.

In the utility model embodiment, the result that meets inscribed when result treatment module is to each reference is screened, And result is transmitted to control module；The reason of being screened is because with the time window quantity on port number and each channel Increase, every two can be big in the extreme with reference to the type that meets obtained during the moment, and meeting resulting data volume also can be non- Chang great, screening operation reject the result that meets for not needing to be concerned about, to mitigate the pressure of data transmission, storage and off-line analysis； Result treatment module can also carry out real-time counting statistics to selected several results that meet for meeting type, so as to rapidly Assessment meets situation；Result treatment module can also obtain the time reference numerals in one or more channel from data cache module According to statistics with histogram being carried out respectively according to channel, for analyzing and monitoring the distribution of each channel pulse arrival time.

Fig. 3 is also referred to, the result treatment module includes: data multiplexer, the first count control module, the first twoport RAM, the first screening washer, the second screening washer, the second count control module, the second dual port RAM, WISHBONE bus and transmission control Module；First screening washer realizes real-time and accurate screening to event matches result, leaves behind those and interested meets thing Example, to reduce the pressure analyzed subsequent transmission bandwidth, memory space and data.The screening conditions of first screening washer can basis It needs to flexibly set, generally few body as caused by photon loss can at least be met and be screened out, this high number met. It can also can not occur in principle but undesirable by current conditions and what is occurred meet and remove some.Data multiplex Device, the first count control module, the first dual port RAM realize Annual distribution measurement and monitoring module together, can be to being gated All pulse arrival times are for statistical analysis on road, obtain the position that photon occurs on each channel, and then obtain outgoing event Meet the time window setting parameter of module.And the second screening washer, the second count control module, the second dual port RAM then may be implemented To the real-time statistics function of meeting result.Due to the limited storage space inside FPGA, modern light quantum experiment institute can not be saved Some meets the counting of result type, and part can only be selected by the second screening washer and meets the such real-time statistics of result progress.? In the utility model embodiment, the second screening washer support select can be located at same or different channel on 8 time windows into Row real-time statistic analysis.To partially meet result carry out real-time statistic analysis ability for experiment build before optical path debugging with And the Stateful Inspection during experiment progress is highly useful.

Specifically:

The data multiplexer, the timestamp data selection in N number of channel for exporting data cache module is wherein Give first count control module in an interested channel；

First count control module is read on first dual port RAM using obtained timestamp data as address Value and write back the first dual port RAM raw address after adding 1；

First dual port RAM is used for the number that timestamp data is that index saves that the timestamp data occurs Analysis and the distribution for monitoring selected channel pulse arrival time, and when starting, the content of first dual port RAM is cleared；

First screening washer, the result that meets for exporting to the event matches module are sieved according to specified conditions Choosing, and store；

Second screening washer, the result that meets for exporting to the event matches module are sieved according to specified conditions Choosing, obtains the result for monitoring in real time；

Second count control module reads second twoport using the selection result of second screening washer as address Value on RAM simultaneously writes back the second dual port RAM raw address after adding 1；

Second dual port RAM is with time that the selection result of second screening washer is that index saves that the selection result occurs Number, for carrying out real-time counting statistics to selected several results that meet for meeting type, and when starting, described second pair The content of mouth RAM is cleared；

The WISHBONE bus by the transmission control module and first dual port RAM, second dual port RAM with And first screening washer connects, and the transmission control module is enabled to directly read the data of these three modules；

The transmission control module gives the output of result treatment module for controlling the coffret outside FPGA The control module.

6, control module.

In the utility model embodiment, there are the control module scanning, monitoring and data to acquire three kinds of operational modes, point Do not make the corresponding number for reading first dual port RAM, second dual port RAM and first screening washer of transmission control module According to；

In scanning-mode it, the data multiplexer for controlling the result treatment module successively selects each channel, each The channel dwell regular hour, then by reading the first dual port RAM content of result treatment module to obtain in respective channel Pulse arrival time distribution situation, according to analysis peak condition obtain respective channel time window setting value；

In the monitoring mode, control the desired monitoring of the second screening washer selection of the result treatment module meets type, Then the required distribution situation for meeting type monitored is obtained by reading the content of the second dual port RAM；

Under data acquisition scheme, the result for reading first screening washer is analyzed and is saved.

Above-mentioned Three models can be selected according to actual needs: 1) when the scan mode is selected, its role is to Determine the position of interest pulse, implementation is that the first count control module selects all the way from the data of the road N TDC FIFO As the address of the first dual port RAM, counting therein is read, adds 1 and writes back, the counting initial value of all address rams is 0.The The data of one dual port RAM are read by USB transmission control module by WISHBONE bus, and are transmitted to via external USB interface Control module.2) when selecting monitoring mode, its role is to provide, counting rate is higher to be met as a result, its implementation is will The bound of the road M data fifo and M window comparator in the road N is less than or equal to the upper bound then ratio than size, if more than lower bound Special position is ' 1 ', is otherwise ' 0 ', finally generates the data of M bit, the second count control module is using the M bit data as the The address of two dual port RAMs reads counting therein, adds and write back together, and the counting initial value of all address rams is 0；Second twoport The data of RAM are read by USB transmission control module by WISHBONE bus, and are transmitted to control mould via external USB interface Block.3) when digital modeling is adopted in selection, its role is to provide to meet that body number is higher to be met as a result, its implementation is by the road N The bound of data fifo and N number of window comparator is than size, and if more than lower bound, less than or equal to the upper bound, then the bit is ' 1 ', Otherwise it is ' 0 ', finally generates the data of N bit, which is read by USB transmission control module by WISHBONE bus, and Control module is transmitted to via external USB interface.

In the utility model embodiment, related specific value is that citing is not construed as limiting；Illustratively, above-mentioned In embodiment, it can be applied in the experiment of 12 photon entanglements, there is 24 single-photon detectors, i.e., above-mentioned N=24.

Illustratively, fpga chip can select XILINX company SPARTAN-6 XC6SLX16-2CSG324C, USB to connect Mouth selects the CY7C68013A of CYPRESS company.Each device parameters can be adjusted flexibly according to experimental program, for example, selection 7 Series FPGA of a new generation of XILINX company, serial communication such as kilomega network of the bandwidth in 10MBps or more.

In the utility model embodiment, the time mark module, the data cache module, the event matches module And the result treatment module is all realized by resource in the piece of the FPGA on one piece of main control board；

It realizes one piece of input processing module or muti-piece sub-circuit board is directly inserted on the main control board or logical Backboard is crossed to link together with the main control board；If input processing module is realized by muti-piece sub-circuit board, muti-piece electricity Signal connection between road plate and main control board uses star structure；

The control module is realized using embedded processing unit or PC, is able to carry out high speed with the main control board Data communication.

In addition, the main control board, sub-circuit board can be made into the form of common standard PC case plug-in card, it is inserted into certainly On the backboard of definition.

As shown in figure 4, for entire coincidence counting device and its application scenarios in a typical quantum optices experiment Schematic diagram；In Fig. 4, dotted arrow is optical signal, other arrows are electric signal.Laser (laser) is incident to optical system In (Optical System), several entangled photons are generated, after a series of optical manipulation, are being spatially separated into N A optical path is received by N number of single-photon detector respectively, after being converted into the road N electric pulse, is sent to several pieces of sub-circuit boards and carries out electricity The operations such as flat turn is changed, burr removes, polarity controls and channel is enabled, then give fpga chip on main control board through backboard Common I/O pin.What laser provided gives with the 76MHz electric pulse of laser pulse synchronization via the clock dedicated foot of FPGA Phaselocked loop inside fpga chip.

From fig. 4, it can be seen that the utility model embodiment is mainly by several pieces of sub-circuit boards, using fpga chip as core Main control board, and PC machine (control module) composition of operation control program.Sub-circuit board and main control board pass through backboard It is connected, main control board is connected by USB interface with PC machine.Main control board and sub-circuit board are all made into standard 3U crate plug-in unit Form, be inserted into the 3U high of standard, in 19 inches wide, 14 slots cabinet, connected together by oneself defining backboard.Sub- electricity The quantity of road plate is depending on photon detection port number N and the port number M that can handle of every piece of sub-circuit board in total.Usual M is 8, the in this way standard PC case for 14 slots have a slot to need to be used to insert main control board, and remaining 13 slots can insert sub- electricity Road plate can realize maximum 104 channels in a cabinet in this way.

Fpga chip contains a large amount of programmable logic resource, however only when user is organically mutual by these logical resources Connection is even integral, could complete specific task.The fpga logic of the utility model includes time mark module (multi-phase clock TDC, phaselocked loop), data buffering module (FIFO), (data are more for event matches module (window comparator) and result treatment module Road device, the first count control module, the first dual port RAM, the first screening washer, the second screening washer, the second count control module, second Dual port RAM, WISHBONE bus and USB transmission control module).

The above scheme of the utility model embodiment, mainly obtain it is following the utility model has the advantages that

1) the time label that pulse is realized using multi-phase clock TDC or high speed serial parallel exchange, so that the increase of port number Consumption to resource is simultaneously few, is very suitable to the scene more than port number.

2) functions such as all time labels, event matches and result treatment, monitoring, mirror can be realized in monolithic FPGA Increasing very rich with I/O pin in fpga logic resource capacity, this is very suitable to, and photon detection channel is very more to answer With can support channels up to a hundred.

3) functions such as all time labels, event matches and result treatment, monitoring, mirror can be realized in monolithic FPGA Increasing very rich with I/O pin in fpga logic resource capacity, this is very suitable to, and photon detection channel is very more to answer With current technology level can support channels up to a hundred.

4) it uses sub-circuit board to be responsible for input processing, be responsible for the framework met by the main control board of core of FPGA, it is non- Often it is suitble to system expanding to channels up to a hundred, and upgrades very convenient, there is good scalability and reliability.

5) fpga logic used by can realize have fine in the various mainstream fpga chips of major FPGA manufacturer Compatibility.

The preferable specific embodiment of the above, only the utility model, but the protection scope of the utility model is not It is confined to this, anyone skilled in the art can readily occur in the technical scope that the utility model discloses Change or replacement, should be covered within the scope of the utility model.Therefore, the protection scope of the utility model should Subject to the scope of protection of the claims.

Claims (5)

1. a kind of multi-photon coincidence counting device characterized by comprising input processing module, time mark module, data are slow Storing module, event matches module, result treatment module and control module；Wherein:

Input processing module, time mark module and data cache module are sequentially connected；The data cache module and event accord with It molds block and result treatment module is connected；The event matches module is also connected with result treatment module；The result treatment mould Block is connected with control module.

2. a kind of multi-photon coincidence counting device according to claim 1, which is characterized in that in the time mark module Time measurement function use based on multi-phase clock TDC scheme realize, or using high speed serial parallel exchange device realize；

According to multi-phase clock TDC scheme is based on, then it includes when N number of multiphase of quantity identical as input processing module port number Clock TDC and a phaselocked loop, the phaselocked loop are connected with each multi-phase clock TDC.

3. a kind of multi-photon coincidence counting device according to claim 2, which is characterized in that the data cache module packet N number of fifo module is included, the event matches module includes N number of numerical aperture comparator；The multi-phase clock TDC, the FIFO Module and the one-to-one connection of numerical aperture comparator.

4. a kind of multi-photon coincidence counting device according to claim 1, which is characterized in that the input processing module by One piece or muti-piece sub-circuit board realize, the time mark module, the data cache module, the event matches module and The result treatment module is all realized by resource in the piece of the FPGA on one piece of main control board；

It realizes one piece of input processing module or muti-piece sub-circuit board is directly inserted on the main control board or passes through back Plate links together with the main control board；If input processing module is realized by muti-piece sub-circuit board, muti-piece sub-circuit board Signal connection between main control board uses star structure；

The control module is realized using embedded processing unit or PC.

5. a kind of multi-photon coincidence counting device according to claim 1, which is characterized in that the result treatment module packet It includes: data multiplexer, the first count control module, the first dual port RAM, the first screening washer, the second screening washer, the second tally control Module, the second dual port RAM, WISHBONE bus and transmission control module；Wherein:

The data multiplexer first port is connected with the data cache module, the second port of the data multiplexer, institute The first port for stating the first count control module and first dual port RAM is sequentially connected；

The first port of first screening washer and the first port of second screening washer with the event matches module phase Even, the first port of the second port of second screening washer, second count control module and second dual port RAM according to It is secondary to be connected；

The of the second port of first dual port RAM, the second port of second dual port RAM and first screening washer Two-port netwerk is connected by the WISHBONE bus with the first port of the transmission control module；

The second port of the transmission control module is connected with control module.