CN208766255U

CN208766255U - Hit detection device

Info

Publication number: CN208766255U
Application number: CN201821513520.2U
Authority: CN
Inventors: 魏武; 农冠勇
Original assignee: GUANGZHOU CEPREI CALIBRATION AND TESTING CENTER SERVICE CO Ltd
Current assignee: GUANGZHOU CEPREI CALIBRATION AND TESTING CENTER SERVICE CO Ltd
Priority date: 2018-09-14
Filing date: 2018-09-14
Publication date: 2019-04-19
Anticipated expiration: 2028-09-14

Abstract

The utility model discloses a kind of hit detection device, the hit detection device includes: counter, is counted for the burst length to measured pulse；Comparator, it is configured to detect the failing edge voltage of the rising edge voltage of the measured pulse and the measured pulse, and the rising edge voltage of the measured pulse and failing edge voltage are compared with hit threshold voltage, when the rising edge voltage of the measured pulse is greater than the hit threshold voltage, the counter is enabled to count, when the failing edge voltage of the measured pulse is less than the hit threshold voltage, stops the counter and count；And processor, it is configured to calculate the burst length of the measured pulse according to the count value of the counter, and judge hit state according to the burst length of the measured pulse.The utility model being capable of accurate judgement and quickly capture hit pulse and accurately measurement hit burst length.

Description

Hit detection device

Technical field

The utility model relates to field of precision measurement more particularly to a kind of hit detection devices.

Background technique

It is a kind of fine measuring instrument that hit tester, which is connected, for monitoring electric connector connection wiring harness and interconnection Component in the dynamic loadings environmental test such as vibration, impact, collision whether can there is a phenomenon where momentary breaks suddenly, detect simultaneously Position and the time that hit occurs, for determining that contact of the elements such as harness and connector during dynamic use is reliable Property.Hit pulse for hit tester to be connected quickly captures and time synchronized measurement technology, is a kind of to judge to be in Whether the electric connector under the dynamical states such as vibration, electrical characteristic are vibrated the influence of impact, connector are caused to be transmitted Electric signal there is momentary breaks phenomenon, and accurately measurement occurs the time of hit and develops the special test technology of generation.

The existing hit pulse for hit tester to be connected quickly captures and time synchronized measurement technology generally uses The traditional logic gate device TTL realizes that operating voltage is higher, when work internal transistor be not parked in turn-on and turn-off state it Between toggle, cause its propagation delay time to can only achieve μ s magnitude, can only operate in the circuit at a slow speed of 1 μ s grade or more, be based on The existing measuring technique of TTL circuit is difficult to realize the purpose accurately measured the time of 0.01 μ s magnitude.

The difficulty of the small signal of burst pulse high speed is measured from the precise measurement to hit pulse width in short-term.To improve wink The measurement accuracy of disconnected pulse signal width, generally takes the method for improving counting clock frequency, and clock frequency is higher, measures pulsewidth Error it is smaller, but frequency is higher higher to the performance requirement of chip.Assuming that wink break time accuracy of measurement is 0.1 μ s, hit Time measurement resolution is 0.01 μ s；So clock frequency will reach 100MHz, one clock period time is 10ns.At this time General traditional logic gates, counter are all difficult to work normally, such as the rising of 74HC series of high speed TTL gate circuit chip Edge, failing edge are above 25ns, and signal transmission delay reaches 30ns, can not survey at all to 10ns hit pulse signal below Amount.

In order to guarantee reliable performance of the electric connector under vibrational state, country has promulgated that multiple standards advise it It is fixed, such as " unless otherwise prescribed, own when " GJB1217A-2009 electric connector test method " the 4.2nd article of regulation impact test The electric load of contact is up to 100mA；It is not allow for the electrical continuity of stipulated time, should use can detect 1 μ s hit Detector ".After so hit pulse signal occurs, how accurate judgement hit phenomenon occurs and how quickly to wink break time It measures etc. and higher design requirement is proposed to conducting hit tester, in the design of conducting hit tester, how It solves the problems, such as accurate judgement and quickly captures and accurately measure key of the hit burst length as design.

Utility model content

The purpose of the utility model is to provide a kind of hit detection devices, being capable of accurate judgement and quickly capture hit pulse And accurately measure the hit burst length.

The one aspect of the utility model provides a kind of hit detection device, comprising: counter, for measured pulse Burst length is counted；Comparator is configured to detect the rising edge voltage of the measured pulse and the measured pulse Failing edge voltage, and the rising edge voltage of the measured pulse and failing edge voltage are compared with hit threshold voltage, When the rising edge voltage of the measured pulse is greater than the hit threshold voltage, enables the counter and count, when the quilt When surveying the failing edge voltage of pulse less than the hit threshold voltage, stops the counter and count；And processor, it is configured to The burst length of the measured pulse is calculated according to the count value of the counter, and when according to the pulse of the measured pulse Between judge hit state.

Preferably, the processor is constituted are as follows: is less than the setting hit burst length when the burst length of the measured pulse When, judge that there is no hits；When the hit burst length is greater than the setting hit burst length and is less than the general pulse time When, judge that hit occurs.

Preferably, the hit detection device further include: latch is configured to that hit occurs when processor judgement When, the latch signal of output token hit generation.

Preferably, the processor is constituted are as follows: when judging that there is no resetting the counter and the latch when hit Device.

Preferably, the counter, the comparator and the latch are ECL high speed gate circuit.

Preferably, the transmission level of the measured pulse is ECL level, and the comparator is configured to according to the ECL electricity The rising edge voltage of the flat detection measured pulse and the failing edge voltage of the measured pulse.

The technical solution of above-mentioned aspect according to the present utility model, being capable of accurate judgement and quick capture hit pulse and standard The really measurement hit burst length.

Detailed description of the invention

It, below will be to institute in embodiment description in order to illustrate more clearly of the technical solution of the utility model embodiment Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the utility model Embodiment for those of ordinary skill in the art without any creative labor, can also be according to this A little attached drawings obtain other attached drawings.

Fig. 1 is a kind of schematic diagram of the hit detection device of embodiment of the utility model；

Fig. 2 is a kind of social function theory of the hit detection device of embodiment of the utility model；

Fig. 3 is a kind of process flow diagram of the hit detection method of embodiment of the utility model；

Fig. 4 is a kind of exemplary diagram of the hit detection method of embodiment of the utility model.

Specific embodiment

For convenient for the understanding to the utility model, below in conjunction with attached drawing to specific embodiment of the present utility model do into The explanation of one step, wherein various embodiments do not constitute the restriction to the utility model.

One embodiment of the utility model provides a kind of hit detection device, comprising: counter, for tested arteries and veins The burst length of punching is counted；Comparator is configured to detect the rising edge voltage of the measured pulse and the tested arteries and veins The failing edge voltage of punching, and the rising edge voltage of the measured pulse and failing edge voltage are compared with hit threshold voltage Compared with enabling the counter and count, when described when the rising edge voltage of the measured pulse is greater than the hit threshold voltage When the failing edge voltage of measured pulse is less than the hit threshold voltage, stops the counter and count；And processor, it constitutes For the burst length for calculating the measured pulse according to the count value of the counter, and according to the pulse of the measured pulse Time judges hit state.

The hit testing principle of present embodiment is as shown in Figure 1, hit (pulse to be measured) rising edge that electric connector generates It is compared with hit threshold voltage.When hit rising edge voltage is greater than hit threshold voltage, comparator output signal EN makes Energy counter, counter start counting under clock source signals CLK triggering；Rise when detecting with the hit of electric connector generation When along the adjacent hit failing edge voltage of voltage, comparator output signal stops counter and counts；Micro-control unit MCU (Micro Controller Unit) value of counter is read at this time and calculates the time of hit pulse accordingly.

In the present embodiment, as shown in Figure 1, being used as constant vibration time signal using active crystal oscillator (crystal oscillator) Source, the signal source carry out the clock reference source that level conversion makees counter counting with through NAND gate chip, and wherein level conversion is TTL signal is changed into ECL signal.Since the rising edge of hit pulse can not be fully synchronized with clock pulses, the period is counted not Completely, hit pulse width measuring is caused to be bound to have error, therefore clock source frequency is at least higher than the 2 of testing time frequency Times, it just can guarantee the accuracy of measurement.

To overcome influence of the device to line transmission, present embodiment uses emitter-coupled logic (ECL) ECL (Emitter Coupled Logic) level is as transmission level, in the sequential logical circuit of present embodiment, transmission level It is the electric signal that logic level is transmitted from device input to output end.Present embodiment preferably uses ECL high-speed door electric Road is as sequential logical circuit, its biggest characteristic is that basic gate circuit work in unsaturated state, since output impedance is small, drives Electric current is bigger, strong antijamming capability, and delay time is ps and ns magnitude, is highly suitable for high-speed transfer occasion.

Specifically, in the present embodiment, as the hit burst length T of measurement_{It is disconnected}< sets hit burst length T_setWhen, Show that there is no momentary breaks；As measurement hit burst length T_{It is disconnected}> sets hit burst length T_set, and measure hit pulse Time T_{It is disconnected}When < 99.99us (example of general pulse time), show that momentary breaks have occurred, counter continues to count, and works as wink At the end of disconnected, counter stops counting, and data are latched；If T_{It is disconnected}> 99.99us, counter stop counting.That is, being sent out in hit When raw, counter is started counting, and terminates in hit or hit counts and stops counting when being greater than 99.99us.Here wink break time The maximum time of measurement is 99.99us, then without counting more than 99.99us, can then accurately measure hit arteries and veins less than 99.99us Rush the time.MCU reads count value and respective logical states, and output state result.

The following table 1 is the sequential logic truth table for carrying out hit measurement in present embodiment using logical device.Wherein, T_{It is disconnected}Table Show the hit burst length of measured pulse, T_setIndicate the setting hit burst length, count is the value of counter, and MR indicates to reset Mark, lockBit, which indicates to count, latches mark, and countValue indicates counted number of pulses, and software reset indicates that MCU is needed to carry out Reset count value.

1 sequential logic truth table of table

Present embodiment, it is preferable that take ECL level as the transmission level of the measured pulse, examined according to the ECL level Survey the rising edge voltage and failing edge voltage of the measured pulse.

Fig. 2 is a kind of concrete function logic chart of the hit detection device of embodiment of the utility model.It is patrolled in the function It collects in figure, it is preferable that realize that this hit is measured using the hardware circuit of high-speed response, it should be understood by those skilled in the art that its As a kind of implementation of present embodiment, the limitation to present embodiment is not constituted.

In Fig. 2, voltage compares threshold generation circuits, for generating hit comparison voltage threshold value, with connector input Hit pulse voltage is compared into comparator together, comparator according to input voltage difference export comparative level enter or Gate logic processing, enters back into 16 digit counters and is counted, and crystal oscillator generates the TTL signal source of standard, becomes ECL through level conversion Level enters counter, mainly cooperates counter to generate what wink break time counted with door, nor gate, latch, digital comparator Comparing and lock logic function, MCU is responsible for reading the count value of counter and the time of setting digital comparator compares design value, Software reset is carried out to latch, counter simultaneously and removing is handled.

To guarantee the accurate of high speed transmission of signals, the signal delay of logic level has a great impact to accurate measurement, because This logic chip in signals transmission all uses the component of ECL level, guarantees the accuracy of level transmission.This embodiment party The logical device of all ECL level of device in formula, has high-speed transfer characteristic, and other TTL logical devices can also complete phase Same logic function is delayed very big when only progress high-speed transfer goes out, and causes high speed to measure inaccurate.Therefore, present embodiment When designing sequential logical circuit, high-speed comparator, high-speed counter, at a high speed with the logic devices such as door or door, digital comparator ECL level logic chip is preferably used in the selection of part, transmission delay is in ns magnitude, as shown in table 2 below.

2 gate circuit parameter of table

Model	Type	Level	Transmission delay (ns)
				SY100E137	Counter	ECL	2.2
SY10-100E104	NAND gate	ECL	0.38
				SY100S302	Nor gate	ECL	0.7
SY10-100E166	Digital comparator	ECL	1.1
				SY100S350	Latch	ECL	1.0

In logic circuits, TTL circuit and ECL circuit can realize logic level, and just TTL circuit can only realize low speed Transmission, high-speed transfer can generate signal delay distortion, and ECL level will not generate distortion in high-speed transfer.By as above adopting With ECL high-speed door circuit chip, the accuracy of signal transmission ensure that.

In present embodiment preferably using ECL high speed gate circuit as sequential logical circuit outside, can also be used programmable Logical device FPGA or CPLD substitution are realized.

The another embodiment of the utility model provides a kind of hit detection method, comprising: when detecting measured pulse Rising edge voltage be greater than hit threshold voltage when, enablement count device count；When the failing edge electricity for detecting the measured pulse When pressure is less than the hit threshold voltage, stops the counter and count；The quilt is calculated according to the count value of the counter Survey the burst length of pulse；Hit state is judged according to the burst length of the measured pulse.

Specifically, the process flow of the hit detection method of present embodiment is as shown in figure 3, include that following processing walks It is rapid:

Step S21, when the rising edge voltage for detecting measured pulse is greater than hit threshold voltage, enablement count device meter Number；

Step S22, when the failing edge voltage for detecting the measured pulse is less than the hit threshold voltage, stop institute State counter counting；

Step S23, the hit burst length of the measured pulse is calculated according to the count value of the counter；

Step S24, hit state is determined according to the burst length of the measured pulse.

Preferably, in step s 24, judge that hit state includes: when described according to the burst length of the measured pulse When the burst length of measured pulse is less than the setting hit burst length, judge that there is no hits；When the hit burst length When greater than the setting hit burst length and being less than the general pulse time, then judge that hit occurs.

In hit impulsive measurement, different connectors is different to the requirement of hit burst length, and this requires testers The setting hit burst length can be determined acording to the requirement of user.

Below according to a specific example, hit state is determined according to the hit burst length come illustrate present embodiment Method detects hit as shown in figure 4, the hit measurement process of present embodiment is actually a sequential logical circuit process Rising edge voltage, in hit measurement process, when the hit rising edge voltage of generation is greater than hit threshold voltage, processor refers to Show that comparator overturning exports a level control enablement count device and counts, counter is counted with the frequency of clock signal.When When hit failing edge voltage is less than hit threshold voltage, stops the counter and count；When stopping counting according to the counter Count value calculate the hit burst length；At this point, the count value of counter output enters digital comparator, with setting hit pulse Time T_setIt is compared, as hit burst length T_{It is disconnected}< sets hit burst length T_setWhen, and the hit burst length is corresponding Hit failing edge voltage is less than the hit threshold voltage, logic gate meeting reset count device, then it represents that hit exception or hit There is no 4 hit burst lengths T1, T2, T3, T4 are both less than T in figure_set, so circuit automatic fitration is fallen, logic circuit Judge hit there is no.It is greater than T in the time T5 of T5 hit pulse generation_set, digital comparator export the control of level with Gate circuit, the latch signal that latch output hit occurs marks hit, and indication counter continues to count；Directly When being less than the hit threshold voltage to hit burst length corresponding hit failing edge voltage, counter stops counting, measurement It latches, logic circuit judges hit, while single-chip microcontroller detects that signal occurs for hit, reads the value of counter, is divided It analyses and shows, then hit measurement process is completed.

In conclusion the utility model embodiment passes through when the rising edge voltage for detecting measured pulse is greater than hit threshold When threshold voltage, enablement count device is counted；When detect the failing edge voltage adjacent with the rising edge voltage be less than the hit When threshold voltage, stops the counter and count；The hit arteries and veins of the measured pulse is calculated according to the count value of the counter Rush the time；The hit state of the measured pulse is determined according to the hit burst length to determine whether that hit occurs.Pass through The above method, can while judge whether occurring to pulse hit, can quickly to hit time pulse signal into The synchronous detection of row, capture and identification measurement.

Those of ordinary skill in the art will appreciate that: attached drawing is the schematic diagram of an embodiment, the module in attached drawing Or process is not necessarily implemented necessary to the utility model.

Through the above description of the embodiments, those skilled in the art can be understood that the utility model can It realizes by means of software and necessary general hardware platform.Based on this understanding, the technical solution of the utility model Substantially the part that contributes to existing technology can be embodied in the form of software products in other words, the computer software Product can store in storage medium, such as ROM/RAM, magnetic disk, CD, including some instructions are used so that a computer Equipment (can be personal computer, server or the network equipment etc.) executes each embodiment of the utility model or reality Apply method described in certain parts of mode.

The foregoing is merely the preferable specific embodiment of the utility model, but the protection scope of the utility model not office It is limited to this, anyone skilled in the art within the technical scope disclosed by the utility model, can readily occur in Change or replacement should be covered within the scope of the utility model.Therefore, the protection scope of the utility model should be with Subject to scope of protection of the claims.

Claims

1. a kind of hit detection device characterized by comprising

Counter is counted for the burst length to measured pulse；

Comparator is configured to detect the failing edge voltage of the rising edge voltage of the measured pulse and the measured pulse, and The rising edge voltage of the measured pulse and failing edge voltage are compared with hit threshold voltage, when the measured pulse Rising edge voltage when being greater than the hit threshold voltage, enable the counter and count, when the failing edge of the measured pulse When voltage is less than the hit threshold voltage, stops the counter and count；

And processor, it is configured to calculate the burst length of the measured pulse, and root according to the count value of the counter Hit state is judged according to the burst length of the measured pulse.

2. hit detection device according to claim 1, which is characterized in that the processor is constituted are as follows:

When being less than the setting hit burst length in the burst length of the measured pulse, judge that there is no hits；

When the hit burst length being greater than the setting hit burst length and being less than the general pulse time, judge that hit occurs.

3. hit detection device according to claim 2, which is characterized in that further include: latch is configured to when the place When managing device judgement generation hit, the latch signal of output token hit generation.

4. hit detection device according to claim 3, which is characterized in that the processor is constituted are as follows: when judgement does not have When hit occurs, the counter and the latch are resetted.

5. hit detection device according to claim 3 or 4, which is characterized in that the counter, the comparator and institute Stating latch is ECL high speed gate circuit.

6. hit detection device according to claim 1, which is characterized in that

The transmission level of the measured pulse is ECL level, and the comparator is configured to the quilt according to the ECL level detection Survey the rising edge voltage of pulse and the failing edge voltage of the measured pulse.