CN208674114U - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
- Publication number
- CN208674114U CN208674114U CN201821529359.8U CN201821529359U CN208674114U CN 208674114 U CN208674114 U CN 208674114U CN 201821529359 U CN201821529359 U CN 201821529359U CN 208674114 U CN208674114 U CN 208674114U
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- semiconductor layer
- layer
- grid line
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The utility model relates to a kind of semiconductor structure, the semiconductor structure includes substrate；Positioned at the storage stack structure of the substrate surface；Through the grid line separate slot of the storage stack structure to the substrate surface；The semiconductor layer being filled in the grid line separate slot, doped with the foreign atom for reducing the semiconductor layer grain size in the semiconductor layer.The semiconductor layer crystal grain that the above method is formed is smaller, can be improved the performance of semiconductor structure.
Description
Technical field
The utility model relates to semiconductor production preparation field more particularly to a kind of semiconductor structures.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
During forming 3D nand memory, need to form in substrate surface formation sacrificial layer with stacked dielectric layer
Stacked structure, then etch the stacked structure and form grid line separate slot, then the filling semiconductor layer in grid line separate slot.
In the prior art, polysilicon layer or amorphous semiconductor material layer are filled usually in grid line separate slot.Polysilicon layer exists
It is smaller that strain is generated after subsequent high temperature annealing, but usually there are gaps with the inner wall surface of grid line separate slot, cannot be properly fit onto
The surface of the grid line separate slot, and inside is easy to appear cavity, influences the performance of finally formed memory；Amorphous semiconductor material
The bed of material can tamp grid line separate slot, and with the surface gapless of grid line separate slot and inside is without cavity, however in subsequent carry out high temperature
The problems such as crystallization can be generated after annealing, is applied by biggish stress, warpage occurs so as to cause substrate for substrate, to influence final
The performance of the memory of formation.
Therefore, the performance for the memory that the prior art is formed needs to be further improved.
Utility model content
The purpose of this utility model is to provide a kind of semiconductor structure, it can be used in the performance for improving memory.
In order to solve the above-mentioned technical problem, the technical solution of the utility model provides a kind of semiconductor structure, comprising: lining
Bottom；Positioned at the storage stack structure of the substrate surface；Through the storage stack structure to the substrate surface grid line every
Slot；The polycrystalline state semiconductor layer as made of amorphous state being filled in the grid line separate slot adulterates in the semiconductor layer
There is the foreign atom for reducing the semiconductor layer grain size.
Optionally, the semiconductor layer is polysilicon layer.
Optionally, the foreign atom is carbon atom.
Optionally, the ratio range of the amount of the substance of the amount and silicon atom of the substance of the carbon atom in the semiconductor layer is
5% to 20%.
Optionally, the particle size range of crystal grain is 19nm~150nm in the semiconductor layer.
Optionally, further includes: cover the insulation side wall of the grid line separate slot side wall.
Optionally, the foreign atom is doped in situ in the semiconductor layer.
Optionally, the semiconductor layer fills the full grid line separate slot.
Optionally, the storage stack structure includes that insulating layer and the control of setting are alternately stacked along vertical substrates surface direction
Grid structure layer processed.
Optionally, the semiconductor structure is 3D nand memory.
What is filled in the grid line separate slot of the semiconductor structure of the utility model is the semiconductor layer doped with foreign atom, institute
Stating foreign atom can reduce grain size in semiconductor layer, so that homogeneous grain size in semiconductor layer.Due to amorphous half
Foreign atom in conductor material layer can reduce grain size, reduce the annealed processing shape of the amorphous semiconductor material layer
At the strain generated after polycrystalline material, to reduce a possibility that warpage occurs for substrate, finally formed memory is improved
Performance.
Detailed description of the invention
Fig. 1 is the process signal of the preparation method of the semiconductor structure in a kind of specific embodiment of the utility model
Figure；
Fig. 2 to Fig. 6 is the formation schematic diagram of the semiconductor structure in a kind of specific embodiment of the utility model；
Fig. 7 is the corresponding amorphous semiconductor material layer of gas flow ratio of different ethylene and silane in 650 DEG C of high temperature
Dependent variable schematic diagram after annealing.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to the utility model proposes a kind of semiconductor structure and its preparation side
The detailed description of method.
Referring to Fig. 1, the flow chart of the preparation method for semiconductor structure described in a kind of specific embodiment.Described half
The preparation method of conductor structure is the following steps are included: S11: providing a substrate, the substrate surface is formed with stacked structure.S12:
Grid line separate slot is formed in the stacked structure, the grid line separate slot is through the stacked structure to the substrate surface.S13:
Semiconductor layer is formed in the grid line separate slot, the semiconductor layer is filled in the grid line separate slot, and in the semiconductor layer
Doped with foreign atom, the foreign atom can reduce the grain size of the semiconductor layer.
Fig. 2 to Fig. 6 is please referred to, is that a kind of semiconductor structure of specific embodiment of the utility model forms the knot of process
Structure schematic diagram.
Referring to Fig. 2, providing a substrate 201,201 surface of substrate is formed with stacked structure 202, the stacked structure
202 include the insulating layer 203 and sacrificial layer 204 being stacked with along 201 surface direction of vertical substrates.Fig. 2 shows semiconductor junctions
The partial profile structure of structure.
The substrate 201 can be described for Si substrate, Ge substrate, SiGe substrate, silicon-on-insulator or germanium on insulator etc.
Substrate 201 can also be laminated construction and other epitaxial structures, such as Si/SiGe or sige-on-insulator etc..In the specific reality
It applies in mode, the substrate 201 is Si substrate.
The stacked structure 202 includes the insulating layer 203 and sacrificial layer 204 being alternately stacked upwards along vertical substrates 201.It should
In specific embodiment, the insulating layer 203 is silicon oxide layer, and sacrificial layer 204 is silicon nitride layer.In other specific embodiments
In, the insulating layer 203 and sacrificial layer 204 can also use other suitable materials.
In the specific embodiment, it is also formed in the stacked structure 202 through stacked structure 202 to 201 table of substrate
The channel pore structure (not shown) in face, the channel pore structure include through the channel hole of stacked structure 202, positioned at channel
The epitaxial semiconductor layer on 201 surface of substrate of hole bottom, and function side wall, the filling channel hole of covering channel hole sidewall surfaces
Channel dielectric layer.The channel pore structure is as the storage string structure perpendicular to 201 surface of substrate, side wall and the insulating layer
203 and sacrificial layer 204 connect.
Referring to Fig. 3, forming grid line separate slot 301 in the stacked structure 202, the grid line separate slot 301 is through described
Stacked structure 202 is to 201 surface of substrate.
In a specific embodiment, dry etch process can be used and etch the stacked structure 202 to 201 table of substrate
Face forms the grid line separate slot 301 in the stacked structure 202.In this specific embodiment, using reactive plasma
Etching technics carries out vertical etch to stacked structure 202, forms the grid line separate slot 301.
Referring to Fig. 4, side wall removal sacrificial layer 204 (the please referring to Fig. 3) formation along the grid line separate slot 301 is located at
Opening 302 between adjacent insulating layer 203.
The sacrificial layer 204 can be removed using wet-etching technology.In the specific embodiment, the sacrificial layer 204
Material be silicon nitride, the sacrificial layer 204 is etched using phosphoric acid solution.
Due to being formed with channel pore structure in the stacked structure 202, insulating layer 203 is connect with channel pore structure side wall,
After removing the sacrificial layer 204, the channel pore structure can play a supporting role to insulating layer 203, so that adjacent exhausted
There is opening 302 between edge layer 203.
Referring to Fig. 5, forming control gate structure sheaf 500 in 302 (please referring to Fig. 5) of the opening.
It is opened described in gate dielectric layer and filling of the control gate structure sheaf 500 including covering 302 inner wall surfaces of opening are full
The grid layer of mouth 302.The gate dielectric layer can be formed using atom layer deposition process, be formed using chemical vapor deposition process
The grid layer.
Referring to FIG. 6, forming the insulation side wall 401 for covering 301 sidewall surfaces of grid line separate slot and the filling grid
The semiconductor layer 501 of line separate slot 301.
It further include being doped to the substrate 201 of 301 bottom of grid line separate slot before forming the insulation side wall 401, shape
At source doping region 400.
It is formed after the source doping region 400, forms insulation side wall 401 in the sidewall surfaces of the grid line separate slot 301,
The insulation side wall 401 can be using insulating dielectric materials such as silica, silicon nitrides.It in a specific embodiment, can be with
Using chemical vapor deposition method, atom layer deposition process or other suitable deposition methods, in 301 inner wall of grid line separate slot
Surface formed spacer material layer after, removal be located at 301 bottom surface of grid line separate slot spacer material layer, retain be located at grid line every
The spacer material layer of 301 sidewall surfaces of slot, as insulation side wall 401.
It is formed after the insulation side wall 401, forms semiconductor layer 501, the semiconductor in the grid line separate slot 301
Layer 501 fills the full grid line separate slot 301, and doped with foreign atom in the semiconductor layer 501, the foreign atom can
Reduce the grain size of the semiconductor layer 501.
501 forming method of semiconductor layer includes: to be deposited in the grid line separate slot 301 using doping process in situ
Amorphous semiconductor material layer with foreign atom, the amorphous semiconductor material layer fill the full grid line separate slot 301；To institute
It states amorphous semiconductor material layer to be made annealing treatment, crystallizes amorphous semiconductor material layer, be converted to the semiconductor of polycrystalline state
Layer 501.Since the foreign atom can reduce crystal of the amorphous semiconductor material layer when annealing is converted into polycrystalline state
Grain size reduces semiconductor layer 501 and applies to substrate 201 so that the grain size in finally formed semiconductor layer 501 is smaller
Stress.
The temperature and handling duration that the annealing uses can be configured as needed.In the specific embodiment
In, the temperature range of the annealing is 630 DEG C to 670 DEG C, and the processing time is 0.5h~1.5h.
The amorphous semiconductor material layer with foreign atom is deposited in the grid line separate slot 301 using doping process in situ
When, chemical vapor deposition method, Atomic layer deposition method or other suitable deposition methods can be used.In the specific embodiment
In, using chemical vapor deposition method in the grid line separate slot 301 deposited amorphous semiconductor material layer.
In this specific embodiment, the foreign atom is carbon atom.The semiconductor layer 501 is polysilicon layer.It is heavy
Reaction gas used by product amorphous semiconductor material layer includes: deposition gases and impurity gas, and the deposition gases include containing
Silicon gas, the impurity gas are carbonaceous gas.
In a specific embodiment, in the reaction gas substance of the amount and silicon atom of the substance of carbon atom amount
Ratio be 5%~20%.By controlling the amount of the substance of the amount and silicon atom of the substance of carbon atom in the reaction gas
Ratio controls the ratio of the amount of the substance of carbon atom and silicon atom in the semiconductor layer 501.
In a specific embodiment, the silicon-containing gas includes at least one of silane and disilane.It is described to contain
The gas of carbon gas includes at least one of ethylene, acetylene, propylene, propine.According to carbon atom in gas with various, silicon atom
The ratio of the amount of the substance of the amount and silicon atom of the substance of carbon atom in content and required reaction gas determines specific
Gas flow ratio.Those skilled in the art can choose the type of actual carbonaceous gas and silicon-containing gas as needed, and
It is not limited with the type of above-mentioned statement.
In this specific embodiment, the silicon-containing gas used is silane, and the carbonaceous gas used is ethylene, and the second
The ratio range of the gas flow of alkene and silane is 5% to 20%, at this point, the amount of the substance of carbon atom and silicon are former in reaction gas
The ratio of the amount of the substance of son is 5%~20%.
Referring to Fig. 7, the amorphous semiconductor material that is correspondingly formed of ratio of the gas flow for different ethylene and silane
Layer is through 650 DEG C of dependent variable schematic diagrames after annealing at a high temperature.
In Fig. 7, when the ratio of ethylene and the gas flow of silane is in 5%~20%, with ethylene and silane
The raising of the ratio of gas flow, the amorphous semiconductor material layer form answering for polycrystal semiconductor layer after the high temperature anneal
Variate reduces.When the ratio of ethylene and the gas flow of silane reaches 20%, the annealed place of amorphous semiconductor material layer
Strain value after reason is 120 μm, and when the ratio of ethylene and the gas flow of silane is greater than 20%, the amorphous semiconductor material
The bed of material is annealed, and treated that strain value has the tendency that rising, is greater than 120 μm of minimum value.
Inventor also found, when being free of ethylene in reaction gas, the amorphous semiconductor material layer of generation is annealed through 650 DEG C
After processing, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation is 314nm.
When the ratio of ethylene in reaction gas and the gas flow of silane is 5%, the amorphous semiconductor material layer of generation
After 650 DEG C of annealings, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation is 150nm.
When the ratio of ethylene in reaction gas and the gas flow of silane is 10%, the amorphous semiconductor material layer of generation
After 650 DEG C of annealings, the average grain diameter of the grain of the semiconductor layer 501 of formation is 67nm.
When the ratio of ethylene in reaction gas and the gas flow of silane is 20%, the amorphous semiconductor material layer of generation
After 650 DEG C of annealings, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation is 19nm.
In the range of 5% to 20%, as the ratio of the gas flow of ethylene and silane in reaction gas increases, generate
Amorphous semiconductor material layer through 650 DEG C annealing after, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation gradually subtracts
It is small.
Therefore, in the range of 5% to 20%, with the ratio of the gas flow of ethylene and silane in the reaction gas
Increase, the ratio of the amount of the substance of carbon atom and silicon atom is also increasing in the semiconductor layer 501, the amorphous semiconductor of generation
The crystal grain that material layer crystallizes the semiconductor layer 501 of formation after annealed processing is gradually reduced, and what is generated after annealed processing answers
Change is also gradually reduced.
When choosing other gases as silicon-containing gas and the carbonaceous gas, need according in required reaction gas
The ratio of the amount of the substance of the amount and silicon atom of the substance of carbon atom controls the gas flow ratio of silicon-containing gas and carbonaceous gas
Value.In a specific embodiment, the inlet of the silicon-containing gas and the inlet of carbonaceous gas are respectively arranged with gas
Flowmeter, with the ratio of silicon-containing gas described in monitoring and measurement and the gas flow of carbonaceous gas.
In the specific embodiment, the ratio of the amount of the substance of carbon atom and silicon atom is 5% in the semiconductor layer 501
~20%, the model of the partial size of the crystal grain of the semiconductor layer 501 formed after the annealed processing crystallization of amorphous semiconductor material layer
It encloses for 19nm~150nm.The crystal grain of the semiconductor layer 501 formed after the annealed processing crystallization of amorphous semiconductor material layer
The range of partial size is directly related with the ratio of amount of the substance of carbon atom and silicon atom in the semiconductor layer 501.Tune can be passed through
The ratio of the amount of the substance of carbon atom and silicon atom in the whole semiconductor layer 501 adjusts crystal grain in the semiconductor layer 501
Partial size.The ratio of the amount of the substance of carbon atom and silicon atom can be by carbon containing gas in the reaction gas in the semiconductor layer 501
The direct decision of the gas flow of body and silicon-containing gas.
In the specific embodiment, during forming semiconductor layer 501, formed in grid line separate slot 301 first non-
Brilliant semiconductor material layer, due in the semiconductor material layer without grain structure, when depositing in the grid line separate slot 301,
It can be tightly combined between the inner wall of the grid line separate slot 301, the defects of inside will not form gap.It is subsequent to described non-
Brilliant semiconductor material layer, which carries out annealing, makes it change the semiconductor layer of more polycrystalline states 501, due to amorphous semiconductor material
Foreign atom in layer can reduce the grain size in semiconductor layer 501, so that semiconductor layer 501, has smaller crystal grain.
Crystal grain is smaller, it is meant that the strain generated in crystallization process is also smaller, and the stress for being applied to substrate 201 is small, reduces substrate
201 are extruded into a possibility that warpage occurs, so as to improve the performance of finally formed memory.
A kind of semiconductor structure is additionally provided in specific embodiment of the present utility model.
In the specific embodiment, the semiconductor structure is 3D nand memory.
Referring to Fig. 6, for the partial structurtes signal of the semiconductor structure in a kind of specific embodiment of the utility model
Figure.
In this specific embodiment, the semiconductor structure includes: substrate 201；Positioned at depositing for 201 surface of substrate
Store up stacked structure；Through the storage stack structure to the grid line separate slot on 201 surface of substrate；It is filled in the grid line separate slot
In semiconductor layer 501, doped with the doping for reducing 501 grain size of semiconductor layer in the semiconductor layer 501
Atom.
The storage stack structure 702 includes tell somebody what one's real intentions are along vertical substrates the surface direction insulating layer 203 and control gate of stacking
Structure sheaf 500.
The substrate 201 can be described for Si substrate, Ge substrate, SiGe substrate, silicon-on-insulator or germanium on insulator etc.
Substrate 201 can also be laminated construction and other epitaxial structures, such as Si/SiGe or sige-on-insulator etc..In the specific reality
It applies in mode, the substrate 201 is Si substrate.
The grid line separate slot through storage stack structure to 201 surface of substrate, and the substrate 201 of grid line separate slot bottom
It is interior that there is source doping region 400.
In the specific embodiment, insulation side wall 401 is also covered on the side wall of the grid line separate slot, as semiconductor layer
Isolation structure between 501 and control gate structure sheaf 500.
The material of the semiconductor layer 501 is polycrystalline semiconductor material.Specifically, the material of the semiconductor layer 501 is
Polysilicon.And doped with foreign atom in the semiconductor layer 501, the foreign atom can reduce semiconductor layer 301
Grain size.In the specific embodiment, the foreign atom is carbon atom.
The ratio of carbon atom and silicon atom determines the grain size in semiconductor layer 501.In the specific of the utility model
In embodiment, the ratio range of the amount of the substance of the amount and silicon atom of the substance of the carbon atom in the semiconductor layer 501 is
5% to 20%.The foreign atom is doped in situ in the semiconductor layer 501, can also be with displacement atom or interstitial atom
Form doping with the semiconductor layer 501 in.
The range of the partial size of the crystal grain of the semiconductor layer 705 is 19nm to 150nm, and crystal grain is uniform in size.One
It, can be by adjusting the object of silicon atom and carbon atom in the reaction gas for generating the semiconductor layer 705 in kind specific embodiment
The ratio of the amount of matter adjusts the particle size range of the crystal grain of the semiconductor layer 705.In a specific embodiment, work as doping
When thering is the annealing temperature of the amorphous semiconductor material layer of carbon atom to be 630 DEG C to 670 DEG C, the generation semiconductor layer 705 is controlled
Reaction gas in carbon atom substance amount and silicon atom substance amount ratio range within 5% to 20%, i.e.,
The range that can control the partial size of the crystal grain of the semiconductor layer 501 is 19nm to 150nm.
The semiconductor layer 501 fills the full grid line separate slot, is connected to the source doping region of grid line separate slot bottom
400, as the array common source for running through the storage stack structure.In the specific embodiment, the semiconductor layer 501 also covers
It covers to the top surface of the storage stack structure, it is subsequent that the storage stack structural top can be removed by flatening process
Semiconductor layer 501.
Doped with mixing for grain size can be reduced in the semiconductor layer filled in the grid line separate slot of above-mentioned semiconductor structure
Hetero atom, so that the crystallite dimension in the semiconductor layer is lower, so that the stress that the semiconductor layer applies substrate is reduced,
The problems such as reducing the warpage that substrate occurs, so that the performance of semiconductor structure improves.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
Art personnel can also make several improvements and modifications without departing from the principle of this utility model, these improvements and modifications
Also it should be regarded as the protection scope of the utility model.
Claims (10)
1. a kind of semiconductor structure characterized by comprising
Substrate；
Positioned at the storage stack structure of the substrate surface；
Through the grid line separate slot of the storage stack structure to the substrate surface；
The polycrystalline state semiconductor layer as made of amorphous state being filled in the grid line separate slot adulterates in the semiconductor layer
There is the foreign atom for reducing the semiconductor layer grain size.
2. semiconductor structure according to claim 1, which is characterized in that the semiconductor layer is polysilicon layer.
3. semiconductor structure according to claim 2, which is characterized in that the foreign atom is carbon atom.
4. semiconductor structure according to claim 3, which is characterized in that the substance of the carbon atom in the semiconductor layer
The ratio range of amount and the amount of the substance of silicon atom is 5% to 20%.
5. semiconductor structure according to claim 1, which is characterized in that the particle size range of crystal grain is in the semiconductor layer
19nm~150nm.
6. semiconductor structure according to claim 1, which is characterized in that further include: cover the grid line separate slot side wall
Insulate side wall.
7. semiconductor structure according to claim 1, which is characterized in that the foreign atom is doped in situ described partly leads
In body layer.
8. semiconductor structure according to claim 1, which is characterized in that the semiconductor layer fill the full grid line every
Slot.
9. semiconductor structure according to claim 1, which is characterized in that the storage stack structure includes along vertical substrates
Surface direction is alternately stacked the insulating layer and control gate structure sheaf of setting.
10. semiconductor structure according to claim 1, which is characterized in that the semiconductor structure is 3D NAND storage
Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821529359.8U CN208674114U (en) | 2018-09-19 | 2018-09-19 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821529359.8U CN208674114U (en) | 2018-09-19 | 2018-09-19 | Semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208674114U true CN208674114U (en) | 2019-03-29 |
Family
ID=65842251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821529359.8U Active CN208674114U (en) | 2018-09-19 | 2018-09-19 | Semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208674114U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962903A (en) * | 2018-09-19 | 2018-12-07 | 长江存储科技有限责任公司 | Semiconductor structure |
-
2018
- 2018-09-19 CN CN201821529359.8U patent/CN208674114U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962903A (en) * | 2018-09-19 | 2018-12-07 | 长江存储科技有限责任公司 | Semiconductor structure |
| CN108962903B (en) * | 2018-09-19 | 2024-02-02 | 长江存储科技有限责任公司 | Semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI404123B (en) | Selective epitaxial formation of semiconductor films | |
| CN108649034B (en) | Semiconductor structure and forming method thereof | |
| JP2014512669A (en) | Low temperature selective epitaxy method | |
| KR102072270B1 (en) | Method of growing crystal in recess and processing apparatus used therefor | |
| JP2006186240A5 (en) | ||
| CN108962903A (en) | Semiconductor structure | |
| CN105810638B (en) | A kind of 3D NAND flash memory structure and production method | |
| JPH0799241A (en) | Method for forming insulating trench in substrate for smart power chip | |
| CN109326507A (en) | The forming method of memory | |
| CN106941103A (en) | The forming method of nand memory | |
| JP2017183508A (en) | Silicon film forming method and forming device | |
| US9780173B2 (en) | High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate | |
| CN102800679B (en) | The forming method of the memory cell of flash memory | |
| CN109411475A (en) | Memory and forming method thereof | |
| CN208674114U (en) | Semiconductor structure | |
| US20060021570A1 (en) | Reduction in size of hemispherical grains of hemispherical grained film | |
| CN108155231A (en) | Igbt and its grid making method, IPM modules and air conditioner | |
| CN103855098B (en) | Method for forming storage unit of flash memory | |
| TWI700784B (en) | Recess filling method and storage medium | |
| CN102456561B (en) | Forming method of thick gate oxide layer at bottom of groove in groove-type power device | |
| CN107799531B (en) | A kind of 3D nand memory grade layer stack manufacturing method | |
| CN101692434B (en) | Filling method of deep groove isolation structure of silicon-on-insulator | |
| US8178426B2 (en) | Method for manufacturing a structure of semiconductor-on-insulator type | |
| TW200933710A (en) | Method for preparing doped polysilicon conductors and method for preparing trench capacitor structures using the same | |
| CN103187269A (en) | Forming method of transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |