CN109326507A - The forming method of memory - Google Patents
The forming method of memory Download PDFInfo
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- CN109326507A CN109326507A CN201811092078.5A CN201811092078A CN109326507A CN 109326507 A CN109326507 A CN 109326507A CN 201811092078 A CN201811092078 A CN 201811092078A CN 109326507 A CN109326507 A CN 109326507A
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- 230000015654 memory Effects 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 133
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000007789 gas Substances 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 52
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 125000004429 atom Chemical group 0.000 claims description 28
- 229910052799 carbon Inorganic materials 0.000 claims description 28
- 150000001721 carbon Chemical group 0.000 claims description 25
- 239000000126 substance Substances 0.000 claims description 25
- 238000000137 annealing Methods 0.000 claims description 19
- 239000012495 reaction gas Substances 0.000 claims description 19
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 16
- 229910000077 silane Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 15
- 238000009413 insulation Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 claims description 3
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 claims description 3
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 claims description 3
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 claims description 3
- MWWATHDPGQKSAR-UHFFFAOYSA-N propyne Chemical compound CC#C MWWATHDPGQKSAR-UHFFFAOYSA-N 0.000 claims description 3
- 150000001336 alkenes Chemical class 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 16
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 15
- 239000005977 Ethylene Substances 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000003860 storage Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 6
- 239000011148 porous material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention relates to a kind of forming method of memory, the forming method of the memory includes: to provide a substrate, and the substrate surface is formed with stacked structure；Grid line separate slot is formed in the stacked structure, the grid line separate slot is through the stacked structure to the substrate surface；Semiconductor layer is formed in the grid line separate slot, the semiconductor layer is filled in the grid line separate slot, and doped with foreign atom in the semiconductor layer, the foreign atom can reduce the grain size of the semiconductor layer.The semiconductor layer crystal grain that the above method is formed is smaller, can be improved the performance of memory.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of forming methods of memory.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
During forming 3D nand memory, need to form in substrate surface formation sacrificial layer with stacked dielectric layer
Stacked structure, then etch the stacked structure and form grid line separate slot, then the filling semiconductor layer in grid line separate slot.
In the prior art, polysilicon layer or amorphous semiconductor material layer are filled usually in grid line separate slot.Polysilicon layer exists
It is smaller that strain is generated after subsequent high temperature annealing, but usually there are gaps with the inner wall surface of grid line separate slot, cannot be properly fit onto
The surface of the grid line separate slot, and inside is easy to appear cavity, influences the performance of finally formed memory；Amorphous semiconductor material
The bed of material can tamp grid line separate slot, and with the surface gapless of grid line separate slot and inside is without cavity, however in subsequent carry out high temperature
The problems such as crystallization can be generated after annealing, is applied by biggish stress, warpage occurs so as to cause substrate for substrate, to influence final
The performance of the memory of formation.
Therefore, the performance for the memory that the prior art is formed needs to be further improved.
Summary of the invention
The purpose of the present invention is to provide a kind of forming method of memory, it can be used in the performance for improving memory.
In order to solve the above-mentioned technical problem, a kind of forming method of memory is provided in the present invention, a kind of memory
Forming method, comprising the following steps: provide a substrate, the substrate surface is formed with stacked structure；In the stacked structure
Grid line separate slot is formed, the grid line separate slot is through the stacked structure to the substrate surface；It is formed in the grid line separate slot
Semiconductor layer, the semiconductor layer are filled in the grid line separate slot, and doped with foreign atom in the semiconductor layer, described to mix
Hetero atom can reduce the grain size of the semiconductor layer.
Optionally, the semiconductor layer forming method is included: and is deposited in the grid line separate slot using doping process in situ
Amorphous semiconductor material layer with foreign atom, the amorphous semiconductor material layer fill the full grid line separate slot；To described
Amorphous semiconductor material layer is made annealing treatment, and is crystallized amorphous semiconductor material layer, is converted to the semiconductor layer of polycrystalline state.
Optionally, the foreign atom is carbon atom.
Optionally, the semiconductor layer is polysilicon layer.
Optionally, reaction gas used by deposited amorphous semiconductor material layer includes: deposition gases and impurity gas, institute
Stating deposition gases includes silicon-containing gas, and the impurity gas is carbonaceous gas.
Optionally, the ratio of the amount of the substance of carbon atom and silicon atom is 5%~20% in the semiconductor layer.
Optionally, the gas of the carbonaceous gas includes at least one of ethylene, acetylene, propylene, propine；It is described siliceous
Gas includes at least one of silane and disilane.
Optionally, in the reaction gas amount of the substance of the amount and silicon atom of the substance of carbon atom ratio be 5%~
20%.
Optionally, the temperature range of the annealing is 630 DEG C to 670 DEG C, and the processing time is 0.5h~1.5h.
Optionally, further includes: before forming semiconductor layer, remove the sacrificial layer along the grid line separate slot, form position
Opening between adjacent insulating layer；Control gate structure sheaf is formed in the opening.
Optionally, further includes: before forming the semiconductor layer, form the insulation sides for covering the grid line separate slot side wall
Wall.
What the forming method of memory of the invention was filled in grid line separate slot is the semiconductor layer doped with foreign atom,
The foreign atom can reduce the grain size in semiconductor layer, so that homogeneous grain size in semiconductor layer.And further
, due to filled in the grid line separate slot be amorphous semiconductor material layer annealing after formation semiconductor layer,
It is seamless between the semiconductor layer and the grid line separate slot, and inside the semiconductor layer also tight the defects of.Further
, since the foreign atom in amorphous semiconductor material layer can reduce grain size, reduce the amorphous semiconductor material
The annealed processing of layer forms the strain generated after polycrystalline material, to reduce a possibility that warpage occurs for substrate, improves most
End form at memory performance.
Detailed description of the invention
Fig. 1 is the flow diagram of the forming method of the memory in a kind of specific embodiment of the invention；
Fig. 2 to Fig. 6 is the formation schematic diagram of the memory in a kind of specific embodiment of the invention；
Fig. 7 is the corresponding amorphous semiconductor material layer of gas flow ratio of different ethylene and silane in 650 DEG C of high temperature
Dependent variable schematic diagram after annealing.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of the detailed of memory proposed by the present invention and forming method thereof
Explanation.
Referring to Fig. 1, the flow chart of the forming method for memory described in a kind of specific embodiment.The memory
Forming method the following steps are included: S11: provide a substrate, the substrate surface is formed with stacked structure.S12: in the heap
Grid line separate slot is formed in stack structure, the grid line separate slot is through the stacked structure to the substrate surface.S13: in the grid
Form semiconductor layer in line separate slot, the semiconductor layer is filled in the grid line separate slot, and doped with mixing in the semiconductor layer
Hetero atom, the foreign atom can reduce the grain size of the semiconductor layer.
Fig. 2 to Fig. 6 is please referred to, is a kind of structural representation of the memory forming process of specific embodiment of the invention
Figure.
Referring to Fig. 2, providing a substrate 201,201 surface of substrate is formed with stacked structure 202, the stacked structure
202 include the insulating layer 203 and sacrificial layer 204 being stacked with along 201 surface direction of vertical substrates.Fig. 2 shows memories
Partial profile structure.
The substrate 201 can be described for Si substrate, Ge substrate, SiGe substrate, silicon-on-insulator or germanium on insulator etc.
Substrate 201 can also be laminated construction and other epitaxial structures, such as Si/SiGe or sige-on-insulator etc..In the specific reality
It applies in mode, the substrate 201 is Si substrate.
The stacked structure 202 includes the insulating layer 203 and sacrificial layer 204 being alternately stacked upwards along vertical substrates 201.It should
In specific embodiment, the insulating layer 203 is silicon oxide layer, and sacrificial layer 204 is silicon nitride layer.In other specific embodiments
In, the insulating layer 203 and sacrificial layer 204 can also use other suitable materials.
In the specific embodiment, it is also formed in the stacked structure 202 through stacked structure 202 to 201 table of substrate
The channel pore structure (not shown) in face, the channel pore structure include through the channel hole of stacked structure 202, positioned at channel
The epitaxial semiconductor layer on 201 surface of substrate of hole bottom, and function side wall, the filling channel hole of covering channel hole sidewall surfaces
Channel dielectric layer.The channel pore structure is as the storage string structure perpendicular to 201 surface of substrate, side wall and the insulating layer
203 and sacrificial layer 204 connect.
Referring to Fig. 3, forming grid line separate slot 301 in the stacked structure 202, the grid line separate slot 301 is through described
Stacked structure 202 is to 201 surface of substrate.
In a specific embodiment, dry etch process can be used and etch the stacked structure 202 to 201 table of substrate
Face forms the grid line separate slot 301 in the stacked structure 202.In this specific embodiment, using reactive plasma
Etching technics carries out vertical etch to stacked structure 202, forms the grid line separate slot 301.
Referring to Fig. 4, side wall removal sacrificial layer 204 (the please referring to Fig. 3) formation along the grid line separate slot 301 is located at
Opening 302 between adjacent insulating layer 203.
The sacrificial layer 204 can be removed using wet-etching technology.In the specific embodiment, the sacrificial layer 204
Material be silicon nitride, the sacrificial layer 204 is etched using phosphoric acid solution.
Due to being formed with channel pore structure in the stacked structure 202, insulating layer 203 is connect with channel pore structure side wall,
After removing the sacrificial layer 204, the channel pore structure can play a supporting role to insulating layer 203, so that adjacent exhausted
There is opening 302 between edge layer 203.
Referring to Fig. 5, forming control gate structure sheaf 500 in 302 (please referring to Fig. 5) of the opening.
It is opened described in gate dielectric layer and filling of the control gate structure sheaf 500 including covering 302 inner wall surfaces of opening are full
The grid layer of mouth 302.The gate dielectric layer can be formed using atom layer deposition process, be formed using chemical vapor deposition process
The grid layer.
Referring to FIG. 6, forming the insulation side wall 401 for covering 301 sidewall surfaces of grid line separate slot and the filling grid
The semiconductor layer 501 of line separate slot 301.
It further include being doped to the substrate 201 of 301 bottom of grid line separate slot before forming the insulation side wall 401, shape
At source doping region 400.
It is formed after the source doping region 400, forms insulation side wall 401 in the sidewall surfaces of the grid line separate slot 301,
The insulation side wall 401 can be using insulating dielectric materials such as silica, silicon nitrides.It in a specific embodiment, can be with
Using chemical vapor deposition method, atom layer deposition process or other suitable deposition methods, in 301 inner wall of grid line separate slot
Surface formed spacer material layer after, removal be located at 301 bottom surface of grid line separate slot spacer material layer, retain be located at grid line every
The spacer material layer of 301 sidewall surfaces of slot, as insulation side wall 401.
It is formed after the insulation side wall 401, forms semiconductor layer 501, the semiconductor in the grid line separate slot 301
Layer 501 fills the full grid line separate slot 301, and doped with foreign atom in the semiconductor layer 501, the foreign atom can
Reduce the grain size of the semiconductor layer 501.
501 forming method of semiconductor layer includes: to be deposited in the grid line separate slot 301 using doping process in situ
Amorphous semiconductor material layer with foreign atom, the amorphous semiconductor material layer fill the full grid line separate slot 301；To institute
It states amorphous semiconductor material layer to be made annealing treatment, crystallizes amorphous semiconductor material layer, be converted to the semiconductor of polycrystalline state
Layer 501.Since the foreign atom can reduce crystal of the amorphous semiconductor material layer when annealing is converted into polycrystalline state
Grain size reduces semiconductor layer 501 and applies to substrate 201 so that the grain size in finally formed semiconductor layer 501 is smaller
Stress.
The temperature and handling duration that the annealing uses can be configured as needed.In the specific embodiment
In, the temperature range of the annealing is 630 DEG C to 670 DEG C, and the processing time is 0.5h~1.5h.
The amorphous semiconductor material layer with foreign atom is deposited in the grid line separate slot 301 using doping process in situ
When, chemical vapor deposition method, Atomic layer deposition method or other suitable deposition methods can be used.In the specific embodiment
In, using chemical vapor deposition method in the grid line separate slot 301 deposited amorphous semiconductor material layer.
In this specific embodiment, the foreign atom is carbon atom.The semiconductor layer 501 is polysilicon layer.It is heavy
Reaction gas used by product amorphous semiconductor material layer includes: deposition gases and impurity gas, and the deposition gases include containing
Silicon gas, the impurity gas are carbonaceous gas.
In a specific embodiment, in the reaction gas substance of the amount and silicon atom of the substance of carbon atom amount
Ratio be 5%~20%.By controlling the amount of the substance of the amount and silicon atom of the substance of carbon atom in the reaction gas
Ratio controls the ratio of the amount of the substance of carbon atom and silicon atom in the semiconductor layer 501.
In a specific embodiment, the silicon-containing gas includes at least one of silane and disilane.It is described to contain
The gas of carbon gas includes at least one of ethylene, acetylene, propylene, propine.According to carbon atom in gas with various, silicon atom
The ratio of the amount of the substance of the amount and silicon atom of the substance of carbon atom in content and required reaction gas determines specific
Gas flow ratio.Those skilled in the art can choose the type of actual carbonaceous gas and silicon-containing gas as needed, and
It is not limited with the type of above-mentioned statement.
In this specific embodiment, the silicon-containing gas used is silane, and the carbonaceous gas used is ethylene, and the second
The ratio range of the gas flow of alkene and silane is 5% to 20%, at this point, the amount of the substance of carbon atom and silicon are former in reaction gas
The ratio of the amount of the substance of son is 5%~20%.
Referring to Fig. 7, the amorphous semiconductor material that is correspondingly formed of ratio of the gas flow for different ethylene and silane
Layer is through 650 DEG C of dependent variable schematic diagrames after annealing at a high temperature.
In Fig. 7, when the ratio of ethylene and the gas flow of silane is in 5%~20%, with ethylene and silane
The raising of the ratio of gas flow, the amorphous semiconductor material layer form answering for polycrystal semiconductor layer after the high temperature anneal
Variate reduces.When the ratio of ethylene and the gas flow of silane reaches 20%, the annealed place of amorphous semiconductor material layer
Strain value after reason is 120 μm, and when the ratio of ethylene and the gas flow of silane is greater than 20%, the amorphous semiconductor material
The bed of material is annealed, and treated that strain value has the tendency that rising, is greater than 120 μm of minimum value.
Inventor also found, when being free of ethylene in reaction gas, the amorphous semiconductor material layer of generation is annealed through 650 DEG C
After processing, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation is 314nm.
When the ratio of ethylene in reaction gas and the gas flow of silane is 5%, the amorphous semiconductor material layer of generation
After 650 DEG C of annealings, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation is 150nm.
When the ratio of ethylene in reaction gas and the gas flow of silane is 10%, the amorphous semiconductor material layer of generation
After 650 DEG C of annealings, the average grain diameter of the grain of the semiconductor layer 501 of formation is 67nm.
When the ratio of ethylene in reaction gas and the gas flow of silane is 20%, the amorphous semiconductor material layer of generation
After 650 DEG C of annealings, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation is 19nm.
In the range of 5% to 20%, as the ratio of the gas flow of ethylene and silane in reaction gas increases, generate
Amorphous semiconductor material layer through 650 DEG C annealing after, the average grain diameter of the crystal grain of the semiconductor layer 501 of formation gradually subtracts
It is small.
Therefore, in the range of 5% to 20%, with the ratio of the gas flow of ethylene and silane in the reaction gas
Increase, the ratio of the amount of the substance of carbon atom and silicon atom is also increasing in the semiconductor layer 501, the amorphous semiconductor of generation
The crystal grain that material layer crystallizes the semiconductor layer 501 of formation after annealed processing is gradually reduced, and what is generated after annealed processing answers
Change is also gradually reduced.
When choosing other gases as silicon-containing gas and the carbonaceous gas, need according in required reaction gas
The ratio of the amount of the substance of the amount and silicon atom of the substance of carbon atom controls the gas flow ratio of silicon-containing gas and carbonaceous gas
Value.In a specific embodiment, the inlet of the silicon-containing gas and the inlet of carbonaceous gas are respectively arranged with gas
Flowmeter, with the ratio of silicon-containing gas described in monitoring and measurement and the gas flow of carbonaceous gas.
In the specific embodiment, the ratio of the amount of the substance of carbon atom and silicon atom is 5% in the semiconductor layer 501
~20%, the model of the partial size of the crystal grain of the semiconductor layer 501 formed after the annealed processing crystallization of amorphous semiconductor material layer
It encloses for 19nm~150nm.The crystal grain of the semiconductor layer 501 formed after the annealed processing crystallization of amorphous semiconductor material layer
The range of partial size is directly related with the ratio of amount of the substance of carbon atom and silicon atom in the semiconductor layer 501.Tune can be passed through
The ratio of the amount of the substance of carbon atom and silicon atom in the whole semiconductor layer 501 adjusts crystal grain in the semiconductor layer 501
Partial size.The ratio of the amount of the substance of carbon atom and silicon atom can be by carbon containing gas in the reaction gas in the semiconductor layer 501
The direct decision of the gas flow of body and silicon-containing gas.
In the specific embodiment, during forming semiconductor layer 501, formed in grid line separate slot 301 first non-
Brilliant semiconductor material layer, due in the semiconductor material layer without grain structure, when depositing in the grid line separate slot 301,
It can be tightly combined between the inner wall of the grid line separate slot 301, the defects of inside will not form gap.It is subsequent to described non-
Brilliant semiconductor material layer, which carries out annealing, makes it change the semiconductor layer of more polycrystalline states 501, due to amorphous semiconductor material
Foreign atom in layer can reduce the grain size in semiconductor layer 501, so that semiconductor layer 501, has smaller crystal grain.
Crystal grain is smaller, it is meant that the strain generated in crystallization process is also smaller, and the stress for being applied to substrate 201 is small, reduces substrate
201 are extruded into a possibility that warpage occurs, so as to improve the performance of finally formed memory.
A kind of memory is additionally provided in a specific embodiment of the invention.
In the specific embodiment, the memory is 3D nand memory.
Referring to Fig. 6, for the partial structural diagram of the memory in a kind of specific embodiment of the invention.
In this specific embodiment, the memory includes: substrate 201；Memory heap positioned at 201 surface of substrate
Stack structure；Through the storage stack structure to the grid line separate slot on 201 surface of substrate；It is filled in the grid line separate slot
Semiconductor layer 501, doped with the foreign atom for reducing 501 grain size of semiconductor layer in the semiconductor layer 501.
The storage stack structure 702 includes tell somebody what one's real intentions are along vertical substrates the surface direction insulating layer 203 and control gate of stacking
Structure sheaf 500.
The substrate 201 can be described for Si substrate, Ge substrate, SiGe substrate, silicon-on-insulator or germanium on insulator etc.
Substrate 201 can also be laminated construction and other epitaxial structures, such as Si/SiGe or sige-on-insulator etc..In the specific reality
It applies in mode, the substrate 201 is Si substrate.
The grid line separate slot through storage stack structure to 201 surface of substrate, and the substrate 201 of grid line separate slot bottom
It is interior that there is source doping region 400.
In the specific embodiment, insulation side wall 401 is also covered on the side wall of the grid line separate slot, as semiconductor layer
Isolation structure between 501 and control gate structure sheaf 500.
The material of the semiconductor layer 501 is polycrystalline semiconductor material.Specifically, the material of the semiconductor layer 501 is
Polysilicon.And doped with foreign atom in the semiconductor layer 501, the foreign atom can reduce semiconductor layer 301
Grain size.In the specific embodiment, the foreign atom is carbon atom.
The ratio of carbon atom and silicon atom determines the grain size in semiconductor layer 501.In specific implementation of the invention
In mode, the ratio range of the amount of the substance of the amount and silicon atom of the substance of the carbon atom in the semiconductor layer 501 be 5% to
20%.The foreign atom is doped in situ in the semiconductor layer 501, can also be in the form of displacement atom or interstitial atom
In doping and the semiconductor layer 501.
The range of the partial size of the crystal grain of the semiconductor layer 705 is 19nm to 150nm, and crystal grain is uniform in size.One
It, can be by adjusting the object of silicon atom and carbon atom in the reaction gas for generating the semiconductor layer 705 in kind specific embodiment
The ratio of the amount of matter adjusts the particle size range of the crystal grain of the semiconductor layer 705.In a specific embodiment, work as doping
When thering is the annealing temperature of the amorphous semiconductor material layer of carbon atom to be 630 DEG C to 670 DEG C, the generation semiconductor layer 705 is controlled
Reaction gas in carbon atom substance amount and silicon atom substance amount ratio range within 5% to 20%, i.e.,
The range that can control the partial size of the crystal grain of the semiconductor layer 501 is 19nm to 150nm.
The semiconductor layer 501 fills the full grid line separate slot, is connected to the source doping region of grid line separate slot bottom
400, as the array common source for running through the storage stack structure.In the specific embodiment, the semiconductor layer 501 also covers
It covers to the top surface of the storage stack structure, it is subsequent that the storage stack structural top can be removed by flatening process
Semiconductor layer 501.
It is former doped with the doping that can reduce grain size in the semiconductor layer filled in the grid line separate slot of above-mentioned memory
Son, to reduce the stress that the semiconductor layer applies substrate, reduces so that the crystallite dimension in the semiconductor layer is lower
The problems such as warpage that substrate occurs, so that the performance of memory improves.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (11)
1. a kind of forming method of memory, which comprises the following steps:
A substrate is provided, the substrate surface is formed with stacked structure；
Grid line separate slot is formed in the stacked structure, the grid line separate slot is through the stacked structure to the substrate surface；
Semiconductor layer is formed in the grid line separate slot, the semiconductor layer is filled in the grid line separate slot, and the semiconductor
Doped with foreign atom in layer, the foreign atom can reduce the grain size of the semiconductor layer.
2. the forming method of memory according to claim 1, which is characterized in that the semiconductor layer forming method packet
It includes:
Using doping process in situ, deposition has the amorphous semiconductor material layer of foreign atom in the grid line separate slot, described
Amorphous semiconductor material layer fills the full grid line separate slot；
The amorphous semiconductor material layer is made annealing treatment, amorphous semiconductor material layer is crystallized, is converted to polycrystalline state
Semiconductor layer.
3. the forming method of memory according to claim 2, which is characterized in that the foreign atom is carbon atom.
4. the forming method of memory according to claim 3, which is characterized in that the semiconductor layer is polysilicon layer.
5. the forming method of memory according to claim 4, which is characterized in that deposited amorphous semiconductor material layer is adopted
Reaction gas includes: deposition gases and impurity gas, and the deposition gases include silicon-containing gas, the impurity gas be containing
Carbon gas.
6. the forming method of memory according to claim 4, which is characterized in that carbon atom and silicon in the semiconductor layer
The ratio of the amount of the substance of atom is 5%~20%.
7. the forming method of memory according to claim 5, which is characterized in that the gas of the carbonaceous gas includes second
At least one of alkene, acetylene, propylene, propine；The silicon-containing gas includes at least one of silane and disilane.
8. the forming method of memory according to claim 5, which is characterized in that the object of carbon atom in the reaction gas
The ratio of the amount of the substance of the amount and silicon atom of matter is 5%~20%.
9. the forming method of memory according to claim 2, which is characterized in that the temperature range of the annealing is
630 DEG C to 670 DEG C, the processing time is 0.5h~1.5h.
10. the forming method of memory according to claim 1, which is characterized in that the stacked structure includes along vertical
The sacrificial layer and insulating layer that substrate surface direction is alternately stacked, the forming method of the memory further include: forming semiconductor
Before layer, the sacrificial layer is removed along the grid line separate slot, forms the opening between adjacent insulating layer；In the opening
Form control gate structure sheaf.
11. the forming method of memory according to claim 1, which is characterized in that further include: forming the semiconductor
Before layer, the insulation side wall for covering the grid line separate slot side wall is formed.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176459A (en) * | 2019-06-19 | 2019-08-27 | 英特尔半导体(大连)有限公司 | Channel column and its manufacturing method for memory |
| CN110649032A (en) * | 2019-10-23 | 2020-01-03 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111725058A (en) * | 2020-07-23 | 2020-09-29 | 上海华力微电子有限公司 | Polycrystalline silicon thin film forming method and semiconductor structure forming method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035488A (en) * | 2012-11-07 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of groove-shaped semiconductor structure |
| US9406675B1 (en) * | 2015-03-16 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company Ltd. | FinFET structure and method of manufacturing the same |
| CN107863347A (en) * | 2016-09-22 | 2018-03-30 | 上海新昇半导体科技有限公司 | The method that microwave annealing prepares 3D NAND |
| CN108511358A (en) * | 2018-03-29 | 2018-09-07 | 长江存储科技有限责任公司 | 3D NAND detection structures and forming method thereof |
-
2018
- 2018-09-19 CN CN201811092078.5A patent/CN109326507B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035488A (en) * | 2012-11-07 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of groove-shaped semiconductor structure |
| US9406675B1 (en) * | 2015-03-16 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company Ltd. | FinFET structure and method of manufacturing the same |
| CN107863347A (en) * | 2016-09-22 | 2018-03-30 | 上海新昇半导体科技有限公司 | The method that microwave annealing prepares 3D NAND |
| CN108511358A (en) * | 2018-03-29 | 2018-09-07 | 长江存储科技有限责任公司 | 3D NAND detection structures and forming method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176459A (en) * | 2019-06-19 | 2019-08-27 | 英特尔半导体(大连)有限公司 | Channel column and its manufacturing method for memory |
| CN110649032A (en) * | 2019-10-23 | 2020-01-03 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN110649032B (en) * | 2019-10-23 | 2023-11-21 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111725058A (en) * | 2020-07-23 | 2020-09-29 | 上海华力微电子有限公司 | Polycrystalline silicon thin film forming method and semiconductor structure forming method |
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