CN208421674U - Low pressure difference linear voltage regulator - Google Patents
Low pressure difference linear voltage regulator Download PDFInfo
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- CN208421674U CN208421674U CN201820899470.XU CN201820899470U CN208421674U CN 208421674 U CN208421674 U CN 208421674U CN 201820899470 U CN201820899470 U CN 201820899470U CN 208421674 U CN208421674 U CN 208421674U
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- power tube
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Abstract
A kind of low pressure difference linear voltage regulator, it include: p-type power tube, the source of the p-type power tube is connect with the first input supply terminal, the drain terminal of the p-type power tube is connect with output voltage terminal, the p-type power tube has backgate, and the backgate of the p-type power tube is connect with the source of the p-type power tube；Driving circuit, the output end of the driving circuit are connect with the grid of the p-type power tube；Error amplifier, the output end of the error amplifier are connect with the input terminal of the driving circuit；Ripple introduces unit, and the ripple introduces unit and is connected between the output end of the error amplifier and the input terminal of the driving circuit.The low pressure difference linear voltage regulator improves power supply rejection ratio.
Description
Technical field
The utility model relates to electronic technology field more particularly to a kind of low pressure difference linear voltage regulators.
Background technique
Low pressure difference linear voltage regulator (low dropout regulator, LDO) can provide unrelated with power supply and environment
Stable output voltage, and there is certain load capacity, it has been widely used among all kinds of chips.
Relative to conventional linear voltage-stablizer, use PMOS tube as the low pressure difference linear voltage regulator of power tube, can make to input
Pressure difference between voltage and output voltage, minimum may approximately equal to the product of load current Yu PMOS tube conducting resistance, it is seen then that minimum
Conducting resistance keep corresponding low pressure difference linear voltage regulator pressure difference very low.In this case, when system input voltage and output
When voltage is close, very high efficiency can reach.
One important parameter of low pressure difference linear voltage regulator is power supply rejection ratio (Power Supply Rejection
Ratio, PSRR), i.e., input voltage and output voltage variation ratio.Since the factors such as ambient noise can be such that input voltage generates
Burr, so that output voltage stability is influenced, therefore a biggish power supply rejection ratio can make low pressure difference linear voltage regulator have one
A more stable output.
Therefore, the power supply rejection ratio for improving low pressure difference linear voltage regulator becomes the expectation of industry.
Utility model content
The utility model solves the problems, such as to be to provide a kind of low pressure difference linear voltage regulator, to improve low pressure difference linear voltage regulator
Power supply rejection ratio.
To solve the above problems, the utility model provides a kind of low pressure difference linear voltage regulator, comprising: p-type power tube, institute
The source for stating p-type power tube is connect with the first input supply terminal, and the drain terminal of the p-type power tube is connect with output voltage terminal, institute
P-type power tube is stated with backgate, the backgate of the p-type power tube is connect with the source of the p-type power tube；Driving electricity
Road, the output end of the driving circuit are connect with the grid of the p-type power tube；Error amplifier, the error amplifier
Output end is connect with the input terminal of the driving circuit；Ripple introduces unit, and the ripple introduces unit and is connected to the error
Between the output end of amplifier and the input terminal of the driving circuit.
Optionally, it includes NMOS tube that the ripple, which introduces unit, and the NMOS tube has backgate.
Optionally, it further includes first resistor and capacitor that the ripple, which introduces unit,.
Optionally, the backgate of the NMOS tube is connected to ground by the first resistor, the NMOS tube it is described
Backgate is connect by the capacitor with the second input supply terminal.
Optionally, the grid of the NMOS tube is connected to biased electrical pressure side, and the biased electrical pressure side is independently of described first
Input supply terminal.
Optionally, the low pressure difference linear voltage regulator further includes sampling resistor network, and the sampling resistor network connection exists
Between the output voltage terminal and ground.
Optionally, the reverse input end of the error amplifier connects reference voltage input terminal, the error amplifier it is same
Mutually input terminates the sampled voltage end of the sampling resistor network.
Optionally, the sampling resistor network includes concatenated second resistance and 3rd resistor, the sampled voltage end position
Between the second resistance and the 3rd resistor.
In the one aspect of technical solutions of the utility model, increases ripple in circuit and introduce unit, introduced using ripple
Back-gate effect inside unit, detection input power disturbance, and then circuit is influenced, input power disturbance is offset to output voltage
Interference improves power supply rejection ratio.
Further, it is acted on by the capacitive coupling that ripple introduces inside unit, input power ripple is injected into NMOS tube
Backgate, and influence the output of error amplifier, p-type power tube grid voltage adjusted by feedback control loop, plays stable output
Voltage improves power supply rejection ratio.
Detailed description of the invention
Fig. 1 is a kind of low differential voltage linear voltage stabilizer circuit figure of conventional architectures；
Fig. 2 is low pressure difference linear voltage regulator input voltage shown in Fig. 1 and corresponding output voltage schematic diagram；
Fig. 3 is the low differential voltage linear voltage stabilizer circuit figure of another conventional architectures；
Fig. 4 is low differential voltage linear voltage stabilizer circuit figure provided by the embodiment of the utility model.
Specific embodiment
A kind of circuit diagram of conventional low difference linear constant voltage regulator is as shown in Figure 1, include error amplifier 101, driving circuit
102, p-type power tube 103 and sampling resistor network 104 (being indicated with dotted line frame).When circuit works, the change of input power (Vin)
Change and output voltage (Vout) is passed to by p-type power tube 103.Error amplifier is passed to by sampling resistor network 104
101, generate driving signal.By driving circuit 102 control 103 grid voltage of p-type power tube, formed negative feedback loop, with
In stabilizing the output voltage.P-type power tube 103 has backgate, and backgate is connect with input power.It can in conjunction with the V diagram of Fig. 2
To see, this conventional low difference linear constant voltage regulator of Fig. 1 will affect p-type when input power (input voltage) has disturbance up and down
Power tube 103, causes output voltage to disturb, and just replys original level against error amplifier 101.
Fig. 3 is the circuit diagram of another low pressure difference linear voltage regulator, it is conventional low difference linear constant voltage regulator shown in Fig. 1
On the basis of, the backgate of p-type power tube 103 is connect by resistance 105 with another input power, other aspects and Fig. 1 phase
Together.
Due to the intervention of resistance 105, the V of p-type power tube 103BS(B is backgate, and S is source) is not 0, generates backgate effect
It answers, makes 103 threshold voltage (V of p-type power tubeTH) with back gate source voltage (VBS) change and change.When the first input power occurs
Up and down when disturbance, it is assumed that the grid voltage of p-type power tube 103 is constant, then due to the gate source voltage (V of p-type power tube 103GS) become
Change, it will cause accordingly to export curent change, to influence output voltage (Vout).And it is introduced by resistance 105 and generates backgate
Effect, input power disturbance will cause p-type power tube threshold voltage variation.But due to the electric current and gate-source of p-type power tube 103
Voltage is related to threshold voltage, therefore the introducing of back-gate effect, reduces the output curent change of p-type power tube 103, to make
Output voltage is more stable.
However, due to introducing resistance 105, being equivalent to p-type power tube 103 in low pressure difference linear voltage regulator shown in Fig. 3
Resistance substrate increase, cause (p-type power tube 103) to be easier to cause latch-up, generate power supply to the punchthrough current on ground, damage
Bad respective chip.
For this purpose, the utility model, which originally provides one kind, can be improved power supply rejection ratio, for reducing input voltage disturbance to defeated
The low pressure difference linear voltage regulator of voltage disturbance out.
More clearly to indicate, the utility model is described in detail with reference to the accompanying drawing.
The utility model embodiment provides a kind of low pressure difference linear voltage regulator, please refers to Fig. 4.
The low pressure difference linear voltage regulator includes p-type power tube 203, driving circuit 202, error amplifier 201 and ripple
Introduce unit 205.
The source of p-type power tube 203 is connect with the first input supply terminal Vin, the drain terminal and output electricity of p-type power tube 203
Pressure side Vout connection, p-type power tube 203 have backgate, and the backgate of p-type power tube 203 is connect with the source of p-type power tube 203,
I.e. the backgate of p-type power tube 203 also connects the first input supply terminal Vin.Also, the backgate of p-type power tube 203 and the first input
There is no resistance between power end Vin.
The output end of driving circuit 202 is connect with the grid of p-type power tube 203.
The output end of error amplifier 201 is connect with the input terminal of driving circuit 202.
Ripple introduces unit 205 and is connected between the output end of error amplifier 201 and the input terminal of driving circuit 202.
With continued reference to FIG. 4, the low pressure difference linear voltage regulator further includes sampling resistor network 204, sampling resistor network
204 are connected between output voltage terminal and ground (not marking).
The reverse input end of error amplifier 201 connects reference voltage input terminal Vref, the homophase input of error amplifier 201
Terminate the sampled voltage end (not marking) of sampling resistor network 204.
In the present embodiment, sampling resistor network 204 includes concatenated second resistance 2041 and 3rd resistor 2042, described to adopt
Sample voltage end is between second resistance 2041 and 3rd resistor 2042.What second resistance 2041 was not connect with 3rd resistor 2042
One termination output voltage terminal Vout, one end ground connection that 3rd resistor 2042 is not connect with second resistance 2041.
In the present embodiment, it may include NMOS tube 2051 that ripple, which introduces unit 205, and NMOS tube 2051 has backgate.It is described
The other structures that backgate further introduces unit 205 with ripple cooperate, subsequent to will be further illustrated.
In the present embodiment, it can also include first resistor 2052 and capacitor 2053 that ripple, which introduces unit 205,.Ripple introduces single
The backgate of the NMOS tube 2051 of member 205 is connect by first resistor 2052 with ground (not marking), and the backgate of NMOS tube 2051 passes through
Capacitor 2053 is connect with the second input supply terminal (not marking).Ripple introduces the grid of the NMOS tube 2051 of unit 205, is connected to
Biased electrical pressure side Vbias, biased electrical pressure side Vbias are independently of the first input supply terminal Vin.
In low pressure difference linear voltage regulator provided by the present embodiment, between driving circuit 202 and error amplifier 201,
It increases ripple and introduces unit 205.Wherein, it includes NMOS tube 2051, first resistor 2052 and capacitor that ripple, which introduces unit 205,
2053.Also, the segmentum intercalaris of the input terminal of the output end and driving circuit 202 of the drain terminal of NMOS tube 2051 and error amplifier 201
Point is connected, while the source ground connection of NMOS tube 2051, the grid of NMOS tube 2051 meet fixed bias voltage Vbias, NMOS
The backgate of pipe 2051 is connect with first resistor 2052 and capacitor 2053 respectively, the other end ground connection of first resistor 2052, capacitor
2053 another termination inputs the second input supply terminal.
At work, the sampling of output voltage (Vout) and sampling resistor network of the generation of circuit output voltage end Vout
Voltage end voltage (FB) meets following relationship, and (it should be noted that in this specification, Vin and Vout also make both as mark
For the expression of relevant voltage):
Wherein, R2 is the resistance of second resistance 2041, and R3 is the resistance of 3rd resistor 2042.
In this case, the output of error amplifier 201 is superimposed with 2051 pull-down current of NMOS tube that ripple introduces unit 205
Driving signal is generated, the grid voltage of p-type power tube 203 is controlled by driving circuit 202.2051 grid voltage of NMOS tube be with
The unrelated fixed bias voltage (Vbias) of input power (Vin), the work of NMOS tube 2051 meet in saturation region, drain terminal electric current
Following relationship:
Above-mentioned formula (2) is known formula, μnFor the electron mobility of NMOS tube 2051, COXFor the grid oxygen of NMOS tube 2051
Capacitor, W are the channel width of NMOS tube 2051, and L is the channel length of NMOS tube 2051, VGSFor the gate source voltage of NMOS tube 2051
(the present embodiment is fixed as Vbias), VTHFor the threshold voltage of NMOS tube 2051.
As it can be seen that the drain terminal size of current of NMOS tube 2051 and its threshold voltage VTHIt is related.
And 2051 backgate of NMOS tube is grounded by first resistor 2052, and when power good, back gate voltage (VBS) it is 0,
When power supply generates disturbance, its back grid potential is caused to change by the coupling of capacitor 2053 by electric source disturbance, back gate voltage VBSIt is not
0, metal-oxide-semiconductor back-gate effect is generated, the threshold voltage (V of NMOS tube 2051 is madeTH) corresponding change, and then influence 2051 drain terminal of NMOS tube
Electric current.
As it can be seen that being imitated when the disturbance of the input power (Vin) of the first input supply terminal Vin through the backgate of NMOS tube 2051
It answers, the node between error amplifier 201 and driving circuit 202 changes sensed in advance input power, passes through driving circuit 202
203 grid voltage of p-type power tube is adjusted accordingly in advance, so that output voltage (Vout) disturbance be made to become smaller.
In summary content introduces unit it is found that the present embodiment increases ripple in circuit, is introduced in unit using ripple
The back-gate effect in portion, detection input power disturbance, and then circuit is influenced, interference of the input power disturbance to output voltage is offset,
Improve power supply rejection ratio.
Further, it in the present embodiment, is acted on by the capacitive coupling that ripple introduces inside unit, by input power ripple
The backgate of NMOS tube 2051 is injected, and influences the output of error amplifier 201,203 grid of p-type power tube are adjusted by feedback control loop
Pole tension is played and is stabilized the output voltage, and improves power supply rejection ratio.
Although the utility model discloses as above, the utility model is not limited to this.Anyone skilled in the art,
It does not depart from the spirit and scope of the utility model, can make various changes or modifications, therefore the protection scope of the utility model
It should be defined by the scope defined by the claims..
Claims (8)
1. a kind of low pressure difference linear voltage regulator characterized by comprising
The source of p-type power tube, the p-type power tube is connect with the first input supply terminal, the drain terminal of the p-type power tube with it is defeated
Voltage end connects out, and the p-type power tube has backgate, the source of the backgate of the p-type power tube and the p-type power tube
End connection；
Driving circuit, the output end of the driving circuit are connect with the grid of the p-type power tube；
Error amplifier, the output end of the error amplifier are connect with the input terminal of the driving circuit；
Ripple introduces unit, and the ripple introduces the output end and the driving circuit that unit is connected to the error amplifier
Between input terminal.
2. low pressure difference linear voltage regulator as described in claim 1, which is characterized in that it includes NMOS that the ripple, which introduces unit,
Pipe, the NMOS tube have backgate.
3. low pressure difference linear voltage regulator as claimed in claim 2, which is characterized in that it further includes first that the ripple, which introduces unit,
Resistance and capacitor.
4. low pressure difference linear voltage regulator as claimed in claim 3, which is characterized in that the backgate of the NMOS tube passes through institute
It states first resistor to be connected to ground, the backgate of the NMOS tube is connect by the capacitor with the second input supply terminal.
5. low pressure difference linear voltage regulator as claimed in claim 4, which is characterized in that the grid of the NMOS tube is connected to biasing
Voltage end, the biased electrical pressure side is independently of first input supply terminal.
6. low pressure difference linear voltage regulator as described in claim 1, which is characterized in that it further include sampling resistor network, it is described to adopt
Sample resistor network is connected between the output voltage terminal and ground.
7. low pressure difference linear voltage regulator as claimed in claim 6, which is characterized in that the reverse input end of the error amplifier
Reference voltage input terminal is connect, the homophase input of the error amplifier terminates the sampled voltage end of the sampling resistor network.
8. low pressure difference linear voltage regulator as claimed in claim 7, which is characterized in that the sampling resistor network includes concatenated
Second resistance and 3rd resistor, the sampled voltage end is between the second resistance and the 3rd resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820899470.XU CN208421674U (en) | 2018-06-11 | 2018-06-11 | Low pressure difference linear voltage regulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820899470.XU CN208421674U (en) | 2018-06-11 | 2018-06-11 | Low pressure difference linear voltage regulator |
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| CN208421674U true CN208421674U (en) | 2019-01-22 |
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| CN201820899470.XU Active CN208421674U (en) | 2018-06-11 | 2018-06-11 | Low pressure difference linear voltage regulator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108762361A (en) * | 2018-06-11 | 2018-11-06 | 厦门元顺微电子技术有限公司 | Low pressure difference linear voltage regulator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108762361A (en) * | 2018-06-11 | 2018-11-06 | 厦门元顺微电子技术有限公司 | Low pressure difference linear voltage regulator |
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