CN208336228U - A kind of transistor arrangement using embedded type bit line - Google Patents

Abstract

The utility model provides a kind of transistor arrangement using embedded type bit line, which includes that groove, the first wordline groove, the second wordline groove, embedded type word line, bit line trenches and embedded type bit line are sunk in substrate, isolation structure, drain electrode.The utility model sinks to the structure that groove changes transistor by drain electrode, so that transistor has the bit line of flush type, the area that groove increases the node contact of source electrode and drain electrode is sunk in the drain electrode formed in transistor, and is conducive to the etching of wordline, reduces channel leakage.The transistor arrangement using embedded type bit line of the utility model can be applied in active area of different shapes, and can be applied in different electrical circuits.

Description

A kind of transistor arrangement using embedded type bit line

Technical field

The utility model belongs to semiconductor integrated circuit field, is related to a kind of transistor arrangement using embedded type bit line.

Background technique

Semiconductor memory (semi-conductor memory) is a kind of depositing using semiconductor circuit as storage media Reservoir, built-in storage are exactly to be made of the semiconductor integrated circuit of referred to as memory chip.Semiconductor memory can by its function It is divided into: random access memory (abbreviation RAM) and read-only memory (read-only ROM).With small in size, storage speed is fast, storage The advantage that density is high, is easy with logic circuit interface.RAM include DRAM (dynamic random access memory) and SRAM (it is static with Machine accesses memory), when shutdown or power-off, information therein can all lose therewith.DRAM is mainly used for the main memory (master of memory Body portion), SRAM is mainly used for cache memory.ROM is mainly used for BIOS memory.Semiconductor memory is by its manufacture Technique can be divided into: bipolar transistor memory and MOS transistor memory.

DRAM is one of big main product of semiconductor memory three (DRAM, NAND Flash, NOR Flash).DRAM: dynamic State random access memory (Dynamic RAM), " dynamic " two word refer at regular intervals, refresh charge primary, otherwise interior The data in portion can disappear.This is because the basic unit of DRAM is that a transistor adds a capacitor, and electricity consumption has no electricity Lotus indicates digital information 0 and 1, and capacity fall off quickly, causes to read information error, need periodicity to prevent capacity fall off Ground is to the capacitor charging of DRAM, therefore DRAM speed ratio SRAM is slow.On the other hand, this simple memory module is but also DRAM Integrated level is much higher than SRAM, and a DRAM memory cell only needs a transistor and a small capacitances, and each sram cell needs Four to six transistors and other parts are wanted, therefore DRAM is more advantageous than SRAM in high density (large capacity) and in price. SRAM is chiefly used in the place high to performance requirement (the level-one level 2 buffering of such as CPU), and DRAM is then mainly used for computer The fields such as memory bar.

Fig. 1 is shown as a kind of planar cloth of the single active area 101 of DRAM in the prior art, wordline 102 and bit line 103 Office, Fig. 2 are shown as sectional view of the structure shown in Fig. 1 in A0 plane, and Fig. 3 is shown as the cutting in B0 plane of structure shown in Fig. 1 Face figure, wherein also show the cushion oxide layer 104 between active area 101 and wordline 102 in Fig. 2 and Fig. 3 and be located at Insulating layer 105 between wordline 102 and bit line 103 further illustrates the isolation structure 106 of isolation active area 101 in Fig. 3.

As semiconductor storage unit becomes highly integrated, the area of unit cell on a semiconductor substrate can correspondingly by It is tapered small, so that the area of node contact (Node Contact) is also reduced accordingly.

Therefore, how the new transistor arrangement of one kind is provided and improves the electrical property of transistor to increase node contact area Can, become those skilled in the art's important technological problems urgently to be resolved.

Utility model content

In view of the foregoing deficiencies of prior art, embedded type bit line is used the purpose of this utility model is to provide a kind of Transistor arrangement, for solve in the prior art because device Highgrade integration, node contact area reduce, lead to device The problem of performance declines.

In order to achieve the above objects and other related objects, the utility model provides a kind of transistor using embedded type bit line Structure, comprising:

Substrate；

Isolation structure is formed in the substrate, and the isolation structure defines multiple active areas in the substrate；

Groove is sunk in drain electrode, is formed in the active area, and the drain electrode is sunk to groove and is folded in the active area middle section, And by the top surface of the substrate, the bottom surface that groove is sunk in the drain electrode is relatively shallower than the bottom surface of the isolation structure；

First wordline groove and the second wordline groove, are all formed in the substrate, by the top surface of the substrate, described The bottom surface of one wordline groove and the second wordline groove is all relatively shallower than the bottom surface of the isolation structure and is relatively deeper than Groove floor is sunk in the drain electrode, and the first wordline groove and the second wordline groove all pass through the active area, by The first wordline groove and the second wordline groove interval, the active area include the first source region, drain region with Second source region, the drain region is between first source region and second source region；

Embedded type word line is formed in the first wordline groove and the second wordline groove；

Bit line trenches are formed in the substrate, and the bit line trenches pass through the drain electrode and sink to groove, and the bit line Groove passes through the part that groove is sunk in the drain electrode and exposes the drain region top surface；And

Embedded type bit line is formed in the bit line trenches, and the metal top surface of the embedded type bit line is lower than the substrate Top surface, the top surface of the substrate includes the upper surface of first source region and the upper surface of second source region, And the top surface of the substrate is in the region in same active area and between first source region and second source region It is that insulation is buried.

Optionally, the transistor arrangement further includes bit line insulating protective layer, and the bit line insulating protective layer is formed in institute State embedded type bit line top surface.

Optionally, cushion oxide layer, the lining are all formed in the first wordline groove and the second wordline groove Pad oxide surrounds bottom surface and the side wall of the embedded type word line.

Optionally, the top surface of the embedded type word line is lower than the bottom surface of the embedded type bit line.

Optionally, the bit line trenches sink to groove also cross multiple drain electrodes.

Optionally, it in the plane figure of the transistor arrangement, the active area, the embedded type word line and described buries Entering formula bit line includes any one in linear type, broken line type and undaform.

Optionally, the first wordline groove and the second wordline groove sink to the both ends of groove with described drain respectively It is connected or overlaps mutually.

As described above, the transistor arrangement using embedded type bit line of the utility model, has the advantages that this reality The structure that groove changes transistor is sunk to by drain electrode with the novel transistor arrangement using embedded type bit line, so that transistor Bit line with flush type, the drain electrode formed in transistor sink to groove and increase source electrode (Source) and drain (Drain) The area of node contact, and be conducive to the etching of wordline, reduce channel leakage.The crystalline substance using embedded type bit line of the utility model Body pipe structure can be applied in active area of different shapes, and can be applied in different electrical circuits.

Detailed description of the invention

Fig. 1 is shown as a kind of planar cloth of the single active area 101 of DRAM in the prior art, wordline 102 and bit line 103 Office.

Fig. 2 is shown as sectional view of the structure shown in Fig. 1 in A0 plane.

Fig. 3 is shown as sectional view of the structure shown in Fig. 1 in B0 plane

Fig. 4 is shown as the top view of single active area in the substrate provided.

Fig. 5 is shown as the sectional view of substrate A1 plane shown in Fig. 4.

Fig. 6 is shown as the sectional view of substrate A2 plane shown in Fig. 4.

Fig. 7 is shown as the sectional view of substrate A3 plane shown in Fig. 4.

Fig. 8 is shown as the sectional view of substrate B1 plane shown in Fig. 4.

Fig. 9 is shown as single active area and the plane figure of groove is sunk in drain electrode.

Figure 10 a is shown as formed as the sectional view that obtained structure A1 plane shown in Fig. 9 after groove is sunk in drain electrode.

It is flat that Figure 10 b is shown as fill insulant obtained structure A1 shown in Fig. 9 after drain electrode is sunk in groove The sectional view in face.

Figure 11 a is shown as formed as the sectional view that obtained structure A2 plane shown in Fig. 9 after groove is sunk in drain electrode.

It is flat that Figure 11 b is shown as fill insulant obtained structure A2 shown in Fig. 9 after drain electrode is sunk in groove The sectional view in face.

Figure 12 a is shown as formed as the sectional view that obtained structure A3 plane shown in Fig. 9 after groove is sunk in drain electrode.

It is flat that Figure 12 b is shown as fill insulant obtained structure A3 shown in Fig. 9 after drain electrode is sunk in groove The sectional view in face.

Figure 13 a is shown as formed as the sectional view that obtained structure B1 plane shown in Fig. 9 after groove is sunk in drain electrode.

It is flat that Figure 13 b is shown as fill insulant obtained structure B1 shown in Fig. 9 after drain electrode is sunk in groove The sectional view in face.

Figure 14 is shown as single active area, groove, the first wordline groove, the second wordline groove, flush type word are sunk in drain electrode The plane figure of line.

Figure 15 is shown as formed as the first wordline groove and the second wordline groove in substrate, and forms embedded type word line The sectional view of obtained structure A1 plane shown in Figure 14 after in one wordline groove and the second wordline groove.

Figure 16 is shown as formed as the first wordline groove and the second wordline groove in substrate, and forms embedded type word line The sectional view of obtained structure A2 plane shown in Figure 14 after in one wordline groove and the second wordline groove.

Figure 17 is shown as formed as the first wordline groove and the second wordline groove in substrate, and forms embedded type word line The sectional view of obtained structure A3 plane shown in Figure 14 after in one wordline groove and the second wordline groove.

Figure 18 is shown as formed as the first wordline groove and the second wordline groove in substrate, and forms embedded type word line The sectional view of obtained structure B1 plane shown in Figure 14 after in one wordline groove and the second wordline groove.

Figure 19 is shown as single active area, groove, the first wordline groove, the second wordline groove, flush type word are sunk in drain electrode Line, bit line trenches, embedded type bit line plane figure.

The section of obtained structure A1 plane shown in Figure 19 after Figure 20 a is shown as formed as bit line trenches in substrate Figure.

Obtained structure A1 shown in Figure 19 after Figure 20 b is shown as formed as embedded type bit line in the bit line trenches The sectional view of plane.

The section of obtained structure A2 plane shown in Figure 19 after Figure 21 a is shown as formed as bit line trenches in substrate Figure.

Obtained structure A2 shown in Figure 19 after Figure 21 b is shown as formed as embedded type bit line in the bit line trenches The sectional view of plane.

The section of obtained structure A3 plane shown in Figure 19 after Figure 22 a is shown as formed as bit line trenches in substrate Figure.

Obtained structure A3 shown in Figure 19 after Figure 22 b is shown as formed as embedded type bit line in the bit line trenches The sectional view of plane.

The section of obtained structure B1 plane shown in Figure 19 after Figure 23 a is shown as formed as bit line trenches in substrate Figure.

Obtained structure B1 shown in Figure 19 after Figure 23 b is shown as formed as embedded type bit line in the bit line trenches The sectional view of plane.

Figure 24 is shown as a kind of active area array, groove is sunk in drain electrode, the planar cloth of embedded type word line, embedded type bit line Office.

Figure 25 is shown as structure shown in Figure 24 in the sectional view of A4 plane.

Figure 26 is shown as structure shown in Figure 24 in the sectional view of A5 plane.

Figure 27 is shown as structure shown in Figure 24 in the sectional view of B2 plane.

Component label instructions

101 active areas

102 wordline

103 bit lines

104 cushion oxide layers

105 insulating layers

106 isolation structures

201 substrates

202 isolation structures

203 active areas

2031 first source regions

2032 drain regions

2033 second source regions

Groove is sunk in 204 drain electrodes

205 insulating materials

205 ' insulation material layers

205 " isolation materials

206 first wordline grooves

207 second wordline grooves

208,208a, 208b embedded type word line

208 ' wordline conductive materials

209 bit line trenches

210 embedded type bit lines

210 ' bit line conductive materials

211 bit line insulating protective layers

212 cushion oxide layers

Plane where groove floor is sunk in M drain electrode

Plane where N isolation structure bottom surface

Plane where E wordline trench bottom surfaces

A0, A1, A2, A3, A4, A5, B0, B1, B2 plane

Specific embodiment

Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer With carrying out various modifications or alterations under the spirit without departing from the utility model.

Fig. 4 is please referred to Figure 27.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in schema then Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind Become, and its assembly layout kenel may also be increasingly complex.

Embodiment one

The utility model provides a kind of transistor arrangement using embedded type bit line, including substrate, isolation structure, drain electrode are heavy Enter groove, the first wordline groove, the second wordline groove, embedded type word line and embedded type bit line, wherein the isolation structure exists Multiple active areas are defined in the substrate, the drain electrode is sunk to groove and is formed in the active area.

Figure 19 is please referred to, is shown as in the utility model single active area 203, groove 204, the first wordline ditch are sunk in drain electrode Slot 206, the second wordline groove 207, embedded type word line 208a, embedded type word line 208b, bit line trenches 209, embedded type bit line 210 Plane figure, it is seen then that the drain electrode is sunk to groove 204 and is folded in 203 middle section of active area.

Figure 23 is please referred to, the sectional view of transistor arrangement B1 plane shown in Figure 19 is shown as, it is seen then that described One wordline groove 206 and the second wordline groove 207 are all formed in the substrate 201, and the first wordline groove 206 and institute It states the second wordline groove 207 and all passes through the active area, by the first wordline groove 206 and the second wordline groove 207 intervals, the active area include the first source region 2031, drain region 2032 and the second source region 2033, the leakage Polar region domain 2032 is between first source region 2031 and second source region 2033.

Specifically, the bit line trenches 209 are formed in the substrate 201, and the bit line trenches 209 pass through the leakage Groove 204 is sunk in pole.The bit line trenches 209 pass through the part that groove 204 is sunk in the drain electrode and expose the drain region 2032 top surfaces.It should be pointed out that in an array, the bit line trenches 209 can sink to groove also cross multiple drain electrodes 204。

It should be pointed out that groove 204 and the bit line trenches 209 are sunk in the drain electrode either false relation, It can be aligned relationship, in the present embodiment, the drain electrode sinks to groove 204 and the bit line trenches 209 preferably using staggeredly closing System.

Specifically, shown in Figure 23 plane N where plane M, isolation structure bottom surface where groove floor are sunk in drain electrode and Plane E where wordline trench bottom surfaces, it is seen then that by the top surface of the substrate, the bottom surface that groove 204 is sunk in the drain electrode is relatively shallower In the bottom surface of the isolation structure 202, the first wordline groove 206 is all opposite with the bottom surface of the second wordline groove 207 Relatively it is shallower than the bottom surface of the isolation structure 202 and is relatively deeper than the drain electrode and sinks to 204 bottom surface of groove.

Specifically, the first wordline groove 206 sinks to groove with the drain electrode respectively with the second wordline groove 207 204 both ends are connected or overlap mutually, and the embedded type word line 208a and the embedded type word line 208b are respectively formed in described the In one wordline groove 206 and the second wordline groove 207, the embedded type bit line 210 is formed in the bit line trenches 209 In, and the metal top surface of the embedded type bit line 210 is lower than the top surface of the substrate 201, the top surface of the embedded type word line is low In the bottom surface of the embedded type bit line, the top surface of the substrate includes the upper surface and second source of first source region The upper surface in polar region domain, and the top surface of the substrate is in same active area and first source region and second source electrode Region between region is that insulation is buried.

Specifically, being all formed with cushion oxide layer in the first wordline groove 206 and the second wordline groove 207 212, the cushion oxide layer 212 surrounds bottom surface and the side wall of the embedded type word line 210.The transistor arrangement further includes position Line insulating protective layer 211, the bit line insulating protective layer 211 are formed in 210 top surface of embedded type bit line.The bit line insulation Protective layer 211 is different from the material of the insulation material layer 205 ', for example, the material of the bit line insulating protective layer 211 is optional Silica can be selected with the material of silicon nitride, the insulation material layer 205 '.

The transistor arrangement using embedded type bit line of the utility model can be applied in active area of different shapes, and can To apply in different electrical circuits.As an example, Figure 24 is shown as a kind of active area array, groove, flush type are sunk in drain electrode Wordline, the plane figure of embedded type bit line.Figure 25 is shown as structure shown in Figure 24 in the sectional view of A4 plane.Figure 26 is shown as figure Sectional view of the structure shown in 24 in A5 plane.Figure 27 is shown as structure shown in Figure 24 in the sectional view of B2 plane.In the present embodiment, In the plane figure of the transistor arrangement, the active area 203, the embedded type word line 208 and the embedded type bit line 210 be linear type, and in other embodiments, the shape of active area, wordline, bit line in transistor arrangement can be according to reality It needs to be adjusted, such as can also be broken line type or undaform, should not excessively limit the protection scope of the utility model herein.

The utility model sinks to groove due to being formed with drain electrode using the transistor arrangement of embedded type bit line, so that crystal The structure of pipe changes, the bit line with flush type, and the drain electrode formed in transistor sinks to groove and increases source electrode (Source) and the area of the node contact of drain electrode (Drain), and be conducive to the etching of wordline, reduce channel leakage.

Embodiment two

The present embodiment provides a kind of manufacturing methods, for manufacturing the crystal described in embodiment one using embedded type bit line Pipe structure, method includes the following steps:

Referring initially to Fig. 8, step S1 being executed: a substrate 201 being provided, isolation structure 202 is equipped in the substrate, it is described Isolation structure defines multiple active areas 203 in the substrate.

Specifically, the substrate 201 includes but is not limited to the semiconductor substrates such as Si, Ge, SiGe, SOI.The isolation structure 202 can be shallow trench isolation (Shallow Trench Isolation, abbreviation STI).

As an example, referring to Fig. 4, being shown as the top view of single active area 203 in substrate, wherein substrate is in Fig. 4 institute Show the sectional view of A1 plane as shown in figure 5, the sectional view of substrate A2 plane shown in Fig. 4 is as shown in fig. 6, substrate is shown in Fig. 4 The sectional view of A3 plane is as shown in fig. 7, and earlier figures 8 are shown as the sectional view of substrate B1 plane shown in Fig. 4.

In the present embodiment, the active area 203 is linear type.In other embodiments, the shape of the active area 203 with Arrangement mode can also be adjusted according to actual needs, such as the active area 203 can also be broken line type or undaform, this Place should not excessively limit the protection scope of the utility model.

Referring next to Figure 13 a and Figure 13 b, step S2 is executed: forming drain electrode and sink to groove 204 in the active area 203 In, and fill insulant 205 is sunk in groove 204 in the drain electrode.

Specifically, forming the drain electrode by techniques such as photoetching, etchings sinks to groove 204, pass through chemical vapor deposition, object Physical vapor deposition or other deposition method fill insulants 205 are sunk in groove 204 in the drain electrode.The insulating materials 205 material includes but is not limited to silica.

As an example, referring to Fig. 9, be shown as the plane figure that single active area 203 sinks to groove 204 with drain electrode, In, the utility model forms drain electrode and sinks to obtained structure A1 plane, A2 plane and A3 plane shown in Fig. 9 after groove Sectional view is respectively as shown in Figure 10 a, 11a and Figure 12 a, fill insulant obtained structure after drain electrode is sunk in groove The sectional view of A1 plane shown in Fig. 9, A2 plane and A3 plane is respectively as shown in Figure 10 b, 11b and Figure 12 b, and earlier figures 13a It is shown as formed as the sectional view that obtained structure B1 plane shown in Fig. 9 after groove is sunk in drain electrode, earlier figures 13b is shown as The sectional view of fill insulant obtained structure B1 plane shown in Fig. 9 after drain electrode is sunk in groove.

Specifically, the drain electrode is sunk to groove 204 and is folded in 203 middle section of active area (as shown in Figure 9), and by described The top surface of substrate, described drain sink to bottom surface (plane M where sinking to groove floor referring to drain electrode in Figure 13 a) phase of groove 204 To the bottom surface for being relatively shallower than the isolation structure 202 (referring to plane N where structure floor is isolated in Figure 13 a).

Figure 18 is please referred to again, executes step S3: forming the first wordline groove 206 and the second wordline groove 207 in the lining In bottom 201, and embedded type word line is formed in the first wordline groove 206 and the second wordline groove 207, wherein bury Enter formula wordline 208a to be located in the first wordline groove 206, embedded type word line 208b is located at the second wordline groove 207 In.

As an example, form the embedded type word line the following steps are included:

S3-1: cushion oxide layer 212 is formed in the first wordline groove using thermal oxidation technology or other deposition methods 206 and the second wordline groove 207 bottom and side wall；

S3-2: filling wordline conductive material 208 ' is in the first wordline groove 206 and the second wordline groove 207 In；

S3-3: the wordline conductive material 208 ' is etched back to the top surface of the wordline conductive material 208 ' lower than the leakage The bottom surface of groove is sunk in pole；

S3-4: filling isolation material 205 " is remaining in the first wordline groove 206 and the second wordline groove 207 Space, obtain the embedded type word line 208a and the embedded type word line 208b.

Specifically, by the top surface of the substrate, the top surface of the embedded type word line 208a and the embedded type word line 208b The bottom surface (plane M where groove floor is sunk in drain electrode is shown in Figure 18) of groove is sunk to lower than described drain.First word Line trenches 206 are connected or overlap mutually with the both ends that the second wordline groove 207 sinks to groove 204 with the drain electrode respectively.

In the present embodiment, the embedded type word line 208a and the embedded type word line 208b select linear type.In other realities It applies in example, the embedded type bit line can also be using other linear, such as broken line type or undaform should not excessively limit this herein The protection scope of utility model.

As an example, please refer to Figure 14, be shown as in the utility model single active area 203, groove 204 is sunk in drain electrode, The plane figure of first wordline groove 206, the second wordline groove 207, embedded type word line 208a, embedded type word line 208b, wherein The sectional view of obtained structure A1 plane shown in Figure 14 is as shown in figure 15 after execution step S3, the A2 plane shown in Figure 14 Sectional view it is as shown in figure 16, the sectional view of A3 plane shown in Figure 14 is as shown in figure 17, and earlier figures 18 are shown as executing step The sectional view of obtained structure B1 plane shown in Figure 14 after rapid S3.

Specifically, the bottom surface of the first wordline groove 206 and the second wordline groove 207 is (referring to wordline in Figure 18 Plane E where trench bottom surfaces) all relatively it is shallower than the bottom surface of the isolation structure 202 (referring to isolation structure floor institute in Figure 18 It in plane N) and is relatively deeper than the drain electrode and sinks to groove floor (plane where sinking to groove floor referring to drain electrode in Figure 18 M), the first wordline groove 206 all passes through the active area 203 with the second wordline groove 207, by first word Line trenches 206 and the second wordline groove 207 interval, the active area include the first source region 2031, drain region 2032 and second source region 2033, the drain region 2032 be located at first source region 2031 and second source electrode Between region 2033, and the top surface of the drain region 2032 is in the bottom surface institute coverage area for draining and sinking to groove 204.

Figure 23 a and Figure 23 b are please referred to again, executes step S4: being formed bit line trenches 209 in the substrate 201, and formed Embedded type bit line 210 is in the bit line trenches 209.

Specifically, forming the bit line trenches 209 using etching technics, and the bit line trenches 209 are formed in etching When, using the substrate 201 as etch stop layer.For example, being with monocrystalline silicon if the material of the substrate 201 is monocrystalline silicon Etch stop layer.

As an example, form the embedded type bit line 210 the following steps are included:

S4-1: filling bit line conductive material 210 ' is in the bit line trenches 209；

S4-2: institute's bit line conductive material 210 ' is etched back to the top surface of institute's bit line conductive material 210 ' lower than the lining The top surface at bottom 201, wherein remaining institute's bit line conductive material 210 ' is as bit line after being etched back to；

S4-3: the remaining space in the bit line trenches 209 of fill insulant layer 205 ' obtains the flush type position Line 210.

As an example, further including to form bit line insulating protective layer 211 in described before filling the insulation material layer 205 ' The step of 210 top surface of embedded type bit line, the bit line insulating protective layer 211 is different from the material of the insulation material layer 205 ', For example, silicon nitride can be selected in the material of the bit line insulating protective layer 211, the material of the insulation material layer 205 ' can be selected two Silica.

As an example, please refer to Figure 19, be shown as in the utility model single active area 203, groove 204 is sunk in drain electrode, First wordline groove 206, embedded type word line 208a, embedded type word line 208b, bit line trenches 209, buries second wordline groove 207 Enter the plane figure of formula bit line 210, wherein obtained structure is being schemed after the utility model forms bit line trenches in substrate The sectional view of A1 plane shown in 19, A2 plane and A3 plane as shown in Figure 20 a, Figure 21 a and Figure 22 a, form flush type position respectively Line in the bit line trenches distinguish later by the sectional view of obtained structure A1 plane, A2 plane shown in Figure 19 and A3 plane As shown in Figure 20 b, Figure 21 b and Figure 22 b, and earlier figures 23a be shown as formed as bit line trenches in substrate after obtained knot The sectional view of structure B1 plane shown in Figure 19, gained after Figure 23 b is shown as formed as embedded type bit line in the bit line trenches The sectional view of the structure arrived A3 plane shown in Figure 19.

As seen from Figure 19, the bit line trenches 209 pass through the drain electrode and sink to groove 204.In an array, the bit line ditch Slot 209 can sink to groove 204 also cross multiple drain electrodes.As seen from Figure 23, in the present embodiment, the bit line trenches 209 Across the part that groove 204 is sunk in the drain electrode, the top surface of the drain region 2032, and the embedded type bit line 210 are exposed Metal top surface be lower than the top surface of the substrate 201, the top surface of the substrate include first source region upper surface with The upper surface of second source region, and the top surface of the substrate is in same active area and first source region and institute Stating the region between the second source region is that insulation is buried.

It should be pointed out that groove 204 and the bit line trenches 209 are sunk in the drain electrode either false relation, It can be aligned relationship, two kinds of relationships require more one of exposure development to form groove, and in the present embodiment, the drain electrode is sunk to Groove 204 and the bit line trenches 209 preferably use false relation.

In the present embodiment, the embedded type bit line 210 selects linear type.In other embodiments, the embedded type bit line Can also be using other linear, such as broken line type or undaform should not excessively limit the protection scope of the utility model herein.

So far, manufacture obtains the transistor arrangement using embedded type bit line.The manufacturing method of the present embodiment can be applied Active area of different shapes, and can apply in different electrical circuits.As an example, Figure 24 is shown as a kind of active area battle array It arranges, groove is sunk in drain electrode, the plane figure of embedded type word line, embedded type bit line.It is flat in A4 that Figure 25 is shown as structure shown in Figure 24 The sectional view in face.Figure 26 is shown as structure shown in Figure 24 in the sectional view of A5 plane.Figure 27 is shown as structure shown in Figure 24 in B2 The sectional view of plane.

The manufacturing method of the present embodiment, which passes through, forms the structure that groove change transistor is sunk in drain electrode, so that transistor has The bit line of flush type, the area that groove increases the node contact of source electrode and drain electrode is sunk in the drain electrode formed in transistor, and is had Conducive to the etching of wordline, channel leakage is reduced.

In conclusion the transistor arrangement using embedded type bit line of the utility model, which sinks to groove by drain electrode, changes crystalline substance The structure of body pipe, so that transistor has the bit line of flush type, the drain electrode formed in transistor sinks to groove and increases source electrode (Source) and the area of the node contact of drain electrode (Drain), and be conducive to the etching of wordline, reduce channel leakage.This is practical The novel transistor arrangement using embedded type bit line can be applied in active area of different shapes, and can be applied different Electrical circuit.So the utility model effectively overcomes various shortcoming in the prior art and has high industrial utilization value.

The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.

Claims (7)

1. a kind of transistor arrangement using embedded type bit line characterized by comprising

Substrate；

Isolation structure is formed in the substrate, and the isolation structure defines multiple active areas in the substrate；

Groove is sunk in drain electrode, is formed in the active area, and the drain electrode is sunk to groove and is folded in the active area middle section, and by The top surface of the substrate, the bottom surface that groove is sunk in the drain electrode are relatively shallower than the bottom surface of the isolation structure；

First wordline groove and the second wordline groove, are all formed in the substrate, by the top surface of the substrate, first word The bottom surface of line trenches and the second wordline groove is all relatively shallower than the bottom surface of the isolation structure and is relatively deeper than described Groove floor is sunk in drain electrode, and the first wordline groove and the second wordline groove all pass through the active area, by described First wordline groove and the second wordline groove interval, the active area include the first source region, drain region and second Source region, the drain region is between first source region and second source region；

Embedded type word line is formed in the first wordline groove and the second wordline groove；

Bit line trenches are formed in the substrate, and the bit line trenches pass through the drain electrode and sink to groove, and the bit line trenches The drain region top surface is exposed across the part that groove is sunk in the drain electrode；And

Embedded type bit line is formed in the bit line trenches, and the metal top surface of the embedded type bit line is lower than the top of the substrate Face, upper surface of the top surface of the substrate comprising the upper surface of first source region and second source region, and institute It is exhausted that the top surface of substrate, which is stated, in the region in same active area and between first source region and second source region Edge is buried.

2. the transistor arrangement according to claim 1 using embedded type bit line, which is characterized in that the transistor arrangement Bit line insulating protective layer is further included, the bit line insulating protective layer is formed in the embedded type bit line top surface.

3. the transistor arrangement according to claim 1 using embedded type bit line, it is characterised in that: the first wordline ditch It is all formed with cushion oxide layer in slot and the second wordline groove, the cushion oxide layer surrounds the bottom of the embedded type word line Face and side wall.

4. the transistor arrangement according to claim 1 using embedded type bit line, it is characterised in that: the embedded type word line Top surface be lower than the embedded type bit line bottom surface.

5. the transistor arrangement according to claim 1 using embedded type bit line, it is characterised in that: the bit line trenches are same When pass through it is multiple it is described drain electrode sink to groove.

6. the transistor arrangement according to claim 1 using embedded type bit line, it is characterised in that: in the transistor junction In the plane figure of structure, the active area, the embedded type word line and the embedded type bit line include linear type, broken line type and Any one in undaform.

7. the transistor arrangement according to claim 1 using embedded type bit line, it is characterised in that: the first wordline ditch Slot is connected or overlaps mutually with the both ends that the second wordline groove sinks to groove with the drain electrode respectively.