CN208271910U - 一种塑封SiC肖特基二极管器件 - Google Patents

一种塑封SiC肖特基二极管器件 Download PDF

Info

Publication number
CN208271910U
CN208271910U CN201820728127.9U CN201820728127U CN208271910U CN 208271910 U CN208271910 U CN 208271910U CN 201820728127 U CN201820728127 U CN 201820728127U CN 208271910 U CN208271910 U CN 208271910U
Authority
CN
China
Prior art keywords
schottky diode
sic schottky
bridge piece
diode chip
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201820728127.9U
Other languages
English (en)
Inventor
钱清友
王成森
徐洋
范敏波
江林华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agile Semiconductor Ltd
Original Assignee
Agile Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agile Semiconductor Ltd filed Critical Agile Semiconductor Ltd
Priority to CN201820728127.9U priority Critical patent/CN208271910U/zh
Application granted granted Critical
Publication of CN208271910U publication Critical patent/CN208271910U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

本实用新型公开了一种塑封SiC肖特基二极管器件，包括金属散热底板、外引脚、SiC肖特基二极管芯片、连接桥片，金属散热底板顶部中心区域设有凸台，外引脚包括外引脚焊接区、外引脚引出端，SiC肖特基二极管芯片包括朝下的阳极区和朝上的的阴极区，连接桥片包括连接桥片焊接A区、连接桥片焊接B区，SiC肖特基二极管芯片朝下的阳极区通过焊锡料焊接在凸台上方，SiC肖特基二极管芯片朝上的的阴极区通过焊锡料与连接桥片焊接A区接连，连接桥片焊接B区与外引脚焊接区通过焊锡料连接，本实用新型极大的提高了芯片散热效果，缩短工艺流程，提高生产效率，极大的提高了器件的通流能力，充分发挥出SiC肖特基二极管芯片高通流能力优势。

Description

一种塑封SiC肖特基二极管器件
技术领域
本实用新型涉及功率半导体器件领域，特别涉及一种塑封SiC肖特基二极管器件。
背景技术
目前市场上的塑封SiC肖特基二极管，都是阴极区焊接在散热底板上，阳极区通过铝线键合工艺与外引脚连接。而SiC肖特基二极管芯片相比于硅肖特基二极管芯片有很多优点，如临界击穿场强很高、热导率很大，SiC肖特基二极管芯片能通过更大的电流，具有更优的导热性能。但由于铝线的熔断电流值低，抗浪涌能力差，同时因塑封器件尺寸的限制，导致铝线键合的数量有限，从而造成塑封SiC肖特基二极管的通流能力受到限制；SiC肖特基二极管为肖特基结构，产品应用时产生的热量主要来肖特基结，而肖特基结与芯片的阳极区电极只有100nm左右，与阴极区电极有近400um，当阴极区焊接在散热底板上，肖特基结远离散热底板，热量传递慢、散热效果差、热阻大。
实用新型内容
本实用新型的目的在于提供一种塑封SiC肖特基二极管器件。
本实用新型采用的技术方案是：
一种塑封SiC肖特基二极管器件，其特征在于：包括金属散热底板、外引脚、SiC肖特基二极管芯片、连接桥片，所述金属散热底板顶部中心区域设有凸台，所述外引脚包括外引脚焊接区、外引脚引出端，所述SiC肖特基二极管芯片包括朝下的阳极区和朝上的阴极区，所述连接桥片包括连接桥片焊接A区、连接桥片焊接B区，所述SiC肖特基二极管芯片朝下的阳极区通过焊锡料焊接在凸台上方，所述SiC肖特基二极管芯片朝上的阴极区通过焊锡料与连接桥片焊接A区接连，所述连接桥片焊接B区与外引脚焊接区通过焊锡料连接。
所述凸台为长方形或正方形。
所述SiC肖特基二极管芯片完全覆盖于凸台上表面，并延伸出凸台四周边沿，与金属散热底板顶面非凸台区形成空隙区。
所述连接桥片焊接A区为长方形或正方形。
本实用新型的优点：在本实用新型中，将SiC肖特基二极管芯片阳极面朝下倒置焊接在金属散热底板的凸台上，芯片阴极区采用连接桥片与外引脚连接，热传导距离减小，热阻小，产品性能提升，极大的提高了芯片散热效果，省去了铝线键合工艺，缩短工艺流程，提高生产效率，极大的提高了器件的通流能力，充分发挥出SiC肖特基二极管芯片高通流能力优势。
附图说明
下面结合附图和具体实施方式对本实用新型作进一步详细叙述。
图1为本实用新型的侧视图；
图2为本实用新型金属散热底板及外引脚的俯视图；
图3为本实用新型连接桥片的俯视图；
图4为本实用新型SiC肖特基二极管芯片的侧视图；
图5为本实用新型SiC肖特基二极管芯片的仰视图；
图6为本实用新型SiC肖特基二极管芯片的俯视图。
其中：1、金属散热底板；2、凸台；3、外引脚；4、SiC肖特基二极管芯片；5、阳极区；6、阴极区；7、连接桥片；8、连接桥片焊接A区；9、连接桥片焊接B区；10、外引脚焊接区；11、外引脚引出端。
具体实施方式
如图1-6所示，一种塑封SiC肖特基二极管器件，包括金属散热底板1、外引脚3、SiC肖特基二极管芯片4、连接桥片7，金属散热底板1顶部中心区域设有凸台2，外引脚3包括外引脚焊接区10、外引脚引出端11，SiC肖特基二极管芯片4包括朝下的阳极区5和朝上的阴极区6，连接桥片7包括连接桥片焊接A区8、连接桥片焊接B区9，SiC肖特基二极管芯片4朝下的阳极区5通过焊锡料焊接在凸台2上方，SiC肖特基二极管芯片4朝上的阴极区6通过焊锡料与连接桥片焊接A区8接连，连接桥片焊接B区9与外引脚焊接区10通过焊锡料连接。
凸台2为长方形或正方形。
SiC肖特基二极管芯片4完全覆盖于凸台2上表面，并延伸出凸台2四周边沿，与金属散热底板1顶面非凸台区形成空隙区。
连接桥片焊接A区8为长方形或正方形。
本实用新型在本实用新型中，将SiC肖特基二极管芯片阳极面朝下倒置焊接在金属散热底板的凸台上，芯片阴极区采用连接桥片与外引脚连接，热传导距离减小，热阻小，产品性能提升，极大的提高了芯片散热效果，省去了铝线键合工艺，缩短工艺流程，提高生产效率，极大的提高了器件的通流能力，充分发挥出SiC肖特基二极管芯片高通流能力优势。

Claims (4)

1.一种塑封SiC肖特基二极管器件，其特征在于：包括金属散热底板、外引脚、SiC肖特基二极管芯片、连接桥片，所述金属散热底板顶部中心区域设有凸台，所述外引脚包括外引脚焊接区、外引脚引出端，所述SiC肖特基二极管芯片包括朝下的阳极区和朝上的阴极区，所述连接桥片包括连接桥片焊接A区、连接桥片焊接B区，所述SiC肖特基二极管芯片朝下的阳极区通过焊锡料焊接在凸台上方，所述SiC肖特基二极管芯片朝上的阴极区通过焊锡料与连接桥片焊接A区接连，所述连接桥片焊接B区与外引脚焊接区通过焊锡料连接。
2.根据权利要求1所述的一种塑封SiC肖特基二极管器件，其特征在于：所述凸台为长方形或正方形。
3.根据权利要求1所述的一种塑封SiC肖特基二极管器件，其特征在于：所述SiC肖特基二极管芯片完全覆盖于凸台上表面，并延伸出凸台四周边沿，与金属散热底板顶面非凸台区形成空隙区。
4.根据权利要求1所述的一种塑封SiC肖特基二极管器件，其特征在于：所述连接桥片焊接A区为长方形或正方形。
CN201820728127.9U 2018-05-16 2018-05-16 一种塑封SiC肖特基二极管器件 Active CN208271910U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201820728127.9U CN208271910U (zh) 2018-05-16 2018-05-16 一种塑封SiC肖特基二极管器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201820728127.9U CN208271910U (zh) 2018-05-16 2018-05-16 一种塑封SiC肖特基二极管器件

Publications (1)

Publication Number Publication Date
CN208271910U true CN208271910U (zh) 2018-12-21

Family

ID=64682923

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201820728127.9U Active CN208271910U (zh) 2018-05-16 2018-05-16 一种塑封SiC肖特基二极管器件

Country Status (1)

Country Link
CN (1) CN208271910U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108538924A (zh) * 2018-05-16 2018-09-14 捷捷半导体有限公司 一种塑封SiC肖特基二极管器件及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108538924A (zh) * 2018-05-16 2018-09-14 捷捷半导体有限公司 一种塑封SiC肖特基二极管器件及其制造方法

Similar Documents

Publication Publication Date Title
CN201568934U (zh) Led灯具的复合散热器结构
CN208271910U (zh) 一种塑封SiC肖特基二极管器件
CN102522379B (zh) 一种大电流晶体管封装结构及其制作方法
JP2013219139A (ja) 半導体装置
CN201773840U (zh) 无邦定线的igbt功率模块
CN104078369B (zh) 一种低成本的大功率电子器件封装工艺
CN111326489A (zh) 功率器件封装结构
US10121763B2 (en) Clip and related methods
CN211350630U (zh) 功率器件封装结构
CN204088301U (zh) 基于铜球预压平的芯片封装装置
CN208422903U (zh) 一种沟槽型绝缘栅双极型晶体管封装结构
CN108538924A (zh) 一种塑封SiC肖特基二极管器件及其制造方法
CN217334062U (zh) 一种便于高效散热反向导通的氮化镓器件
CN213752704U (zh) 一种led封装结构
CN215496708U (zh) 一种基于Clip结构的IGBT器件
CN106057935B (zh) 一种应力改善型的轴向旁路光伏二极管
CN106098651B (zh) 一种功率器件封装结构及封装方法
CN209199917U (zh) 一种具有全方位散热功能的三极管封装结构
CN205429001U (zh) 一种led cob光源封装结构
CN211151047U (zh) 一种便于光斑整形的高功率半导体激光器
CN202167471U (zh) 一种大尺寸硅芯片采用塑料实体封装的可控硅
CN210272327U (zh) 一种新型功率模块
CN208028050U (zh) 一种拼接式均温板散热装置
CN203760508U (zh) 一种全金属结构的led封装支架
CN205944109U (zh) 一种应力改善型的轴向旁路光伏二极管

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CP02 Change in the address of a patent holder
CP02 Change in the address of a patent holder

Address after: 226100 No. 6 Jinggangshan Road, Sutong Science and Technology Industrial Park, Nantong City, Jiangsu Province

Patentee after: Agile Semiconductor Ltd

Address before: 226200 Room 2159, Building 3, Jiangcheng R&D Park, 1088 Jiangcheng Road, Sutong Science and Technology Industrial Park, Nantong City, Jiangsu Province

Patentee before: Agile Semiconductor Ltd