CN207853873U - Drive interlocking circuit and car - Google Patents
Drive interlocking circuit and car Download PDFInfo
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- CN207853873U CN207853873U CN201820277028.3U CN201820277028U CN207853873U CN 207853873 U CN207853873 U CN 207853873U CN 201820277028 U CN201820277028 U CN 201820277028U CN 207853873 U CN207853873 U CN 207853873U
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- 239000004065 semiconductor Substances 0.000 description 2
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- 150000004706 metal oxides Chemical class 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model discloses a drive interlock circuit and car, wherein drive interlock circuit includes: a first inverter circuit, a second inverter circuit, a first logic circuit, and a second logic circuit; the output end of the first inverting circuit is connected to the first input end of the first logic circuit; the output end of the second inverting circuit is connected to the first input end of the second logic circuit; the input signals of the second input end of the first logic circuit and the input end of the second inverter circuit are first driving signals, and the input signals of the second input end of the second logic circuit and the input end of the first inverter circuit are second driving signals; when the first driving signal and the second driving signal are high-level signals, the third driving signal output by the first logic circuit and the fourth driving signal output by the second logic circuit are low-level signals. The utility model discloses can avoid complementary first drive signal and second drive signal to be the high level by disturbing simultaneously, lead to the power device of non-same bridge arm the direct condition to appear.
Description
Technical field
The utility model is related to electrical system technical field more particularly to a kind of driving interlock circuits and automobile.
Background technology
Currently, all there is translation circuit, such as on automobile：DC-DC transfer circuit, ac-dc conversion circuit and
DC-AC conversion circuit etc..General translation circuit uses bridge conversion circuit, and bridge-type transformation electricity is controlled by drive signal
The transformation of input/output electric current is realized in device for power switching alternate conduction in road or shutdown.With totem non-bridge PFC (work(
Rate factor correcting, Power Factor Correction) open up mend structure for, since vehicle-mounted charge acc power is big, pfc circuit
The interference generated when work is very strong, in unloaded/fully loaded switching, or input alternating voltage saltus step when, high frequency may be driven
Dynamic signal generates interference, and complementary high-frequency driving signal is simultaneously high level, and the device for power switching of non-same bridge arm is caused to go out
It now leads directly to, or even device for power switching is caused to damage.
Utility model content
The utility model provides a kind of driving interlock circuit and automobile, to solve in the prior art since high-frequency drive is believed
Number disturbed, complementary high-frequency driving signal is simultaneously high level, and the device for power switching of non-same bridge arm is caused to lead directly to,
Device for power switching is even caused to damage problem.
In order to solve the above-mentioned technical problem, the utility model embodiment provides a kind of driving interlock circuit, including：First
Negative circuit, the second negative circuit, the first logic circuit and the second logic circuit；
Wherein, the output end of first negative circuit is connected to the first input end of first logic circuit；It is described
The output end of second negative circuit is connected to the first input end of second logic circuit；
The input signal of second input terminal of first logic circuit and the input terminal of second negative circuit is the
The input signal of the input terminal of one drive signal, the second input terminal of second logic circuit and first negative circuit is
Second drive signal；
When first drive signal and second drive signal are high level signal, first logic circuit
The third drive signal of output and the fourth drive signal of second logic circuit output are low level signal.
Preferably, first logic circuit includes first and door chip, and the output end of first negative circuit connects
In described first and the first input end of door chip；
Described first and the input signal of the second input terminal of door chip are first drive signal.
Preferably, second logic circuit includes second and door chip, and the output end of second negative circuit connects
In described second and the first input end of door chip；
Described second and the input signal of the second input terminal of door chip are second drive signal.
Preferably, first logic circuit includes：First NAND gate chip and third negative circuit, described first with
The output end of NOT gate chip is connected to the input terminal of the third negative circuit；The output end of first negative circuit is connected to
The first input end of the first NAND gate chip；
The input signal of second input terminal of the first NAND gate chip is first drive signal；
When first drive signal and second drive signal are high level signal, the third negative circuit
The third drive signal of output is low level signal.
Preferably, the third negative circuit is phase inverter, NOT gate chip or NAND gate chip.
Preferably, second logic circuit includes：Second NAND gate chip and the 4th negative circuit, described second with
The output end of NOT gate chip is connected to the input terminal of the 4th negative circuit；The output end of second negative circuit is connected to
The first input end of the second NAND gate chip；
The input signal of second input terminal of the second NAND gate chip is second drive signal；
When first drive signal and second drive signal are high level signal, the 4th negative circuit
The fourth drive signal of output is low level signal.
Preferably, the 4th negative circuit is phase inverter, NOT gate chip or NAND gate chip.
Preferably, first negative circuit is phase inverter, NOT gate chip or NAND gate chip.
Preferably, second negative circuit is phase inverter, NOT gate chip or NAND gate chip.
The utility model embodiment additionally provides a kind of automobile, including drives interlock circuit and bridge-type as described above
Translation circuit；
The bridge conversion circuit includes：The first power device, the second power device, the third power being sequentially connected in series
Device and the 4th power device；Wherein, the first input end of the bridge conversion circuit be connected to first power device with
The connecting pin of second power device；Second input terminal of the bridge conversion circuit be connected to the third power device with
The connecting pin of 4th power device；
First output end of the driving interlock circuit is connected to the driving end of first power device, and the driving is mutual
The second output terminal of lock circuit is connected to the driving end of second power device.
The advantageous effect of the embodiments of the present invention is：
Driving interlock circuit in said program, by the way that the first negative circuit is connected to the first defeated of the first logic circuit
Enter end, the second negative circuit is connected to the first input end of the second logic circuit, and the second input terminal of the first logic circuit and
The input signal of the input terminal of second negative circuit is the first drive signal, and the second input terminal of the second logic circuit and first is instead
The input signal of the input terminal of circuitry phase is the second drive signal.In this way, being in the first drive signal and the second drive signal
When high level signal, the third drive signal of the first logic circuit output and the fourth drive signal of the second logic circuit output are equal
For low level signal, avoid the first complementary drive signal and the second drive signal it is disturbed and when being high level signal simultaneously,
The device for power switching of non-same bridge arm is caused to lead directly to, to ensure that device for power switching is not destroyed.
Description of the drawings
Fig. 1 shows the structure diagrams of the driving interlock circuit of the utility model embodiment；
Fig. 2 indicates one of driving interlock circuit schematic diagram of the utility model embodiment；
Fig. 3 indicates the two of the schematic diagram of the driving interlock circuit of the utility model embodiment；
Fig. 4 indicates the schematic diagram of partial circuit in the automobile charging system actual of the utility model embodiment.
Reference sign：
1, the first negative circuit；
2, the second negative circuit；
3, the first logic circuit；
31, first with door chip；
32, the first NAND gate chip；
33, third negative circuit；
4, the second logic circuit；
41, second with door chip；
42, the second NAND gate chip；
43, the 4th negative circuit；
5, bridge conversion circuit；
51, the first power device；
52, the second power device；
53, third power device；
54, the 4th power device.
Specific implementation mode
The exemplary embodiment of the utility model is more fully described below with reference to accompanying drawings.Although showing this in attached drawing
The exemplary embodiment of utility model, it being understood, however, that may be realized in various forms the utility model without should be by here
The embodiment of elaboration is limited.It is to be able to be best understood from the utility model, and energy on the contrary, providing these embodiments
It is enough that the scope of the utility model is completely communicated to those skilled in the art.
As shown in Figure 1, the embodiments of the present invention provide a kind of driving interlock circuit, including：First negative circuit
1, the second negative circuit 2, the first logic circuit 3 and the second logic circuit 4.
Wherein, the output end of first negative circuit 1 is connected to the first input end of first logic circuit 3；Institute
The output end for stating the second negative circuit 2 is connected to the first input end of second logic circuit 4.
The input signal of second input terminal of first logic circuit 3 and the input terminal of second negative circuit 2 is
The input of the input terminal of first drive signal, the second input terminal of second logic circuit 4 and first negative circuit 1 is believed
Number be the second drive signal.
When first drive signal and second drive signal are high level signal, first logic circuit
The third drive signal of 3 outputs and the fourth drive signal of second logic circuit 4 output are low level signal.
Driving interlock circuit in the embodiment is high level signal in the first drive signal and the second drive signal
When, the third drive signal of the first logic circuit output and the fourth drive signal of the second logic circuit output are low level letter
Number, avoid the first complementary drive signal and the second drive signal it is disturbed and when being high level signal simultaneously, cause non-same
The device for power switching of bridge arm is led directly to, to ensure that device for power switching is not destroyed.
Embodiment one：Such as Fig. 2, the driving interlock circuit of the embodiment, including：First negative circuit 1, the second negative circuit
2, the first logic circuit 3 and the second logic circuit 4.
Wherein, the output end of first negative circuit 1 is connected to the first input end of first logic circuit 3；Institute
The output end for stating the second negative circuit 2 is connected to the first input end of second logic circuit 4.
Specifically, first logic circuit 3 includes first and door chip 31, the output end of first negative circuit 1
It is connected to the first input end of described first and door chip 31.Second logic circuit 4 includes second and door chip 41, described
The output end of second negative circuit 2 is connected to the first input end of described second and door chip 41.
Wherein, described first with the input of the second input terminal of door chip 31 and the input terminal of second negative circuit 2
Signal is the first drive signal, described second with the input terminal of the second input terminal and first negative circuit 1 of door chip 41
Input signal be the second drive signal.
In the embodiment, the logic true value table of the embodiment one according to table 1, can learn in the first drive signal and
When second drive signal is high level signal, first with door chip 31 export third drive signal and second with door chip 41
The fourth drive signal of output is low level signal, disturbed to avoid complementary the first drive signal and the second drive signal
And when being high level signal simultaneously, cause the device for power switching of non-same bridge arm to lead directly to, to ensure power switch device
Part is not destroyed.Simultaneously can also ensure that in the first drive signal and the second drive signal difference be high level signal when, i.e.,
The device for power switching of non-same bridge arm is not in (device for power switching normal work) in the case of leading directly to, third driving letter
Number be consistent with the first drive signal, fourth drive signal is consistent with the second drive signal, i.e., third drive signal and
Fourth drive signal is the drive signal of complementation.
Table 1
Embodiment two：Such as Fig. 3, the driving interlock circuit of the embodiment, including：First negative circuit 1, the second negative circuit
2, the first logic circuit 3 and the second logic circuit 4.
Wherein, the output end of first negative circuit 1 is connected to the first input end of first logic circuit 3；Institute
The output end for stating the second negative circuit 2 is connected to the first input end of second logic circuit 4.
Specifically, first logic circuit 3 includes：First NAND gate chip 32 and third negative circuit 33, it is described
The output end of first NAND gate chip 32 is connected to the input terminal of third negative circuit 33；The output of first negative circuit 1
End is connected to the first input end of the first NAND gate chip 32.
Second logic circuit 4 includes：Second NAND gate chip 42 and the 4th negative circuit 43, described second with it is non-
The output end of door chip 42 is connected to the input terminal of the 4th negative circuit 43；The output end of second negative circuit 2 is connected to
The first input end of the second NAND gate chip 42.
Wherein, the input terminal of the second input terminal and second negative circuit 2 of the first NAND gate chip 32 is defeated
It is the first drive signal to enter signal；Second input terminal of the second NAND gate chip 42 and first negative circuit 1 it is defeated
The input signal for entering end is the second drive signal.
In the embodiment, the logic true value table of the embodiment two according to table 2, can learn in the first drive signal and
When second drive signal is high level signal, third drive signal and the 4th negative circuit 43 that third negative circuit 33 exports
The fourth drive signal of output is low level signal, disturbed to avoid complementary the first drive signal and the second drive signal
And when being high level signal simultaneously, cause the device for power switching of non-same bridge arm to lead directly to, to ensure power switch device
Part is not destroyed.Simultaneously can also ensure that in the first drive signal and the second drive signal difference be high level signal when, i.e.,
The device for power switching of non-same bridge arm is not in (device for power switching normal work) in the case of leading directly to, third driving letter
Number be consistent with the first drive signal, fourth drive signal is consistent with the second drive signal, i.e., third drive signal and
Fourth drive signal is the drive signal of complementation.
Table 2
Specifically, the third negative circuit 33 is phase inverter, NOT gate chip or NAND gate chip.Third reverse phase electricity
Road 33 is used to the drive signal exported from the output end of the first NAND gate chip 32 carrying out reverse phase.4th negative circuit 43
For phase inverter, NOT gate chip or NAND gate chip.4th negative circuit 43 is used for will be from the output of the second NAND gate chip 42
The drive signal of end output carries out reverse phase.
Wherein, when using NAND gate chip as negative circuit, with third negative circuit 33 for third NAND gate chip
For illustrate.The output end of first NAND gate chip 32 is connected to the first input end of third NAND gate chip, and will
Second input point of third NAND gate chip is set as high level.In this way, when the output of the first NAND gate chip 32 is high level,
The output of third NAND gate chip is low level；When the output of the first NAND gate chip 32 is low level, third NAND gate chip is defeated
Go out the purpose realized for high level and the drive signal exported from the output end of the first NAND gate chip 32 is carried out to reverse phase.
In driving interlock circuit as shown in Figures 1 to 3, first negative circuit 1 be phase inverter, NOT gate chip or with
NOT gate chip.Second negative circuit 2 is phase inverter, NOT gate chip or NAND gate chip.
It should be noted that at least one of the first negative circuit 1, the second negative circuit 2 and the 4th negative circuit 43
When using NAND gate chip, connection type as described above is can refer to, which is not described herein again.
In addition, negative circuit (the first negative circuit 1, the second negative circuit 2, third negative circuit 33 and the 4th reverse phase electricity
Road 43) it can also be not limited using other chips in addition to above-mentioned example, such as nor gate chip, the utility model.
As shown in figure 4, the utility model embodiment additionally provides a kind of automobile, including interlocking electricity is driven as described above
Road and bridge conversion circuit 5.
The bridge conversion circuit 5 includes：The first power device 51 for being sequentially connected in series, the second power device 52,
Three power devices 53 and the 4th power device 54；Wherein, the first input end of the bridge conversion circuit 5 is connected to described first
The connecting pin of power device 51 and second power device 52；Second input terminal of the bridge conversion circuit 5 is connected to institute
State the connecting pin of third power device 53 and the 4th power device 54.
First output end of the driving interlock circuit is connected to the driving end of first power device 51, the driving
The second output terminal of interlock circuit is connected to the driving end of second power device 52.
Specifically, illustrating for using totem non-bridge PFC topological structure as bridge conversion circuit 5, the totem is without bridge
PFC topological structures include：4 power devices (the first power device 51, the second power device 52, third power device 53 and
Four power devices 54), 2 PFC inductance (the first inductance L1 and the second inductance L2) and electrolytic capacitor C1.Wherein, the first power
Device 51 and the second power device 52 are operated in HF switch state, and third power device 53 and the 4th power device 54 are operated in
Power frequency on off state.Preferably, silicon carbide MOSFET (Metal-Oxide Semiconductor field effect transistor may be used in power device
Pipe, Metal-Oxide-Semiconductor Field-Effect Transistor), be conducive to reduce switching loss.
In said program, by driving interlock circuit to avoid complementary high-frequency driving signal (the first drive signal and second
Drive signal) it is disturbed and when being high level signal simultaneously, cause the device for power switching of non-same bridge arm to lead directly to, thus
Ensure that device for power switching is not destroyed, and then is conducive to improve the security performance of vehicle.
Term " first ", " second " are used for description purposes only in the description of the present invention, and should not be understood as indicating
Or it implies relative importance or implicitly indicates the quantity of indicated technical characteristic." first ", " second " are defined as a result,
Feature can explicitly or implicitly include one or more this feature.In the description of the present invention, " multiple "
It is meant that at least two, such as two, three etc., unless otherwise specifically defined.
In addition unless specifically defined or limited otherwise, the terms such as term " installation ", " connected ", " connection ", " fixation " are answered
It is interpreted broadly, for example, it may be being fixedly connected, may be a detachable connection, or is integral；Can be mechanical connection,
Can be electrically connected or can communicate with one another；It can be directly connected, can also can be indirectly connected through an intermediary two
The interaction relationship of connection or two elements inside a element.For the ordinary skill in the art, Ke Yigen
Understand the concrete meaning of above-mentioned term in the present invention according to concrete condition.
Above-described is preferred embodiments of the present invention, it should be pointed out that for the ordinary person of the art
For, it can also make several improvements and retouch under the premise of not departing from principle described in the utility model, these are improved and profit
Decorations are also within the protection scope of the present utility model.
Claims (10)
1. a kind of driving interlock circuit, which is characterized in that including：First negative circuit (1), the second negative circuit (2), first are patrolled
Collect circuit (3) and the second logic circuit (4)；
Wherein, the output end of first negative circuit (1) is connected to the first input end of first logic circuit (3)；Institute
The output end for stating the second negative circuit (2) is connected to the first input end of second logic circuit (4)；
The input signal of second input terminal of first logic circuit (3) and the input terminal of second negative circuit (2) is
First drive signal, the second input terminal of second logic circuit (4) and the input terminal of first negative circuit (1) it is defeated
It is the second drive signal to enter signal；
When first drive signal and second drive signal are high level signal, first logic circuit (3)
The third drive signal of output and the fourth drive signal of second logic circuit (4) output are low level signal.
2. driving interlock circuit according to claim 1, which is characterized in that first logic circuit (3) includes first
It is connected to described first the first input with door chip (31) with the output end of door chip (31), first negative circuit (1)
End；
Described first and the input signal of the second input terminal of door chip (31) are first drive signal.
3. driving interlock circuit according to claim 1 or 2, which is characterized in that second logic circuit (4) includes the
Two with door chip (41), the output end of second negative circuit (2) be connected to described second with it is the first of door chip (41) defeated
Enter end；
Described second and the input signal of the second input terminal of door chip (41) are second drive signal.
4. driving interlock circuit according to claim 1, which is characterized in that first logic circuit (3) includes：First
The output end of NAND gate chip (32) and third negative circuit (33), the first NAND gate chip (32) is connected to described
The input terminal of three negative circuits (33)；The output end of first negative circuit (1) is connected to the first NAND gate chip
(32) first input end；
The input signal of second input terminal of the first NAND gate chip (32) is first drive signal；
When first drive signal and second drive signal are high level signal, the third negative circuit (33)
The third drive signal of output is low level signal.
5. driving interlock circuit according to claim 4, which is characterized in that the third negative circuit (33) is reverse phase
Device, NOT gate chip or NAND gate chip.
6. driving interlock circuit according to claim 1 or 4, which is characterized in that second logic circuit (4) includes：
The output end of second NAND gate chip (42) and the 4th negative circuit (43), the second NAND gate chip (42) is connected to institute
State the input terminal of the 4th negative circuit (43)；The output end of second negative circuit (2) is connected to the second NAND gate core
The first input end of piece (42)；
The input signal of second input terminal of the second NAND gate chip (42) is second drive signal；
When first drive signal and second drive signal are high level signal, the 4th negative circuit (43)
The fourth drive signal of output is low level signal.
7. driving interlock circuit according to claim 6, which is characterized in that the 4th negative circuit (43) is reverse phase
Device, NOT gate chip or NAND gate chip.
8. driving interlock circuit according to claim 1, which is characterized in that first negative circuit (1) be phase inverter,
NOT gate chip or NAND gate chip.
9. driving interlock circuit according to claim 1, which is characterized in that second negative circuit (2) be phase inverter,
NOT gate chip or NAND gate chip.
10. a kind of automobile, which is characterized in that including driving interlock circuit as claimed in any one of claims 1-9 wherein；And
Bridge conversion circuit (5), the bridge conversion circuit (5) include：The first power device (51) for being sequentially connected in series,
Two power devices (52), third power device (53) and the 4th power device (54)；
Wherein, the first input end of the bridge conversion circuit (5) is connected to first power device (51) and described second
The connecting pin of power device (52)；Second input terminal of the bridge conversion circuit (5) is connected to the third power device
(53) with the connecting pin of the 4th power device (54)；
First output end of the driving interlock circuit is connected to the driving end of first power device (51), and the driving is mutual
The second output terminal of lock circuit is connected to the driving end of second power device (52).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820277028.3U CN207853873U (en) | 2018-02-27 | 2018-02-27 | Drive interlocking circuit and car |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820277028.3U CN207853873U (en) | 2018-02-27 | 2018-02-27 | Drive interlocking circuit and car |
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| Publication Number | Publication Date |
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| CN207853873U true CN207853873U (en) | 2018-09-11 |
Family
ID=63410069
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820277028.3U Active CN207853873U (en) | 2018-02-27 | 2018-02-27 | Drive interlocking circuit and car |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110165879A (en) * | 2019-05-16 | 2019-08-23 | 山东航天电子技术研究所 | A kind of magnetic torquer control circuit |
| CN110993438A (en) * | 2019-11-13 | 2020-04-10 | 上海空间电源研究所 | Three-relay interlocking circuit |
| CN112165319A (en) * | 2020-10-21 | 2021-01-01 | 杭州士兰微电子股份有限公司 | Upper bridge arm driving circuit, high-voltage integrated circuit and power module |
| CN113839550A (en) * | 2021-09-29 | 2021-12-24 | 陕西省地方电力（集团）有限公司 | Bridge arm interlocking circuit suitable for SiC MOSFET |
-
2018
- 2018-02-27 CN CN201820277028.3U patent/CN207853873U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110165879A (en) * | 2019-05-16 | 2019-08-23 | 山东航天电子技术研究所 | A kind of magnetic torquer control circuit |
| CN110993438A (en) * | 2019-11-13 | 2020-04-10 | 上海空间电源研究所 | Three-relay interlocking circuit |
| CN110993438B (en) * | 2019-11-13 | 2021-10-15 | 上海空间电源研究所 | Three-relay interlocking circuit |
| CN112165319A (en) * | 2020-10-21 | 2021-01-01 | 杭州士兰微电子股份有限公司 | Upper bridge arm driving circuit, high-voltage integrated circuit and power module |
| CN113839550A (en) * | 2021-09-29 | 2021-12-24 | 陕西省地方电力（集团）有限公司 | Bridge arm interlocking circuit suitable for SiC MOSFET |
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