CN201797500U - Bipolar latched Hall switch circuit - Google Patents
Bipolar latched Hall switch circuit Download PDFInfo
- Publication number
- CN201797500U CN201797500U CN2010202606780U CN201020260678U CN201797500U CN 201797500 U CN201797500 U CN 201797500U CN 2010202606780 U CN2010202606780 U CN 2010202606780U CN 201020260678 U CN201020260678 U CN 201020260678U CN 201797500 U CN201797500 U CN 201797500U
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- capacitive load
- switch circuit
- hall switch
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Abstract
The utility model discloses a bipolar latched Hall switch circuit, which comprises a voltage stabilizer, a Hall sensing chip, a differential amplifier, a hysteretic comparator, an output unit and at least one capacitive load. A first end of each capacitive load is connected to a positive input end or a negative input end of the hysteretic comparator, and a positive input end or a negative input end of the differential amplifier, and a second end of each capacitive load is connected to an output end or ground potential of the voltage stabilizer. The primary state of the Hall switch circuit is set on a circuit, so that complexity of the system design is reduced and system performance is increased.
Description
Technical field
The utility model relates generally to a kind of Hall switch circuit, particularly a kind of double-electrode latch-type Hall switch circuit.
Background technology
Hall ic is widely used in the various control system as a kind of sensing circuit.The principle of Hall switch circuit is that its integrated hall sensing sheet induction external magnetic field produces Hall voltage, Hall voltage and reference voltage comparison, output logic signal 0 or 1.
Double-electrode latch-type Hall switch circuit is a kind of of Hall switch circuit, and its conventional composition module comprises pressurizer 101, hall sensing sheet 102, differential amplifier 103, hysteresis comparator 104 and output unit 105 as shown in Figure 1.
The transmission characteristic of double-electrode latch-type Hall switch circuit is as shown in Figure 2: when magnetic field greater than B
OPThe time, be output as 0; When magnetic field less than B
RPThe time, be output as 1.When magnetic field was 0, after circuit powered on, output was not defined.Traditional solution all is the processing method on the system program: generally think that on program the output state after just having powered on is invalid, wait output have several 0,1 states repeatedly after remake out the circuit judgement of operate as normal.Processing method on this system program makes system design show complicated slightly, has influenced the quick reaction capability of system simultaneously.
Suppose the needed initial state that powers on can be set on circuit, the design of system program can be simplified, and systematic function can be improved.
The utility model content
The technical problems to be solved in the utility model is to solve the double-electrode latch-type Hall switch circuit uncertain problem of initial state that powers on from circuit, and initial state can be arranged to 0 or 1 as required, to overcome the conventional deficiency of bringing with the system handles method.
For solving the problems of the technologies described above, the technical solution of the utility model is as follows:
A kind of double-electrode latch-type Hall switch circuit, comprise pressurizer, hall sensing sheet, differential amplifier, hysteresis comparator and output unit, described double-electrode latch-type Hall switch circuit also comprises at least one capacitive load, first end of described at least one capacitive load is connected to the positive input terminal or the negative input end of the positive input terminal of hysteresis comparator or negative input end, differential amplifier, and second end of described at least one capacitive load is connected to the output or the earth potential of pressurizer.
By increasing capacitive load at the circuit internal node, the input of hysteresis comparator has the pulsed voltage of a peak value greater than sluggish width in power up, and this pulsed voltage makes output be locked into 0 or 1 in the process that internal power source voltage rises.After the circuit operate as normal, capacitive load does not influence its DC characteristic.Therefore, the utility model has solved the double-electrode latch-type Hall switch circuit uncertain problem of initial state that powers on simply in the mode of circuit.
Description of drawings
Fig. 1 is conventional double-electrode latch-type Hall integrated switching circuit schematic diagram;
Fig. 2 is the transmission characteristic schematic diagram of double-electrode latch-type Hall switch;
Fig. 3 is the schematic diagram of a preferred embodiment of the present utility model;
Fig. 4 is the schematic diagram of an alternate embodiment of the present utility model;
Fig. 5 is the schematic diagram of another alternate embodiment of the present utility model;
Fig. 6 is the schematic diagram of another alternate embodiment of the present utility model;
Fig. 7 is the schematic diagram of another alternate embodiment of the present utility model.
Embodiment
According to Fig. 3 to 7, provide preferred embodiment of the present utility model and alternate embodiment, and described in detail below, enable to understand better function of the present utility model, characteristics.
With reference to figure 3, according to a preferred embodiment of the present utility model, double-electrode latch-type Hall switch circuit comprises pressurizer 301, hall sensing sheet 302, differential amplifier 303, hysteresis comparator 304, output unit 305 and capacitive load 306.Pressurizer 301 is connected between Vcc and the earth potential.Hall sensing sheet 302 is connected between the output and earth potential of pressurizer 301.The positive input terminal of differential amplifier 303 and negative input end are connected to two outputs of hall sensing sheet 302 respectively.The positive input terminal of hysteresis comparator 304 and negative input end are connected to two outputs of differential amplifier 303 respectively.The input of output unit 305 is connected to the output of hysteresis comparator 304.First end of capacitive load 306 is connected to the positive input terminal of hysteresis comparator 304, and its second end is connected to the output of pressurizer 301.
Internal power source voltage V
REGIn uphill process, by the capacitance coupling effect of capacitive load 306, make the hysteresis comparator input terminal voltage that individual pulse process be arranged, as long as, exporting initial state greater than sluggish width, its peak value just is determined.For the peak value that guarantees the pulse of hysteresis comparator input terminal voltage greater than sluggish width, the impedance of capacitive load can not be too big.
Fig. 4 is that the utility model requirement output initial state is 0 o'clock a alternate embodiment, and the difference with Fig. 3 on the circuit is to have increased by 3 capacitive loads 307,308 and 309 at amplifier 303 input/output terminals.First end of capacitive load 306,308 is connected to the positive input terminal of hysteresis comparator 304 and the positive input terminal of differential amplifier 303 respectively, and its second end is connected to the output of pressurizer 301; First end of capacitive load 307,309 is connected to the negative input end of hysteresis comparator 304 and the negative input end of differential amplifier 303 respectively, and its second end is connected to earth potential.
Fig. 5 is that the utility model requirement output initial state is another alternate embodiment of 0 o'clock.When requiring to export initial state and be 1, connected mode can be shown in Fig. 6 and 7.
It should be noted that:
1. the capacitive load 306,307,308 and 309 first end can be connected to any one in four inputs of hysteresis comparator 304 and differential amplifier 303, and second end then can be connected to the output of pressurizer 301 and any one in the earth potential;
2. two kinds of connected modes (Fig. 3,4 and 6 is depicted as a kind of, and Fig. 5 and 7 is depicted as another kind) are arranged between differential amplifier 303, the hysteresis comparator 304;
3. in the circuit that connects according to above-mentioned 1-2 point, any one in the capacitive load 306,307,308 and 309, two or three can not exist.
Therefore, the utlity model has multiple connected mode.As long as there is a capacitive load to be connected to the positive input terminal or the negative input end of hysteresis comparator 304 or differential amplifier 303, second end is connected to the output or the earth potential of pressurizer 301, its structure can both realize that the pulse voltage of a peak value greater than sluggish width appears in the hysteresis comparator input terminal voltage in power up, makes the output state locking.And this output state is 0 or 1, then decides on concrete connection.
The specific implementation of each in the capacitive load 306,307,308 and 309 can be electric capacity, also can have the element or the composition element of capacitive for anti-PN junction partially or other, can be identical, and also can be different.But in semiconductor technology, the manufacturing of capacitor layers need add template in addition, so the most economical with anti-PN junction partially.Equally for economy, capacitive load 306,307,308 is preferably identical with 309 specific implementation.
The utility model increases the method for capacitive load at the circuit internal node, minimum needs to increase an anti-PN junction partially, realized setting the purpose of ambipolar Hall switch circuit initial state from circuit, need not to solve the problem of initial state from system, simplify the complexity of system design, improved systematic function.
Obviously, in the above teachings, may carry out multiple correction and modification, and within the scope of the appended claims, the utility model can be embodied as the specifically described mode that is different to the utility model.
Claims (5)
1. double-electrode latch-type Hall switch circuit, comprise pressurizer, hall sensing sheet, differential amplifier, hysteresis comparator and output unit, it is characterized in that, described double-electrode latch-type Hall switch circuit also comprises at least one capacitive load, first end of described at least one capacitive load is connected to the positive input terminal or the negative input end of the positive input terminal of hysteresis comparator or negative input end, differential amplifier, and second end of described at least one capacitive load is connected to the output or the earth potential of pressurizer.
2. a kind of double-electrode latch-type Hall switch circuit as claimed in claim 1 is characterized in that, described capacitive load is an electric capacity.
3. a kind of double-electrode latch-type Hall switch circuit as claimed in claim 1 is characterized in that, the part in the described capacitive load is an electric capacity.
4. a kind of double-electrode latch-type Hall switch circuit as claimed in claim 1 is characterized in that, described capacitive load is anti-PN junction partially.
5. a kind of double-electrode latch-type Hall switch circuit as claimed in claim 1 is characterized in that, the part in the described capacitive load is anti-PN junction partially.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202606780U CN201797500U (en) | 2010-07-16 | 2010-07-16 | Bipolar latched Hall switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202606780U CN201797500U (en) | 2010-07-16 | 2010-07-16 | Bipolar latched Hall switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201797500U true CN201797500U (en) | 2011-04-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010202606780U Expired - Lifetime CN201797500U (en) | 2010-07-16 | 2010-07-16 | Bipolar latched Hall switch circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN201797500U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888233A (en) * | 2010-07-16 | 2010-11-17 | 灿瑞半导体(上海)有限公司 | Double-electrode latch-type Hall switch circuit |
| CN103063232A (en) * | 2011-10-21 | 2013-04-24 | 上海腾怡半导体有限公司 | One-chip latch type Hall sensor |
| CN103166620A (en) * | 2011-12-09 | 2013-06-19 | 上海华虹Nec电子有限公司 | Full-pole magnetic field detection switch circuit |
-
2010
- 2010-07-16 CN CN2010202606780U patent/CN201797500U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101888233A (en) * | 2010-07-16 | 2010-11-17 | 灿瑞半导体(上海)有限公司 | Double-electrode latch-type Hall switch circuit |
| CN103063232A (en) * | 2011-10-21 | 2013-04-24 | 上海腾怡半导体有限公司 | One-chip latch type Hall sensor |
| CN103166620A (en) * | 2011-12-09 | 2013-06-19 | 上海华虹Nec电子有限公司 | Full-pole magnetic field detection switch circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CB03 | Change of inventor or designer information |
Inventor after: Zhang Liang Inventor after: Wu Yujiang Inventor before: Luo Liquan Inventor before: Zhang Liang Inventor before: Wu Yujiang |
|
| COR | Change of bibliographic data | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 200081 Shanghai, North Sichuan Road, room 1717, No. 1006, room Patentee after: SHANGHAI CANRUI TECHNOLOGY CO., LTD. Address before: 200081 Shanghai, North Sichuan Road, room 1717, No. 1006, room Patentee before: Orient-Chip Semiconductor (Shanghai) Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110413 |