CN102263399A - Abnormal protection circuit for intelligent power module - Google Patents
Abnormal protection circuit for intelligent power module Download PDFInfo
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Abstract
The invention discloses an abnormal protection circuit for an intelligent power module. The abnormal protection circuit comprises a P-channel metal oxide semiconductor (PMOS) transistor 301, an N-channel metal oxide semiconductor (NMOS) transistor 302, a lower bridge arm power supply 303, an insulated gate bipolar transistor (IGBT) 304, a PMOS transistor 305, an NMOS transistor 306, an upper bridge arm power supply 307 and an IGBT 308. A lower bridge arm driving signal LIN is connected with the gate of the PMOS transistor 301, the gate of the NMOS transistor 302 and the input end of the abnormal protection circuit 309. The drain of the PMOS transistor 301 is connected with the drain of the NMOS transistor 302, and is also connected with the gate of the IGBT 304 and the first and second output ends of the abnormal protection circuit 309, and the point of the later connection is marked as LO. The abnormal protection circuit can timely discover the abnormality an IGBT gate connecting line and timely switch the IGBT off, and has the characteristics of simple and rational structure, operational flexibility, high degree of safety and wide application range.
Description
Technical field
The present invention relates to a kind of abnormal protection technology of integrated circuit and the Driving technique of IGBT, particularly a kind of abnormity protection circuit that is used for Intelligent Power Module.
Background technology
Intelligent Power Module, promptly IPM (Intelligent Power Module) is a kind of power drive series products with power electronics and integrated circuit technique combination.Intelligent Power Module integrates device for power switching and high-voltage driving circuit, and in keep overvoltage, overcurrent and failure detector circuit such as overheated.Intelligent Power Module receives the control signal of MCU on the one hand, drives subsequent conditioning circuit work, sends the state detection signal of system back to MCU on the other hand.Compare with the discrete scheme of tradition, Intelligent Power Module wins increasing market with advantages such as its high integration, high reliability, be particularly suitable for the frequency converter and the various inverter of drive motors, it is frequency control, metallurgical machinery, electric traction, servo-drive, a kind of desirable power electronic device of frequency-conversion domestic electric appliances.
Intelligent Power Module belongs to high power device, and the IGBT of upper and lower bridge arm is driven strict sequential requirement, if upper and lower bridge arm conducting simultaneously will make Intelligent Power Module burn and burns subsequent conditioning circuit then and machinery equipment is thoroughly damaged.
The IGBT drive circuit that is applied to the traditional intelligence power model at present is as shown in Figure 1: following brachium pontis drive signal LIN links to each other with the grid of PMOS pipe 101, NMOS pipe 102, the substrate of PMOS pipe 101 links to each other with emitter-base bandgap grading and is connected the anode VCC of brachium pontis power supply 103 down, and the substrate of NMOS pipe 102 links to each other with emitter-base bandgap grading and is connected the negative terminal GND of brachium pontis power supply 103 down; The drain electrode of PMOS pipe 101 and NMOS pipe 102 links to each other and is connected IGBT and manages 104 grid, and this point is designated as LO; The emitter-base bandgap grading of IGBT pipe 104 meets GND, and the collector electrode of IGBT pipe 104 connects the negative terminal VS of brachium pontis power supply 107; Last brachium pontis drive signal HIN links to each other with the grid of PMOS pipe 105, NMOS pipe 106, the substrate of PMOS pipe 105 links to each other with emitter-base bandgap grading and is connected the anode VB of brachium pontis power supply 107, and it is continuous with emitter-base bandgap grading and be connected the negative terminal VS of brachium pontis power supply 107 that NMOS manages 106 substrate; The drain electrode of PMOS pipe 105 and NMOS pipe 106 links to each other and is connected IGBT and manages 108 grid, and this point is designated as HO; The emitter-base bandgap grading of IGBT pipe 108 meets VS, and the collector electrode of IGBT pipe 108 meets high direct voltage P.
Described brachium pontis drive signal LIN down and last brachium pontis drive signal HIN are anti-phase relations, and the waveform of above-mentioned each key point as shown in Figure 2.Because high level alternately appears in LO and HO, IGBT pipe 104 and IGBT manage 108 alternate conduction, and the waveform of VS is alternate between P and GND.
What HO and LO one connect is drive IC, i.e. the curved portion of Fig. 1, and what the other end connect is the grid of IGBT, unavoidably need use line with the junction of IC: fine aluminum wire or thin gold thread.Reason owing to manufacture craft, the line of this junction has the probability of general 500ppm can occur getting loose in the process of solid envelope and high/low-temperature impact, thereby make the grid of IGBT unsettled, connect at collector electrode under the situation of high pressure, the unsettled IGBT of grid can conducting, if another IGBT enters conducting state because of the effect of input signal, will cause the IGBT conducting simultaneously of upper and lower bridge arm, thereby form great electric current, the heat localization meeting causes the IPM blast, causes the circuitry plate to burn out then.
Summary of the invention
Purpose of the present invention aims to provide a kind of simple and reasonable, flexible operation, safe coefficient height, the abnormity protection circuit that is used for Intelligent Power Module applied widely, to overcome weak point of the prior art.
A kind of abnormity protection circuit that is used for Intelligent Power Module by this purpose design, comprise PMOS pipe 301, NMOS pipe 302, following brachium pontis power supply 303, IGBT pipe 304, PMOS pipe 305, NMOS pipe 306, last brachium pontis power supply 307 and IGBT pipe 308, the grid of brachium pontis drive signal LIN and PMOS pipe 301 under it is characterized in that, the grid of NMOS pipe 302, the input of abnormity protection circuit 309 links to each other, the substrate of PMOS pipe 301 links to each other with emitter-base bandgap grading and is connected the anode VCC of brachium pontis power supply 303 down, and the substrate of NMOS pipe 302 links to each other with emitter-base bandgap grading and is connected the negative terminal GND of brachium pontis power supply 303 down; The drain electrode of the drain electrode of PMOS pipe 301 and NMOS pipe 302 links to each other and is connected the grid of IGBT pipe 304, first output and second output of abnormity protection circuit 309, and this point is designated as LO; Abnormity protection circuit 309 is by brachium pontis power supply 303 power supplies down; The emitter-base bandgap grading of IGBT pipe 304 meets GND, and the collector electrode of IGBT pipe 304 connects the negative terminal VS of brachium pontis power supply 307; Last brachium pontis drive signal HIN links to each other with the grid of PMOS pipe 305, the grid of NMOS pipe 306, the input of abnormity protection circuit 310, the substrate of PMOS pipe 305 links to each other with emitter-base bandgap grading and is connected the anode VB of brachium pontis power supply 307, and it is continuous with emitter-base bandgap grading and be connected the negative terminal VS of brachium pontis power supply 307 that NMOS manages 306 substrate; The drain electrode of the drain electrode of PMOS pipe 305 and NMOS pipe 306 links to each other and is connected the grid of IGBT pipe 308, first output and second output of abnormity protection circuit 310, and this point is designated as HO; The emitter-base bandgap grading of IGBT pipe 308 meets VS, and the collector electrode of IGBT pipe 308 meets high direct voltage P.
The input that described brachium pontis drive signal LIN down enters abnormity protection circuit 309 back NAND gate 311 links to each other, the output of not gate 311 connects the input of not gate 312 and the input of not gate 313 respectively, one end of the output of not gate 312 and electric capacity 324, the input of not gate 314 links to each other, another termination GND of electric capacity 324, the output of the output of not gate 313 and not gate 314 connects two inputs of NAND gate 315 respectively, the input of the output termination not gate 316 of NAND gate 315, the grid of the output termination NMOS pipe 317 of not gate 316 and the CP end of synchronous rs flip-flop 322, the substrate of NMOS pipe 317 links to each other with source electrode and is connected GND, the drain electrode of NMOS pipe 317 connects the drain and gate of PMOS pipe 318 and the grid of PMOS pipe 319, the substrate of PMOS pipe 318 links to each other with emitter-base bandgap grading and is connected VCC, the substrate of PMOS pipe 319 links to each other with emitter-base bandgap grading and is connected VCC, the drain electrode of PMOS pipe 319 connects an end of difference connecting resistance 320 and the positive input terminal of voltage comparator 321, another termination LO of resistance 320 and the negative input end of voltage comparator 321; The S end of the output termination synchronous rs flip-flop 322 of voltage comparator 321, the R termination GND of synchronous rs flip-flop 322, the grid of the output termination NMOS pipe 323 of synchronous rs flip-flop 322, the substrate of NMOS pipe 323 link to each other with source electrode and receive GND, and the drain electrode of NMOS pipe 323 meets LO.
The abnormity protection circuit 309 among the present invention and the effect of abnormity protection circuit 310 are in full accord, and these two abnormity protection circuits place the gate driving position of brachium pontis and following brachium pontis respectively.
At the rising edge of the input of abnormity protection circuit, first output of abnormity protection circuit produces a little electric current and pours into IC, if can form path, prove with the wiring of IC well, and second output of abnormity protection circuit is exported high resistant; If can not form path, prove that the wiring with IC disconnects, second output output electronegative potential of abnormity protection circuit makes IGBT force to end.At other states except that the input signal rising edge, first output and second output of abnormity protection circuit all show as high-impedance state.
After the present invention adopts above-mentioned technical scheme; the IPM module can in time be found the break-make with the line of IC; at the IC line when unusually disconnecting; the IGBT of correspondence is forced to end; avoided the IGBT conducting simultaneously of upper and lower bridge arm; stopped to flow through the blast that causes, effectively protected the circuitry plate because of there is big electric current IPM inside.
When the IGBT gate trace got loose, the present invention can in time find the unusual of IGBT gate trace, and IGBT is in time turn-offed, and had simple and reasonable, flexible operation, safe coefficient height, advantage of wide range of application.
Description of drawings
Fig. 1 is the IGBT drive circuit of traditional intelligence power model.
Fig. 2 is the key point waveform of the IGBT drive circuit of traditional intelligence power model.
Fig. 3 is the IGBT drive circuit of the Intelligent Power Module of band abnormity protection function of the present invention.
Fig. 4 is the specific embodiment of abnormity protection circuit of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described.
Referring to Fig. 3-Fig. 4, originally the abnormity protection circuit that is used for Intelligent Power Module, comprise PMOS pipe 301, NMOS pipe 302, following brachium pontis power supply 303, IGBT pipe 304, PMOS pipe 305, NMOS pipe 306, last brachium pontis power supply 307 and IGBT pipe 308, the grid of brachium pontis drive signal LIN and PMOS pipe 301 under it is characterized in that, the grid of NMOS pipe 302, the input of abnormity protection circuit 309 links to each other, the substrate of PMOS pipe 301 links to each other with emitter-base bandgap grading and is connected the anode VCC of brachium pontis power supply 303 down, and the substrate of NMOS pipe 302 links to each other with emitter-base bandgap grading and is connected the negative terminal GND of brachium pontis power supply 303 down; The drain electrode of the drain electrode of PMOS pipe 301 and NMOS pipe 302 links to each other and is connected the grid of IGBT pipe 304, first output and second output of abnormity protection circuit 309, and this point is designated as LO; Abnormity protection circuit 309 is by brachium pontis power supply 303 power supplies down; The emitter-base bandgap grading of IGBT pipe 304 meets GND, and the collector electrode of IGBT pipe 304 connects the negative terminal VS of brachium pontis power supply 307; Last brachium pontis drive signal HIN links to each other with the grid of PMOS pipe 305, the grid of NMOS pipe 306, the input of abnormity protection circuit 310, the substrate of PMOS pipe 305 links to each other with emitter-base bandgap grading and is connected the anode VB of brachium pontis power supply 307, and it is continuous with emitter-base bandgap grading and be connected the negative terminal VS of brachium pontis power supply 307 that NMOS manages 306 substrate; The drain electrode of the drain electrode of PMOS pipe 305 and NMOS pipe 306 links to each other and is connected the grid of IGBT pipe 308, first output and second output of abnormity protection circuit 310, and this point is designated as HO; The emitter-base bandgap grading of IGBT pipe 308 meets VS, and the collector electrode of IGBT pipe 308 meets high direct voltage P.
The input that described brachium pontis drive signal LIN down enters abnormity protection circuit 309 back NAND gate 311 links to each other, the output of not gate 311 connects the input of not gate 312 and the input of not gate 313 respectively, one end of the output of not gate 312 and electric capacity 324, the input of not gate 314 links to each other, another termination GND of electric capacity 324, the output of the output of not gate 313 and not gate 314 connects two inputs of NAND gate 315 respectively, the input of the output termination not gate 316 of NAND gate 315, the grid of the output termination NMOS pipe 317 of not gate 316 and the CP end of synchronous rs flip-flop 322, the substrate of NMOS pipe 317 links to each other with source electrode and is connected GND, the drain electrode of NMOS pipe 317 connects the drain and gate of PMOS pipe 318 and the grid of PMOS pipe 319, the substrate of PMOS pipe 318 links to each other with emitter-base bandgap grading and is connected VCC, the substrate of PMOS pipe 319 links to each other with emitter-base bandgap grading and is connected VCC, the drain electrode of PMOS pipe 319 connects an end of difference connecting resistance 320 and the positive input terminal of voltage comparator 321, another termination LO of resistance 320 and the negative input end of voltage comparator 321; The S end of the output termination synchronous rs flip-flop 322 of voltage comparator 321, the R termination GND of synchronous rs flip-flop 322, the grid of the output termination NMOS pipe 323 of synchronous rs flip-flop 322, the substrate of NMOS pipe 323 link to each other with source electrode and receive GND, and the drain electrode of NMOS pipe 323 meets LO.
Because abnormity protection circuit 309 and abnormity protection circuit 310 are in full accord, so the internal structure of only having drawn abnormity protection circuit 309 among the figure is seen Fig. 4.
The initial set of the output of synchronous rs flip-flop 322 is in low level.
Instantly the high level of brachium pontis drive signal LIN comes interim, the output of described not gate 311 becomes low level rapidly from high level, the output of not gate 313 becomes high level rapidly from low level, and because the existence of electric capacity 324, the suitable breadth length ratio of metal-oxide-semiconductor design for not gate 312, the potential change of the output of not gate 312 is processes of the fast discharge of a charging battery, therefore the output of not gate 312 slowly becomes high level from low level, if this transformation period is T, then the output of not gate 314 is low levels that postpone T than the high level of not gate 313, the low level pulse that width of the output of NAND gate 315 is T, all the other times are high level, what not gate 316 was exported is a high level pulse that width is T, and all the other times are low level; Under the effect of high level pulse, synchronous rs flip-flop 322 is in the triggering state at T in the time, and NMOS managed for 317 conducting T times, and the path at PMOS pipe 318 and NMOS pipe 317 will have electric current to flow through, and at this moment two kinds of situations are arranged:
(1) if the curved portion of LO does not disconnect, manage 319 sides at PMOS identical image current is arranged, make the both sides of resistance 320 produce pressure drop, voltage comparator 321 is output as low level, the output of synchronous rs flip-flop 322 keeps original low level constant, and NMOS pipe 323 ends, but because NMOS pipe 302 conductings at this moment and LO curve place do not disconnect, the grid of IGBT pipe 304 is managed 302 ground connection by NMOS, and the IGBT pipe ends;
(2) if the curved portion of LO disconnects, managing 319 sides at PMOS does not have electric current to flow through, the both sides of resistance 320 do not have pressure drop, voltage comparator 321 is output as high level, and the output of synchronous rs flip-flop 322 is set and is high level, and NMOS manages 323 conductings, therefore, though the LO curve is in disconnection, IGBT pipe 304 still can be managed 323 ground connection by NMOS, and IGBT is forced to end.
When brachium pontis drive signal LIN is in other states except that rising edge instantly, the output of NAND gate 315 remains on high level, not gate 316 outputs remain on low level, synchronous rs flip-flop 322 is in non-triggering state, the output of synchronous rs flip-flop 322 keeps low level constant, NMOS pipe 323 ends, and at this moment two kinds of situations are arranged:
(1) if the curved portion of LO does not disconnect, the conducting of IGBT pipe 304 will be controlled by brachium pontis drive signal LIN whether will, because it is anti-phase that following brachium pontis drive signal LIN and last brachium pontis drive signal HIN have been guaranteed, the conducting simultaneously scarcely of the IGBT of upper and lower bridge arm pipe;
(2) if the curved portion of LO disconnects, come temporarily at the following next rising edge of brachium pontis drive signal LIN, IGBT pipe 304 will be forced to end, and avoids constantly having big electric current to flow through causing heat localization and the IPM module is blasted.
Claims (2)
1. abnormity protection circuit that is used for Intelligent Power Module; comprise that PMOS manages (301), NMOS pipe (302), brachium pontis power supply (303), IGBT pipe (304), PMOS pipe (305), NMOS manage (306), go up brachium pontis power supply (307) and IGBT pipe (308) down; it is characterized in that brachium pontis drive signal LIN links to each other with the grid of PMOS pipe (301), the grid of NMOS pipe (302), the input of abnormity protection circuit (309) down
The substrate of PMOS pipe (301) links to each other with emitter-base bandgap grading and is connected the anode VCC of time brachium pontis power supply (303),
The substrate of NMOS pipe (302) links to each other with emitter-base bandgap grading and is connected the negative terminal GND of brachium pontis power supply (303) down;
The drain electrode of the drain electrode of PMOS pipe (301) and NMOS pipe (302) links to each other and is connected the grid of IGBT pipe (304), first output and second output of abnormity protection circuit (309), and this point is designated as LO;
Abnormity protection circuit (309) is by brachium pontis power supply (303) power supply down;
The emitter-base bandgap grading of IGBT pipe (304) meets GND,
The collector electrode of IGBT pipe (304) connects the negative terminal VS of brachium pontis power supply (307);
Last brachium pontis drive signal HIN links to each other with the grid of PMOS pipe (305), the grid of NMOS pipe (306), the input of abnormity protection circuit (310),
The substrate of PMOS pipe (305) links to each other with emitter-base bandgap grading and is connected the anode VB of brachium pontis power supply (307),
The substrate of NMOS pipe (306) links to each other with emitter-base bandgap grading and is connected the negative terminal VS of brachium pontis power supply (307);
The drain electrode of the drain electrode of PMOS pipe (305) and NMOS pipe (306) links to each other and is connected the grid of IGBT pipe (308), first output and second output of abnormity protection circuit (310), and this point is designated as HO;
The emitter-base bandgap grading of IGBT pipe (308) meets VS, and the collector electrode of IGBT pipe (308) meets high direct voltage P.
2. the abnormity protection circuit that is used for Intelligent Power Module according to claim 1 is characterized in that the input that described brachium pontis drive signal LIN down enters abnormity protection circuit (309) back NAND gate (311) links to each other,
The output of not gate (311) connects the input of not gate (312) and the input of not gate (313) respectively,
The output of not gate (312) links to each other with an end of electric capacity (324), the input of not gate (314),
Another termination GND of electric capacity (324),
The output of the output of not gate (313) and not gate (314) connects two inputs of NAND gate (315) respectively,
The input of the output termination not gate (316) of NAND gate (315),
The CP end of the grid of the output termination NMOS pipe (317) of not gate (316) and synchronous rs flip-flop (322),
The substrate of NMOS pipe (317) links to each other with source electrode and is connected GND,
The drain electrode of NMOS pipe (317) connects the drain and gate of PMOS pipe (318) and the grid of PMOS pipe (319),
The substrate of PMOS pipe (318) links to each other with emitter-base bandgap grading and is connected VCC,
The substrate of PMOS pipe (319) links to each other with emitter-base bandgap grading and is connected VCC,
The drain electrode of PMOS pipe (319) connects an end of difference connecting resistance (320) and the positive input terminal of voltage comparator (321),
The negative input end of another termination LO of resistance (320) and voltage comparator (321);
The S end of the output termination synchronous rs flip-flop (322) of voltage comparator (321),
The R termination GND of synchronous rs flip-flop (322),
The grid of the output termination NMOS pipe (323) of synchronous rs flip-flop (322),
The substrate of NMOS pipe (323) links to each other with source electrode and receives GND,
The drain electrode of NMOS pipe (323) meets LO.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110177607 CN102263399B (en) | 2011-06-28 | 2011-06-28 | Abnormal protection circuit for intelligent power module |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201110177607 CN102263399B (en) | 2011-06-28 | 2011-06-28 | Abnormal protection circuit for intelligent power module |
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| CN102263399B CN102263399B (en) | 2013-07-31 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104113190A (en) * | 2013-05-20 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module |
| CN104113197A (en) * | 2013-04-19 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module |
| WO2015074471A1 (en) * | 2013-11-25 | 2015-05-28 | 广东美的制冷设备有限公司 | Electrostatic protection device, intelligent power module and frequency-conversion home appliance |
| CN104767181A (en) * | 2014-01-02 | 2015-07-08 | 广东美的制冷设备有限公司 | Electrostatic protection device, intelligent power module, and frequency conversion home appliance |
| CN105099418A (en) * | 2015-06-23 | 2015-11-25 | 珠海格力电器股份有限公司 | Insulated gate bipolar transistor drive circuit |
| CN106711957A (en) * | 2015-07-27 | 2017-05-24 | 长城汽车股份有限公司 | Lithium battery monomer protection circuit, vehicle-mounted power supply and automobile |
| CN109687697A (en) * | 2018-12-12 | 2019-04-26 | 珠海格力电器股份有限公司 | A kind of guard method of IPM, device, storage medium and IPM module |
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| CN102035181A (en) * | 2010-11-16 | 2011-04-27 | 中国电子科技集团公司第五十八研究所 | Overcurrent and overvoltage protection circuit in switch power supply |
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| US20030169025A1 (en) * | 2002-01-25 | 2003-09-11 | Zetex Plc | Current limiting protection circuit |
| CN1688096A (en) * | 2005-05-19 | 2005-10-26 | 上海交通大学 | Zero voltage, zero current switch type inverter based on transformer auxiliary current converting |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104113197A (en) * | 2013-04-19 | 2014-10-22 | 广东美的制冷设备有限公司 | Intelligent power module |
| CN104113197B (en) * | 2013-04-19 | 2016-09-07 | 广东美的制冷设备有限公司 | A kind of SPM |
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| CN104113190B (en) * | 2013-05-20 | 2017-03-08 | 广东美的制冷设备有限公司 | A kind of SPM |
| WO2015074471A1 (en) * | 2013-11-25 | 2015-05-28 | 广东美的制冷设备有限公司 | Electrostatic protection device, intelligent power module and frequency-conversion home appliance |
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| CN104767181B (en) * | 2014-01-02 | 2018-03-27 | 广东美的制冷设备有限公司 | Electrostatic protection device, SPM and frequency-conversion domestic electric appliances |
| CN105099418A (en) * | 2015-06-23 | 2015-11-25 | 珠海格力电器股份有限公司 | Insulated gate bipolar transistor drive circuit |
| CN105099418B (en) * | 2015-06-23 | 2018-01-23 | 珠海格力电器股份有限公司 | Bipolar transistor driving circuit of insulated gate |
| CN106711957A (en) * | 2015-07-27 | 2017-05-24 | 长城汽车股份有限公司 | Lithium battery monomer protection circuit, vehicle-mounted power supply and automobile |
| CN106711957B (en) * | 2015-07-27 | 2019-02-19 | 长城汽车股份有限公司 | A kind of protection circuit, vehicle power supply and the automobile of lithium battery monomer |
| CN109687697A (en) * | 2018-12-12 | 2019-04-26 | 珠海格力电器股份有限公司 | A kind of guard method of IPM, device, storage medium and IPM module |
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|---|---|
| CN102263399B (en) | 2013-07-31 |
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