CN203368316U - PWM dead-time protective circuit and air conditioner - Google Patents
PWM dead-time protective circuit and air conditioner Download PDFInfo
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- CN203368316U CN203368316U CN201320461384.8U CN201320461384U CN203368316U CN 203368316 U CN203368316 U CN 203368316U CN 201320461384 U CN201320461384 U CN 201320461384U CN 203368316 U CN203368316 U CN 203368316U
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Abstract
The utility model discloses a PWM dead-time protective circuit and an air conditioner, wherein the PWM dead-time protective circuit is connected with a motor of the air conditioner. The PWM dead-time protective circuit comprises a microprocessor, a logical processing module and an IPM driver module. An input end of the logical processing module is connected with a control signal output end of the microprocessor. An output end of the logical processing module is connected with an input end of the IPM driver module, an output end of which is connected with the motor. According to the PWM dead-time protective circuit, a low-level drive signal is outputted when a PWM control signal received through the logical processing module is abnormal. Thus, it is ensured that IGBT of upper and lower bridge arms of the IPM module will not connected simultaneously, short-circuited and burned out; the IPM module can be protected timely and effectively; and the IPM module is prevented from being damaged due to direct connection of IGBT of the upper bridge arms of the IPM module. Furthermore, operational reliability of a product with the application of the IPM module is raised, service life is prolonged, and maintenance rate is reduced.
Description
Technical field
The utility model relates to electric and electronic technical field, relates in particular to a kind of PWM Dead Time protective circuit and air conditioner.
Background technology
IPM(Intelligent Power Module, Intelligent Power Module, hereinafter referred to as the IPM module), not only device for power switching and drive circuit are integrated, but also in be provided with overvoltage, overcurrent and the failure detector circuit such as overheated, and detection signal can be delivered to processor CPU.The IPM module consists of the tube core of high-speed low-power-consumption and gate drive circuit and the fast protection circuit of optimization.Even therefore load accident situation or improper use occur, also can guarantee that the IPM module self is not damaged.The IPM module is generally used IGBT(Insulated Gate Bipolar Transistor, insulated gate polar form power tube) as device for power switching, inside establish the integrated morphology of current sensor and drive circuit.The IPM module is with its high reliability, easy to usely win increasing market, being particularly suitable for frequency converter and the various inverter of drive motors, is a kind of ideal power electronic device of frequency control, metallurgical machinery, electric traction, servo-drive, frequency-conversion domestic electric appliances.
But because all there is certain junction capacitance in IGBT constant power switching device, so can cause the delay phenomenon of device for power switching conducting and shutoff.Therefore, if PWM(Pulse Width is Modulation, pulse width modulation) Dead Time does not set, and will cause a brachium pontis of IPM module to turn-off fully, and another brachium pontis is in conducting state, the severe phenomenon that easily causes the IPM module to be blown up.
The utility model content
Main purpose of the present utility model is to propose a kind of PWM Dead Time protective circuit and air conditioner, is intended to protect timely and effectively the IPM module, avoids the straight-through IPM module of blowing up due to the IGBT of IPM module upper and lower bridge arm.
In order to achieve the above object, the utility model proposes a kind of PWM Dead Time protective circuit, this PWM Dead Time protective circuit is connected with motor, comprise microprocessor for output at least three group pwm control signals, for described pwm control signal being carried out to the logic processing module of logical process corresponding output drive signal, and for the IPM driver module according to the described motor running of described driving signal controlling;
The input of described logic processing module is connected with the control signal output of described microprocessor, the output of described logic processing module is connected with the input of described IPM driver module, the output of described IPM driver module is connected with described motor, when described logic processing module receives abnormal pwm control signal, the driving signal by described logical process output low level is to described IPM driver module.
Preferably, described logic processing module comprises the first logical block, the second logical block and the 3rd logical block;
Described the first logical block is connected between described microprocessor and described IPM driver module, for when receiving normal pwm control signal, export the driving signal consistent with the level state of described normal pwm control signal to described IPM driver module, and, when receiving abnormal pwm control signal, the driving signal of output low level is to described IPM driver module;
Described the second logical block is connected between described microprocessor and described IPM driver module, for when receiving normal pwm control signal, export the driving signal consistent with the level state of described normal pwm control signal to described IPM driver module, and, when receiving abnormal pwm control signal, the driving signal of output low level is to described IPM driver module;
Described the 3rd logical block is connected between described microprocessor and described IPM driver module, for when receiving normal pwm control signal, export the driving signal consistent with the level state of described normal pwm control signal to described IPM driver module, and, when receiving abnormal pwm control signal, the driving signal of output low level is to described IPM driver module.
Preferably, the first input end of described the first logical block is connected with an IO mouth of described microprocessor, and the second input of described the first logical block is connected with the 2nd IO mouth of described microprocessor; The first output of described the first logical block, the second output all are connected to described IPM driver module;
The first input end of described the second logical block is connected with the 3rd IO mouth of described microprocessor, and the second input of described the second logical block is connected with the 4th IO mouth of described microprocessor; The first output of described the second logical block, the second output all are connected to described IPM driver module;
The first input end of described the 3rd logical block is connected with the 5th IO mouth of described microprocessor, and the second input of described the 3rd logical block is connected with the 6th IO mouth of described microprocessor; The first output of described the 3rd logical block, the second output all are connected to described IPM driver module.
Preferably, described the first logical block comprise the first not gate, the second not gate, first and door and second with;
The input of described the first not gate is connected with an IO mouth of described microprocessor, and the output of described the first not gate is connected with the first input end of door with described second; Described second is connected with the 2nd IO mouth of described microprocessor with the second input of door, and described second is connected to described IPM driver module with the output of door;
The input of described the second not gate is connected with the 2nd IO mouth of described microprocessor, and the output of described the second not gate is connected with the second input of door with described first; Described first is connected with an IO mouth of described microprocessor with the first input end of door, and described first is connected to described IPM driver module with the output of door.
Preferably, described the second logical block comprise the 3rd not gate, the 4th not gate, the 3rd with door and the 4th with door, described the 3rd logical block comprise the 5th not gate, the 6th not gate, the 5th with door and the 6th with door;
The input of described the 3rd not gate is connected with the 3rd IO mouth of described microprocessor, and the output of described the 3rd not gate is connected with the first input end of door with the described the 4th; The described the 4th is connected with the 4th IO mouth of described microprocessor with the second input of door, and the described the 4th is connected to described IPM driver module with the output of door;
The input of described the 4th not gate is connected with the 4th IO mouth of described microprocessor, and the output of described the 4th not gate is connected with the second input of door with the described the 3rd; The described the 3rd is connected with the 3rd IO mouth of described microprocessor with the first input end of door, and the described the 3rd is connected to described IPM driver module with the output of door;
The input of described the 5th not gate is connected with the 5th IO mouth of described microprocessor, and the output of described the 5th not gate is connected with the first input end of door with the described the 6th; The described the 6th is connected with the 6th IO mouth of described microprocessor with the second input of door, and the described the 6th is connected to described IPM driver module with the output of door;
The input of described the 6th not gate is connected with the 6th IO mouth of described microprocessor, and the output of described the 6th not gate is connected with the second input of door with the described the 5th; The described the 5th is connected with the 5th IO mouth of described microprocessor with the first input end of door, and the described the 5th is connected to described IPM driver module with the output of door.
Preferably, described IPM driver module comprises IPM chip and busbar voltage input port;
The first input pin of described IPM chip is connected with the output of door with described first, the second input pin of described IPM chip is connected with the output of door with the described the 3rd, the 3rd input pin of described IPM chip is connected with the output of door with the described the 5th, the 4th input pin of described IPM chip is connected with the output of door with described second, the 5th input pin of described IPM chip is connected with the output of door with the described the 4th, and the 6th input pin of described IPM chip is connected with the output of door with the described the 6th;
The main power source input pin of described IPM chip is connected with described busbar voltage input port, the over-current detection pin ground connection of described IPM chip;
The first output pin of described IPM chip is connected with the first phase line of described motor, and the second output pin of described IPM chip is connected with the second phase line of described motor, and the 3rd output pin of described IPM chip is connected with the third phase line of described motor.
Preferably, described IPM driver module also comprises the first resistance, the second resistance, the 3rd resistance, the first electric capacity, the second electric capacity and the 3rd electric capacity;
One end of described the first resistance is connected with the output of door with described first, and the other end of described the first resistance is connected with the first input pin of described IPM chip, and via described the first capacity earth;
One end of described the second resistance is connected with the output of door with the described the 3rd, and the other end of described the second resistance is connected with the second input pin of described IPM chip, and via described the second capacity earth;
One end of described the 3rd resistance is connected with the output of door with the described the 5th, and the other end of described the 3rd resistance is connected with the 3rd input pin of described IPM chip, and via described the 3rd capacity earth.
Preferably, described IPM driver module also comprises the 4th resistance, the 5th resistance, the 6th resistance, the 4th electric capacity, the 5th electric capacity and the 6th electric capacity;
One end of described the 4th resistance is connected with the output of door with described second, and the other end of described the 4th resistance is connected with the 4th input pin of described IPM chip, and via described the 4th capacity earth;
One end of described the 5th resistance is connected with the output of door with the described the 4th, and the other end of described the 5th resistance is connected with the 5th input pin of described IPM chip, and via described the 5th capacity earth;
One end of described the 6th resistance is connected with the output of door with the described the 6th, and the other end of described the 6th resistance is connected with the 6th input pin of described IPM chip, and via described the 6th capacity earth;
Preferably, described IPM driver module also comprises the 7th resistance;
One end of described the 7th resistance is connected with the over-current detection pin of described IPM chip, the other end ground connection of described the 7th resistance.
The utility model also proposes a kind of air conditioner, this air conditioner comprises motor, also comprise PWM Dead Time protective circuit, this PWM Dead Time protective circuit is connected with motor, comprise microprocessor for output at least three group pwm control signals, for described pwm control signal being carried out to the logic processing module of logical process corresponding output drive signal, and for the IPM driver module according to the described motor running of described driving signal controlling;
The input of described logic processing module is connected with the control signal output of described microprocessor, the output of described logic processing module is connected with the input of described IPM driver module, the output of described IPM driver module is connected with described motor, when described logic processing module receives abnormal pwm control signal, the driving signal by described logical process output low level is to described IPM driver module.
The PWM Dead Time protective circuit the utility model proposes; export at least three group pwm control signals by microprocessor; logic processing module is carried out logical process corresponding output drive signal to this pwm control signal; and when logic processing module receives abnormal pwm control signal; the driving signal of logic processing module output low level, the IPM driver module is according to the driving signal control motor running of logic processing module output.The utility model PWM Dead Time protective circuit, by logic processing module when the pwm control signal received is abnormal, the driving signal of output low level.Thereby not conducting simultaneously of the IGBT that guarantees IPM module upper and lower bridge arm, by short circuit, burnt, can protect timely and effectively the IPM module, avoid the straight-through IPM module of blowing up due to the IGBT of IPM module upper and lower bridge arm.
The accompanying drawing explanation
The theory diagram that Fig. 1 is the preferred embodiment of the utility model PWM Dead Time protective circuit;
The electrical block diagram that Fig. 2 is the preferred embodiment of the utility model PWM Dead Time protective circuit;
The internal structure schematic diagram that Fig. 3 is IPM chip in the utility model PWM Dead Time protective circuit.
The realization of the purpose of this utility model, functional characteristics and advantage, in connection with embodiment, and be described further with reference to accompanying drawing.
Embodiment
Further illustrate the technical solution of the utility model below in conjunction with Figure of description and specific embodiment.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
The utility model proposes a kind of PWM Dead Time protective circuit.
With reference to Fig. 1, the theory diagram that Fig. 1 is the preferred embodiment of the utility model PWM Dead Time protective circuit.
In the utility model preferred embodiment, PWM Dead Time protective circuit 10 is connected with motor 20, and PWM Dead Time protective circuit 10 comprises microprocessor 11, logic processing module 12 and IPM driver module 13; Microprocessor 11 is for output at least three group pwm control signals, and logic processing module 12 is for pwm control signal being carried out to logical process corresponding output drive signal, and IPM driver module 13 is for operating according to driving signal control motor 20.
Wherein, the input of logic processing module 12 is connected with the control signal output of microprocessor 11, and the output of logic processing module 12 is connected with the input of IPM driver module 13, and the output of IPM driver module 13 is connected with motor 20; When logic processing module 12 receives abnormal pwm control signal, the driving signal by logical process 12 output low levels is to IPM driver module 13.In the present embodiment, microprocessor 11 is central processor CPU or digital signal processor DSP, and motor 20 is DC brushless motor or direct current compressor.The present embodiment is when only needing to drive 20 running of a motor, 11 of microprocessors need three groups of pwm control signals of output, when needs drive a plurality of motor 20 running simultaneously, microprocessor 11 needs the group number of the pwm control signal of output can be set to 3 positive integer times, as needs drive two motors 20 simultaneously, microprocessor 11 needs six groups of pwm control signals of output, and as needs drive three motors 20 simultaneously, microprocessor 11 needs nine groups of pwm control signals of output.
In the present embodiment, microprocessor 11 output at least three group pwm control signals, every group of pwm control signal comprises brachium pontis pwm control signal and lower brachium pontis pwm control signal, this pwm control signal exports logic processing module 12 to, 12 pairs of these pwm control signals of logic processing module carry out logical process corresponding output drive signal, every group of corresponding output drives signal to comprise that brachium pontis drives signal and lower brachium pontis to drive signal, and in the situation that logic processing module 12 receives abnormal pwm control signal (upper brachium pontis pwm control signal and lower brachium pontis pwm control signal are high level) simultaneously, the driving signal of logic processing module 12 output low levels, in the situation of arbitrary group of pwm control signal output abnormality in the pwm control signal that logic processing module 12 receives (upper brachium pontis pwm control signal and lower brachium pontis pwm control signal are high level simultaneously), the driving signal (upper brachium pontis drives signal and lower brachium pontis to drive signal) that 12 pairs of logic processing module should be organized pwm control signal output is low level, IPM driver module 13 is according to driving signal control motor 20 runnings of logic processing module 12 outputs.
With respect to prior art, the utility model PWM Dead Time protective circuit 10, by logic processing module 12 when the pwm control signal received is abnormal, the driving signal of output low level.Thereby not conducting simultaneously of the IGBT that guarantees IPM module upper and lower bridge arm, by short circuit, burnt, can protect timely and effectively the IPM module, avoid the straight-through IPM module of blowing up due to the IGBT of IPM module upper and lower bridge arm.And then the functional reliability of the product of raising use IPM module, increase the service life, reduce maintenance rate.The utility model PWM Dead Time protective circuit 10 is applicable to need to use the equipment of motor 20, for example air conditioner.
In conjunction with Fig. 1 to Fig. 3, the electrical block diagram that wherein Fig. 2 is the preferred embodiment of the utility model PWM Dead Time protective circuit; The internal structure schematic diagram that Fig. 3 is IPM chip in the utility model PWM Dead Time protective circuit.
In the present embodiment, logic processing module 12 comprises the first logical block 121, the second logical block 122 and the 3rd logical block 123.
The first logical block 121 is connected between microprocessor 11 and IPM driver module 13, for when receiving normal pwm control signal (upper brachium pontis pwm control signal is high level when different with lower brachium pontis pwm control signal), export the driving signal consistent with the level state of this normal pwm control signal to IPM driver module 13, and, when receiving abnormal pwm control signal (upper brachium pontis pwm control signal and lower brachium pontis pwm control signal are high level simultaneously), the driving signal of output low level is to IPM driver module 13;
The second logical block 122 is connected between microprocessor 11 and IPM driver module 13, for when receiving normal pwm control signal (upper brachium pontis pwm control signal is high level when different with lower brachium pontis pwm control signal), export the driving signal consistent with the level state of this normal pwm control signal to IPM driver module 13, and, when receiving abnormal pwm control signal (upper brachium pontis pwm control signal and lower brachium pontis pwm control signal are high level simultaneously), the driving signal of output low level is to IPM driver module 13;
The 3rd logical block 123 is connected between microprocessor 11 and IPM driver module 13, for when receiving normal pwm control signal (upper brachium pontis pwm control signal is high level when different with lower brachium pontis pwm control signal), export the driving signal consistent with the level state of this normal pwm control signal to IPM driver module 13, and, when receiving abnormal pwm control signal (upper brachium pontis pwm control signal and lower brachium pontis pwm control signal are high level simultaneously), the driving signal of output low level is to IPM driver module 13.
Particularly, the first input end of the first logical block 121 is connected with an IO mouth IO1 of microprocessor 11, and the second input of the first logical block 121 is connected with the 2nd IO mouth IO2 of microprocessor 11; The first output, second output of the first logical block 121 all are connected to IPM driver module 13; The first input end of the second logical block 122 is connected with the 3rd IO mouth IO3 of microprocessor 11, and the second input of the second logical block 122 is connected with the 4th IO mouth IO4 of microprocessor 11; The first output, second output of the second logical block 122 all are connected to IPM driver module 13; The first input end of the 3rd logical block 123 is connected with the 5th IO mouth IO5 of microprocessor 11, and the second input of the 3rd logical block 123 is connected with the 6th IO mouth IO6 of microprocessor 11; The first output, second output of the 3rd logical block 123 all are connected to IPM driver module 13.
Further, the first logical block 121 comprise the first not gate NOT1, the second not gate NOT2, first and door AND1 and second with AND2.
The input of the first not gate NOT1 is connected with an IO mouth IO1 of microprocessor 11, and the output of the first not gate NOT1 is connected with the first input end of door AND2 with second; Second is connected with the 2nd IO mouth IO2 of microprocessor 11 with the second input of door AND2, and second is connected to IPM driver module 13 with the output of door AND2; The input of the second not gate NOT2 is connected with the 2nd IO mouth IO2 of microprocessor 11, and the output of the second not gate NOT2 is connected with the second input of door AND1 with first; First is connected with an IO mouth IO1 of microprocessor 11 with the first input end of door AND1, and first is connected to IPM driver module 13 with the output of door AND1.
The second logical block 122 comprise the 3rd not gate NOT3, the 4th not gate NOT4, the 3rd with the door AND3 and the 4th with the door AND4.
The input of the 3rd not gate NOT3 is connected with the 3rd IO mouth IO3 of microprocessor 11, and the output of the 3rd not gate NOT3 is connected with the first input end of door AND4 with the 4th; The 4th is connected with the 4th IO mouth IO4 of microprocessor 11 with the second input of door AND4, and the 4th is connected to IPM driver module 13 with the output of door AND4; The input of the 4th not gate NOT4 is connected with the 4th IO mouth IO4 of microprocessor 11, and the output of the 4th not gate NOT4 is connected with the second input of door AND3 with the 3rd; The 3rd is connected with the 3rd IO mouth IO3 of microprocessor 11 with the first input end of door AND3, and the 3rd is connected to IPM driver module 13 with the output of door AND3.
The 3rd logical block 123 comprise the 5th not gate NOT5, the 6th not gate NOT6, the 5th with the door AND5 and the 6th with the door AND6.
The input of the 5th not gate NOT5 is connected with the 5th IO mouth IO5 of microprocessor 11, and the output of the 5th not gate NOT5 is connected with the first input end of door AND6 with the 6th; The 6th is connected with the 6th IO mouth IO6 of microprocessor 11 with the second input of door AND6, and the 6th is connected to IPM driver module 13 with the output of door AND6; The input of the 6th not gate NOT6 is connected with the 6th IO mouth IO6 of microprocessor 11, and the output of the 6th not gate NOT6 is connected with the second input of door AND5 with the 5th; The 5th is connected with the 5th IO mouth IO5 of microprocessor 11 with the first input end of door AND5, and the 5th is connected to IPM driver module 13 with the output of door AND5.
In the present embodiment, IPM driver module 13 comprises IPM chip U1 and busbar voltage input port P.
Wherein, the first input pin IN1 of IPM chip U1 is connected with the output of door AND1 with first, the second input pin IN2 of IPM chip U1 is connected with the output of door AND3 with the 3rd, the 3rd input pin IN3 of IPM chip U1 is connected with the output of door AND5 with the 5th, the 4th input pin IN4 of IPM chip U1 is connected with the output of door AND2 with second, the 5th input pin IN5 of IPM chip U1 is connected with the output of door AND4 with the 4th, and the 6th input pin IN6 of IPM chip U1 is connected with the output of door AND6 with the 6th; The main power source input pin VCC of IPM chip U1 is connected with busbar voltage input port P, the over-current detection pin DET ground connection of IPM chip U1; The first output pin OUT1 of IPM chip U1 is connected with the first phase line U of motor 20, and the second output pin OUT2 of IPM chip U1 is connected with the second phase line V of motor 20, and the 3rd output pin OUT3 of IPM chip U1 is connected with the third phase line W of motor 20.
Particularly, IPM driver module 13 also comprises the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the first capacitor C 1, the second capacitor C 2 and the 3rd capacitor C 3.
One end of the first resistance R 1 is connected with the output of door AND1 with first, and the other end of the first resistance R 1 is connected with the first input pin IN1 of IPM chip U1, and via the first capacitor C 1 ground connection; One end of the second resistance R 2 is connected with the output of door AND3 with the 3rd, and the other end of the second resistance R 2 is connected with the second input pin IN2 of IPM chip U1, and via the second capacitor C 2 ground connection; One end of the 3rd resistance R 3 is connected with the output of door AND5 with the 5th, and the other end of the 3rd resistance R 3 is connected with the 3rd input pin IN3 of IPM chip U1, and via the 3rd capacitor C 3 ground connection.
Particularly, IPM driver module 13 also comprises the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 4th capacitor C 4, the 5th capacitor C 5 and the 6th capacitor C 6.
One end of the 4th resistance R 4 is connected with the output of door AND2 with second, and the other end of the 4th resistance R 4 is connected with the 4th input pin IN4 of IPM chip U1, and via the 4th capacitor C 4 ground connection; One end of the 5th resistance R 5 is connected with the output of door AND4 with the 4th, and the other end of the 5th resistance R 5 is connected with the 5th input pin IN5 of IPM chip U1, and via the 5th capacitor C 5 ground connection; One end of the 6th resistance R 6 is connected with the output of door AND6 with the 6th, and the other end of the 6th resistance R 6 is connected with the 6th input pin IN6 of IPM chip U1, and via the 6th capacitor C 6 ground connection.
Further, IPM driver module 13 also comprises the 7th resistance R 7.One end of the 7th resistance R 7 is connected with the over-current detection pin DET of IPM chip U1, the other end ground connection of the 7th resistance R 7.
The operation principle of the utility model PWM Dead Time protective circuit 10 specifically describes as follows:
As shown in Figure 2, the three groups of pwm control signals of microprocessor 11 output of take describe as example, microprocessor 11 is exported three groups of pwm control signals by its IO mouth to the six IO mouths (IO1 ~ IO6), every group of pwm control signal comprises brachium pontis pwm control signal and lower brachium pontis pwm control signal, as first group of pwm control signal in Fig. 2 comprises brachium pontis pwm control signal HPWM1 and first time brachium pontis pwm control signal LPWM1 on first, second group of pwm control signal comprises brachium pontis pwm control signal HPWM2 and second time brachium pontis pwm control signal LPWM2 on second, the 3rd group of pwm control signal comprises brachium pontis pwm control signal HPWM3 and the 3rd time brachium pontis pwm control signal LPWM3 on the 3rd.After logic processing module 12 is carried out logical process to first group of pwm control signal, second group of pwm control signal, the 3rd group of pwm control signal respectively, three groups of driving signals of corresponding output, as first group in Fig. 2 driving signal comprises that on first, brachium pontis drives signal HDRV1 and first time brachium pontis to drive signal LDRV1, second group drives signal to comprise that on second, brachium pontis drives signal HDRV2 and second time brachium pontis to drive signal LDRV2, and the 3rd group drives signal to comprise that on the 3rd, brachium pontis drives signal HDRV3 and the 3rd time brachium pontis to drive signal LDRV3.
In Fig. 2, on first, brachium pontis pwm control signal HPWM1 is low level, when first time brachium pontis pwm control signal LPWM1 is low level, on first, brachium pontis pwm control signal HPWM1 becomes high level after the first not gate NOT1, brachium pontis pwm control signal LPWM1 is low level due to first time, therefore on first of first time brachium pontis pwm control signal LPWM1 and the first not gate NOT1 output brachium pontis pwm control signal HPWM1 through second with door AND2 phase with after, second with first time brachium pontis driving signal LDRV1 of the output output of door AND2 be also low level; First time brachium pontis pwm control signal LPWM1 becomes high level after the second not gate NOT2, because brachium pontis pwm control signal HPWM1 on first is low level, therefore on first first time brachium pontis pwm control signal LPWM1 of brachium pontis pwm control signal HPWM1 and the second not gate NOT2 output through first with door AND1 phase with after, first with the output output of door AND1 first on brachium pontis driving signal HDRV1 be low level.
On low level first, brachium pontis drives signal HDRV1 to be input to the first input pin IN1 of IPM chip U1 via the first resistance R 1, low level first time brachium pontis drives signal LDRV1 to be input to the 4th input pin IN4 of IPM chip U1 via the 4th resistance R 4, thereby all ends as the first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4 of IPM chip U1 inside in Fig. 3.
On first, brachium pontis pwm control signal HPWM1 is high level, when first time brachium pontis pwm control signal LPWM1 is low level, on first, brachium pontis pwm control signal HPWM1 becomes low level after the first not gate NOT1, brachium pontis pwm control signal LPWM1 is low level due to first time, therefore on first of first time brachium pontis pwm control signal LPWM1 and the first not gate NOT1 output brachium pontis pwm control signal HPWM1 through second with door AND2 phase with after, second with first time brachium pontis driving signal LDRV1 of the output output of door AND2 be also low level; First time brachium pontis pwm control signal LPWM1 becomes high level after the second not gate NOT2, because brachium pontis pwm control signal HPWM1 on first is high level, therefore on first first time brachium pontis pwm control signal LPWM1 of brachium pontis pwm control signal HPWM1 and the second not gate NOT2 output through first with door AND1 phase with after, first with the output output of door AND1 first on brachium pontis driving signal HDRV1 be high level.
High level first on brachium pontis drive signal HDRV1 to be input to the first input pin IN1 of IPM chip U1 via the first resistance R 1, low level first time brachium pontis drives signal LDRV1 to be input to the 4th input pin IN4 of IPM chip U1 via the 4th resistance R 4, thereby, as the first metal-oxide-semiconductor M1 conducting of IPM chip U1 inside in Fig. 3, the 4th metal-oxide-semiconductor M4 cut-off, be input to the first phase line U of motor 20 through the first metal-oxide-semiconductor M1 from the direct voltage of busbar voltage input port P input (as+310V).
On first, brachium pontis pwm control signal HPWM1 is low level, when first time brachium pontis pwm control signal LPWM1 is high level, on first, brachium pontis pwm control signal HPWM1 becomes high level after the first not gate NOT1, brachium pontis pwm control signal LPWM1 is high level due to first time, therefore on first of first time brachium pontis pwm control signal LPWM1 and the first not gate NOT1 output brachium pontis pwm control signal HPWM1 through second with door AND2 phase with after, second with first time brachium pontis driving signal LDRV1 of the output output of door AND2 be also high level; First time brachium pontis pwm control signal LPWM1 becomes low level after the second not gate NOT2, because brachium pontis pwm control signal HPWM1 on first is low level, therefore on first first time brachium pontis pwm control signal LPWM1 of brachium pontis pwm control signal HPWM1 and the second not gate NOT2 output through first with door AND1 phase with after, first with the output output of door AND1 first on brachium pontis driving signal HDRV1 be low level.
On low level first, brachium pontis drives signal HDRV1 to be input to the first input pin IN1 of IPM chip U1 via the first resistance R 1, first time brachium pontis of high level drives signal LDRV1 to be input to the 4th input pin IN4 of IPM chip U1 via the 4th resistance R 4, thereby, as the first metal-oxide-semiconductor M1 cut-off, the 4th metal-oxide-semiconductor M4 conducting of IPM chip U1 inside in Fig. 3, the first phase line U that is equivalent to motor 20 receives ground.
On first, brachium pontis pwm control signal HPWM1 is high level, when first time brachium pontis pwm control signal LPWM1 is high level, on first, brachium pontis pwm control signal HPWM1 becomes low level after the first not gate NOT1, brachium pontis pwm control signal LPWM1 is high level due to first time, therefore on first of first time brachium pontis pwm control signal LPWM1 and the first not gate NOT1 output brachium pontis pwm control signal HPWM1 through second with door AND2 phase with after, second with first time brachium pontis driving signal LDRV1 of the output output of door AND2 be low level; First time brachium pontis pwm control signal LPWM1 becomes low level after the second not gate NOT2, because brachium pontis pwm control signal HPWM1 on first is high level, therefore on first first time brachium pontis pwm control signal LPWM1 of brachium pontis pwm control signal HPWM1 and the second not gate NOT2 output through first with door AND1 phase with after, first with the output output of door AND1 first on brachium pontis driving signal HDRV1 be low level.
On low level first, brachium pontis drives signal HDRV1 to be input to the first input pin IN1 of IPM chip U1 via the first resistance R 1, low level first time brachium pontis drives signal LDRV1 to be input to the 4th input pin IN4 of IPM chip U1 via the 4th resistance R 4, thereby all ends as the first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4 of IPM chip U1 inside in Fig. 3.
As can be seen here, microprocessor 11 output first on brachium pontis pwm control signal HPWM1, first time brachium pontis pwm control signal LPWM1 while being low level, the corresponding output of logic processing module 12 first on brachium pontis drive signal HDRV1, first time brachium pontis to drive signal LDRV1 also to be low level, the first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4 of IPM chip U1 inside all end.Microprocessor 11 output first on brachium pontis pwm control signal HPWM1 while also for high level, first time brachium pontis pwm control signal LPWM1, being low level, the corresponding output of logic processing module 12 first on brachium pontis to drive signal HDRV1 be also that to drive signal LDRV1 be also low level for high level, first time brachium pontis, the first metal-oxide-semiconductor M1 conducting of IPM chip U1 inside, the 4th metal-oxide-semiconductor M4 cut-off.Microprocessor 11 output first on brachium pontis pwm control signal HPWM1 while also for low level, first time brachium pontis pwm control signal LPWM1, being high level, the corresponding output of logic processing module 12 first on brachium pontis to drive signal HDRV1 be also that to drive signal LDRV1 be also high level for low level, first time brachium pontis, the first metal-oxide-semiconductor M1 cut-off of IPM chip U1 inside, the 4th metal-oxide-semiconductor M4 conducting.Microprocessor 11 output first on brachium pontis pwm control signal HPWM1, first time brachium pontis pwm control signal LPWM1 while being high level, the corresponding output of logic processing module 12 first on brachium pontis drive signal HDRV1, first time brachium pontis to drive signal LDRV1 to be as low level, the first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4 of IPM chip U1 inside all end.
Therefore, no matter brachium pontis pwm control signal HPWM1 and first time brachium pontis pwm control signal LPWM1 are when on normal condition when different (be high level) or first, brachium pontis pwm control signal HPWM1 and first time brachium pontis pwm control signal LPWM1 are abnormal conditions (being simultaneously high level) on first of microprocessor 11 outputs, the first metal-oxide-semiconductor M1 and the 4th metal-oxide-semiconductor M4 be not conducting simultaneously, the first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4 can directly not be shorted to ground, thereby can due to the direct voltage from busbar voltage input port P input (as+310V), the first metal-oxide-semiconductor M1 directly flow through, the 4th metal-oxide-semiconductor M4 is to ground, flow through the first metal-oxide-semiconductor M1, the electric current of the 4th metal-oxide-semiconductor M4 is excessive, and make the first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4 burns, thereby can effectively protect the IPM module, can not cause the IPM module to be burnt because of occurring abnormal.
In like manner, in microprocessor 11 outputs second, the level state of brachium pontis pwm control signal HPWM2 and second time brachium pontis pwm control signal LPWM2 is through the 3rd not gate NOT3, the 4th not gate NOT4, the 3rd with the door AND3 and the 4th with the door AND4 logical operation after, while making on second brachium pontis pwm control signal HPWM2 and second time brachium pontis pwm control signal LPWM2 be normal condition when different (be high level), from the 3rd from the output output of door AND3 second brachium pontis drive signal HDRV2 and second time brachium pontis to drive also normally output of signal LDRV2 when different (be high level), when on second, brachium pontis pwm control signal HPWM2 and second time brachium pontis pwm control signal LPWM2 are abnormal conditions (being simultaneously high level), from the 3rd with the output output of door AND3 second brachium pontis drive signal HDRV2 and second time brachium pontis to drive signal LDRV2 all to become low level.
Therefore, no matter brachium pontis pwm control signal HPWM2 and second time brachium pontis pwm control signal LPWM2 are when on normal condition when different (be high level) or second, brachium pontis pwm control signal HPWM2 and second time brachium pontis pwm control signal LPWM2 are abnormal conditions (being simultaneously high level) on second of microprocessor 11 outputs, the second metal-oxide-semiconductor M2 of IPM chip U1 inside and the 5th metal-oxide-semiconductor M5 be not conducting simultaneously, the second metal-oxide-semiconductor M2, the 5th metal-oxide-semiconductor M5 can directly not be shorted to ground, thereby can be due to the second metal-oxide-semiconductor M2 that directly flows through of the direct voltage from busbar voltage input port P input, the 5th metal-oxide-semiconductor M5 is to ground, flow through the second metal-oxide-semiconductor M2, the electric current of the 5th metal-oxide-semiconductor M5 is excessive, and make the second metal-oxide-semiconductor M2, the 5th metal-oxide-semiconductor M5 burns, thereby can effectively protect the IPM module, can not cause the IPM module to be burnt because of occurring abnormal.
In like manner, no matter brachium pontis pwm control signal HPWM3 and the 3rd time brachium pontis pwm control signal LPWM3 are when on normal condition when different (be high level) or the 3rd, brachium pontis pwm control signal HPWM3 and the 3rd time brachium pontis pwm control signal LPWM3 are abnormal conditions (being simultaneously high level) on the 3rd of microprocessor 11 outputs the, the 3rd metal-oxide-semiconductor M3 of IPM chip U1 inside and the 6th metal-oxide-semiconductor M6 be not conducting simultaneously, the 3rd metal-oxide-semiconductor M3, the 6th metal-oxide-semiconductor M6 can directly not be shorted to ground, thereby can be due to the 3rd metal-oxide-semiconductor M3 that directly flows through of the direct voltage from busbar voltage input port P input, the 6th metal-oxide-semiconductor M6 is to ground, flow through the 3rd metal-oxide-semiconductor M3, the electric current of the 6th metal-oxide-semiconductor M6 is excessive, and make the 3rd metal-oxide-semiconductor M3, the 6th metal-oxide-semiconductor M6 burns, thereby can effectively protect the IPM module, can not cause the IPM module to be burnt because of occurring abnormal.
The utility model also proposes a kind of air conditioner; this air conditioner comprises motor 20 and PWM Dead Time protective circuit 10; structure, the operation principle of this PWM Dead Time protective circuit 10 and the beneficial effect brought all can, with reference to above-described embodiment, repeat no more herein.
The foregoing is only preferred embodiment of the present utility model; not thereby limit the scope of the claims of the present utility model; every equivalent structure or conversion of equivalent flow process that utilizes the utility model specification and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in scope of patent protection of the present utility model.
Claims (10)
1. a PWM Dead Time protective circuit, with motor, be connected, it is characterized in that, comprise microprocessor for output at least three group pwm control signals, for described pwm control signal being carried out to the logic processing module of logical process corresponding output drive signal, and for the IPM driver module according to the described motor running of described driving signal controlling;
The input of described logic processing module is connected with the control signal output of described microprocessor, the output of described logic processing module is connected with the input of described IPM driver module, the output of described IPM driver module is connected with described motor, when described logic processing module receives abnormal pwm control signal, the driving signal by described logical process output low level is to described IPM driver module.
2. PWM Dead Time protective circuit as claimed in claim 1, is characterized in that, described logic processing module comprises the first logical block, the second logical block and the 3rd logical block;
Described the first logical block is connected between described microprocessor and described IPM driver module, for when receiving normal pwm control signal, export the driving signal consistent with the level state of described normal pwm control signal to described IPM driver module, and, when receiving abnormal pwm control signal, the driving signal of output low level is to described IPM driver module;
Described the second logical block is connected between described microprocessor and described IPM driver module, for when receiving normal pwm control signal, export the driving signal consistent with the level state of described normal pwm control signal to described IPM driver module, and, when receiving abnormal pwm control signal, the driving signal of output low level is to described IPM driver module;
Described the 3rd logical block is connected between described microprocessor and described IPM driver module, for when receiving normal pwm control signal, export the driving signal consistent with the level state of described normal pwm control signal to described IPM driver module, and, when receiving abnormal pwm control signal, the driving signal of output low level is to described IPM driver module.
3. PWM Dead Time protective circuit as claimed in claim 2, it is characterized in that, the first input end of described the first logical block is connected with an IO mouth of described microprocessor, and the second input of described the first logical block is connected with the 2nd IO mouth of described microprocessor; The first output of described the first logical block, the second output all are connected to described IPM driver module;
The first input end of described the second logical block is connected with the 3rd IO mouth of described microprocessor, and the second input of described the second logical block is connected with the 4th IO mouth of described microprocessor; The first output of described the second logical block, the second output all are connected to described IPM driver module;
The first input end of described the 3rd logical block is connected with the 5th IO mouth of described microprocessor, and the second input of described the 3rd logical block is connected with the 6th IO mouth of described microprocessor; The first output of described the 3rd logical block, the second output all are connected to described IPM driver module.
4. PWM Dead Time protective circuit as claimed in claim 3, is characterized in that, described the first logical block comprise the first not gate, the second not gate, first and door and second with;
The input of described the first not gate is connected with an IO mouth of described microprocessor, and the output of described the first not gate is connected with the first input end of door with described second; Described second is connected with the 2nd IO mouth of described microprocessor with the second input of door, and described second is connected to described IPM driver module with the output of door;
The input of described the second not gate is connected with the 2nd IO mouth of described microprocessor, and the output of described the second not gate is connected with the second input of door with described first; Described first is connected with an IO mouth of described microprocessor with the first input end of door, and described first is connected to described IPM driver module with the output of door.
5. PWM Dead Time protective circuit as claimed in claim 4, it is characterized in that, described the second logical block comprise the 3rd not gate, the 4th not gate, the 3rd with door and the 4th with door, described the 3rd logical block comprise the 5th not gate, the 6th not gate, the 5th with door and the 6th with door;
The input of described the 3rd not gate is connected with the 3rd IO mouth of described microprocessor, and the output of described the 3rd not gate is connected with the first input end of door with the described the 4th; The described the 4th is connected with the 4th IO mouth of described microprocessor with the second input of door, and the described the 4th is connected to described IPM driver module with the output of door;
The input of described the 4th not gate is connected with the 4th IO mouth of described microprocessor, and the output of described the 4th not gate is connected with the second input of door with the described the 3rd; The described the 3rd is connected with the 3rd IO mouth of described microprocessor with the first input end of door, and the described the 3rd is connected to described IPM driver module with the output of door;
The input of described the 5th not gate is connected with the 5th IO mouth of described microprocessor, and the output of described the 5th not gate is connected with the first input end of door with the described the 6th; The described the 6th is connected with the 6th IO mouth of described microprocessor with the second input of door, and the described the 6th is connected to described IPM driver module with the output of door;
The input of described the 6th not gate is connected with the 6th IO mouth of described microprocessor, and the output of described the 6th not gate is connected with the second input of door with the described the 5th; The described the 5th is connected with the 5th IO mouth of described microprocessor with the first input end of door, and the described the 5th is connected to described IPM driver module with the output of door.
6. PWM Dead Time protective circuit as claimed in claim 5, is characterized in that, described IPM driver module comprises IPM chip and busbar voltage input port;
The first input pin of described IPM chip is connected with the output of door with described first, the second input pin of described IPM chip is connected with the output of door with the described the 3rd, the 3rd input pin of described IPM chip is connected with the output of door with the described the 5th, the 4th input pin of described IPM chip is connected with the output of door with described second, the 5th input pin of described IPM chip is connected with the output of door with the described the 4th, and the 6th input pin of described IPM chip is connected with the output of door with the described the 6th;
The main power source input pin of described IPM chip is connected with described busbar voltage input port, the over-current detection pin ground connection of described IPM chip;
The first output pin of described IPM chip is connected with the first phase line of described motor, and the second output pin of described IPM chip is connected with the second phase line of described motor, and the 3rd output pin of described IPM chip is connected with the third phase line of described motor.
7. PWM Dead Time protective circuit as claimed in claim 6, is characterized in that, described IPM driver module also comprises the first resistance, the second resistance, the 3rd resistance, the first electric capacity, the second electric capacity and the 3rd electric capacity;
One end of described the first resistance is connected with the output of door with described first, and the other end of described the first resistance is connected with the first input pin of described IPM chip, and via described the first capacity earth;
One end of described the second resistance is connected with the output of door with the described the 3rd, and the other end of described the second resistance is connected with the second input pin of described IPM chip, and via described the second capacity earth;
One end of described the 3rd resistance is connected with the output of door with the described the 5th, and the other end of described the 3rd resistance is connected with the 3rd input pin of described IPM chip, and via described the 3rd capacity earth.
8. PWM Dead Time protective circuit as described as claim 6 or 7, is characterized in that, described IPM driver module also comprises the 4th resistance, the 5th resistance, the 6th resistance, the 4th electric capacity, the 5th electric capacity and the 6th electric capacity;
One end of described the 4th resistance is connected with the output of door with described second, and the other end of described the 4th resistance is connected with the 4th input pin of described IPM chip, and via described the 4th capacity earth;
One end of described the 5th resistance is connected with the output of door with the described the 4th, and the other end of described the 5th resistance is connected with the 5th input pin of described IPM chip, and via described the 5th capacity earth;
One end of described the 6th resistance is connected with the output of door with the described the 6th, and the other end of described the 6th resistance is connected with the 6th input pin of described IPM chip, and via described the 6th capacity earth.
9. PWM Dead Time protective circuit as claimed in claim 8, is characterized in that, described IPM driver module also comprises the 7th resistance;
One end of described the 7th resistance is connected with the over-current detection pin of described IPM chip, the other end ground connection of described the 7th resistance.
10. an air conditioner, comprise motor, it is characterized in that, also comprises the described PWM Dead Time of any one protective circuit in claim 1 to 9.
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| CN201320461384.8U CN203368316U (en) | 2013-07-30 | 2013-07-30 | PWM dead-time protective circuit and air conditioner |
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| CN201320461384.8U CN203368316U (en) | 2013-07-30 | 2013-07-30 | PWM dead-time protective circuit and air conditioner |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105048794A (en) * | 2015-01-28 | 2015-11-11 | 南通昱品通信科技有限公司 | Insulated Gate Bipolar Transistor (IGBT) driver interlock circuit with power-on time delay function |
| CN105099418A (en) * | 2015-06-23 | 2015-11-25 | 珠海格力电器股份有限公司 | Insulated gate bipolar transistor drive circuit |
| CN112104303A (en) * | 2020-09-14 | 2020-12-18 | 珠海格力电器股份有限公司 | Fault detection method of control circuit, motor controller and servo control system |
| CN112271771A (en) * | 2020-10-14 | 2021-01-26 | 吴斌 | Fill electric pile remote control interlocking control circuit |
| CN113492678A (en) * | 2020-04-07 | 2021-10-12 | 蜂巢传动系统(江苏)有限公司保定研发分公司 | Drive motor control system and method for ensuring safety thereof |
-
2013
- 2013-07-30 CN CN201320461384.8U patent/CN203368316U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105048794A (en) * | 2015-01-28 | 2015-11-11 | 南通昱品通信科技有限公司 | Insulated Gate Bipolar Transistor (IGBT) driver interlock circuit with power-on time delay function |
| CN105099418A (en) * | 2015-06-23 | 2015-11-25 | 珠海格力电器股份有限公司 | Insulated gate bipolar transistor drive circuit |
| CN105099418B (en) * | 2015-06-23 | 2018-01-23 | 珠海格力电器股份有限公司 | Bipolar transistor driving circuit of insulated gate |
| CN113492678A (en) * | 2020-04-07 | 2021-10-12 | 蜂巢传动系统(江苏)有限公司保定研发分公司 | Drive motor control system and method for ensuring safety thereof |
| CN112104303A (en) * | 2020-09-14 | 2020-12-18 | 珠海格力电器股份有限公司 | Fault detection method of control circuit, motor controller and servo control system |
| CN112271771A (en) * | 2020-10-14 | 2021-01-26 | 吴斌 | Fill electric pile remote control interlocking control circuit |
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