CN110993438B - Three-relay interlocking circuit - Google Patents
Three-relay interlocking circuit Download PDFInfo
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- CN110993438B CN110993438B CN201911105847.5A CN201911105847A CN110993438B CN 110993438 B CN110993438 B CN 110993438B CN 201911105847 A CN201911105847 A CN 201911105847A CN 110993438 B CN110993438 B CN 110993438B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/22—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
- H01H47/32—Energising current supplied by semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/001—Functional circuits, e.g. logic, sequencing, interlocking circuits
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Abstract
The invention provides a three-relay interlock circuit, which comprises execution relays J1, J2 and J3; isolation diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12; the power amplification triodes Q1, Q2, Q3 and Q4 are simple in circuit structure and process flow, and the device types are all conventional components, so that engineering is easy to realize. The invention provides a three-relay interlocking circuit implementation method, which realizes the function of at most one path of conduction on one hand, and realizes the three-relay interlocking function on the other hand from the reliability aspect of a hardware circuit.
Description
Technical Field
The invention relates to a three-relay interlocking circuit.
Background
The existing three-relay circuit of the spacecraft cannot realize the function of at most one-way conduction, and cannot realize the three-relay interlocking function in the aspect of the reliability of a hardware circuit.
Disclosure of Invention
The invention aims to provide a three-relay interlocking circuit.
To solve the above problems, the present invention provides a three-relay interlock circuit, including: executive relays J1, J2, J3; isolation diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12; power amplifying triodes Q1, Q2, Q3 and Q4; wherein,
the contact 8 of the relay J1 is connected with the anode of an isolation diode D1, the contact 7 of the relay J2 is connected with the anode of an isolation diode D2, the contact 7 of the relay J3 is connected with an isolation diode D3, the cathodes of the isolation diodes D1, D2 and D3 are connected with the collector C of a triode Q1, and the emitter E of the triode Q1 is connected with a command power supply ground;
the contact 8 of the relay J2 is connected with the anode of an isolation diode D4, the contact 7 of the relay J1 is connected with the anode of an isolation diode D5, the contact 7 of the relay J3 is connected with an isolation diode D6, the cathodes of the isolation diodes D4, D5 and D6 are connected with the collector C of a triode Q2, and the emitter E of the triode Q2 is connected with a command power supply ground;
the contact 8 of the relay J3 is connected with the anode of an isolation diode D7, the contact 7 of the relay J1 is connected with the anode of an isolation diode D8, the contact 7 of the relay J2 is connected with an isolation diode D9, the cathodes of the isolation diodes D7, D8 and D9 are connected with the collector C of a triode Q3, and the emitter E of the triode Q3 is connected with a command power supply ground;
the contact 7 of the relay J1 is connected with the anode of an isolation diode D10, the contact 7 of the relay J2 is connected with the anode of the isolation diode D11, the contact 7 of the relay J3 is connected with an isolation diode D12, the cathodes of the isolation diodes D10, D11 and D12 are connected with the collector C of a triode Q4, and the emitter E of the triode Q4 is connected with a command power supply ground.
Further, in the three-relay interlock circuit, when the signal "J1 on-J2J 3 off" is in the single pulse state, the relay J1 is turned on, the relay J2 is turned off, and the relay J3 is turned off.
Further, in the three-relay interlock circuit, when the signal "J2 on-J1J 3 off" is in the single pulse state, the relay J2 is turned on, the relay J1 is turned off, and the relay J3 is turned off.
Further, in the three-relay interlock circuit, when the signal "J3 on-J1J 2 off" is in the single pulse state, the relay J3 is turned on, the relay J1 is turned off, and the relay J2 is turned off.
Further, in the three-relay interlock circuit, when the signal "J1J 2J3 off" is in the single pulse state, the relay J1 is turned off, the relay J2 is turned off, and the relay J3 is turned off.
Compared with the prior art, the invention comprises actuating relays J1, J2 and J3; isolation diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12; the power amplification triodes Q1, Q2, Q3 and Q4 are simple in circuit structure and process flow, and the device types are all conventional components, so that engineering is easy to realize. The invention provides a three-relay interlocking circuit implementation method, which realizes the function of at most one path of conduction on one hand, and realizes the three-relay interlocking function on the other hand from the reliability aspect of a hardware circuit.
Drawings
FIG. 1 is a block diagram of a three relay interlock circuit in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of the logic of a three-relay interlock in accordance with an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1 and 2, the present invention provides a three-relay interlock circuit including: executive relays J1, J2, J3; isolation diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12; power amplifying triodes Q1, Q2, Q3 and Q4; wherein,
the contact 8 of the relay J1 is connected with the anode of an isolation diode D1, the contact 7 of the relay J2 is connected with the anode of an isolation diode D2, the contact 7 of the relay J3 is connected with an isolation diode D3, the cathodes of the isolation diodes D1, D2 and D3 are connected with the collector C of a triode Q1, and the emitter E of the triode Q1 is connected with a command power supply ground;
the contact 8 of the relay J2 is connected with the anode of an isolation diode D4, the contact 7 of the relay J1 is connected with the anode of an isolation diode D5, the contact 7 of the relay J3 is connected with an isolation diode D6, the cathodes of the isolation diodes D4, D5 and D6 are connected with the collector C of a triode Q2, and the emitter E of the triode Q2 is connected with a command power supply ground;
the contact 8 of the relay J3 is connected with the anode of an isolation diode D7, the contact 7 of the relay J1 is connected with the anode of an isolation diode D8, the contact 7 of the relay J2 is connected with an isolation diode D9, the cathodes of the isolation diodes D7, D8 and D9 are connected with the collector C of a triode Q3, and the emitter E of the triode Q3 is connected with a command power supply ground;
the contact 7 of the relay J1 is connected with the anode of an isolation diode D10, the contact 7 of the relay J2 is connected with the anode of the isolation diode D11, the contact 7 of the relay J3 is connected with an isolation diode D12, the cathodes of the isolation diodes D10, D11 and D12 are connected with the collector C of a triode Q4, and the emitter E of the triode Q4 is connected with a command power supply ground.
In an embodiment of the three-relay interlock circuit, if a signal "J1 on-J2J 3 off" is in a single pulse state, the relay J1 is turned on, the relay J2 is turned off, and the relay J3 is turned off, so that only the relay J1 is turned on.
In an embodiment of the three-relay interlock circuit, if a signal "J2 on-J1J 3 off" is in a single pulse state, the relay J2 is turned on, the relay J1 is turned off, and the relay J3 is turned off, so that only the relay J2 is turned on.
In an embodiment of the three-relay interlock circuit, if a signal "J3 on-J1J 2 off" is in a single pulse state, the relay J3 is turned on, the relay J1 is turned off, and the relay J2 is turned off, so that only the relay J3 is turned on.
In an embodiment of the three-relay interlock circuit, if the signal "J1J 2J3 off" is in the single pulse state, the relay J1 is turned off, the relay J2 is turned off, and the relay J3 is turned off, so that the functions of turning off all the relays J1, J2 and J3 are realized.
Here, one end of the triple-relay interlock circuit of the present invention is connected to the base B of the NPN transistor Q1, one end of the triple-relay interlock circuit is connected to the base B of the NPN transistor Q2, one end of the triple-relay interlock circuit is connected to the base B of the NPN transistor Q3, and one end of the triple-relay interlock circuit is connected to the base (B) of the NPN transistor Q4. The triple relay interlock circuit includes executive relays J1, J2, J3; isolation diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12; and power amplifying triodes Q1, Q2, Q3 and Q4. The signals "J1 on-J2J 3 off", "J2 on-J1J 3 off", "J3 on-J1J 2 off" and "J1J 2J3 off" are all level driving signals, and only one of the signals is in a single-pulse driving state at the same time. If the signal "J1 on-J2J 3 off" is in a single pulse state, the transistor Q1 is driven to be conducted, so that the signals "J1 on", "J2 off" and "J3 off" are conducted to the ground, the contact 1 and the contact 2 of the relay J1, the contact 3 and the contact 4 are driven to be conducted, the contact 1 and the contact 2 of the relay J2, the contact 3 and the contact 4 are disconnected, the contact 1 and the contact 2 of the relay J3, and the contact 3 and the contact 4 are disconnected, and the power "input power positive line" and the power "output power positive line" are ensured to be conducted only through the relay J1; if the signal "J2 on-J1J 3 off" is in a single pulse state, the transistor Q2 is driven to be conducted, so that the signals "J2 on", "J1 off" and "J3 off" are conducted to the ground, the contact 1 and the contact 2 of the relay J2, the contact 3 and the contact 4 are driven to be conducted, the contact 1 and the contact 2 of the relay J1, the contact 3 and the contact 4 are disconnected, the contact 1 and the contact 2 of the relay J3, and the contact 3 and the contact 4 are disconnected, and the power "input power positive line" and the power "output power positive line" are ensured to be conducted only through the relay J2; if the signal "J3 on-J1J 2 off" is in a single pulse state, the transistor Q3 is driven to be conducted, so that the signals "J3 on", "J1 off" and "J2 off" are conducted to the ground, the contact 1 and the contact 2 of the relay J3, the contact 3 and the contact 4 are driven to be conducted, the contact 1 and the contact 2 of the relay J1, the contact 3 and the contact 4 are disconnected, the contact 1 and the contact 2 of the relay J2, and the contact 3 and the contact 4 are disconnected, and the power "input power positive line" and the power "output power positive line" are ensured to be conducted only through the relay J3; if the signal "J1J 2J3 off" is in a single pulse state, the driving transistor Q4 is turned on, so that the signals "J1 off", "J2 off", and "J3 off" are turned on to the ground, the contact 1 and the contact 2 of the driving relay J1 and the contact 3 and the contact 4 are turned off, the contact 1 and the contact 2 of the relay J2 and the contact 3 and the contact 4 are turned off, the contact 1 and the contact 2 of the relay J3 and the contact 3 and the contact 4 are turned off, and the complete disconnection of the power "input power positive line" and the power output positive line "is ensured. The three-relay interlocking function can be realized by reasonably setting the level states of signals 'J1 on-J2J 3 off', 'J2 on-J1J 3 off', 'J3 on-J1J 2 off' and 'J1J 2J3 off', so that the function of either full off or only one relay is on is realized.
After the signal J1 is on and the signal J2J3 is off, the relay J1 is on, the relay J2 is off and the relay J3 is off correspondingly; after the signal J2 is on and the signal J1J3 is off, the relay J2 is on, the relay J1 is off and the relay J3 is off correspondingly; after the signal J3 is on and the signal J1J2 is off, the relay J3 is on, the relay J1 is off and the relay J2 is off correspondingly; after the signal "J1J 2J3 is turned off" is in the single pulse state, the relay J1 is turned off, the relay J2 is turned off, and the relay J3 is turned off. At most one of the 4 signals is in a single-pulse state at the same time.
The single pulse refers in particular to a high-level pulse which can enable the triodes Q1, Q2, Q3 and Q4 to be conducted, and a proper current-limiting resistor is selected at the base (B) of the triode to realize the required driving current according to the amplitude of the high-level pulse and the type selection of the triode; the pulse time is not lower than the action time of the relays J1, J2 and J3, while the action time of the conventional relays is in the order of tens of milliseconds, so that the pulse time of a single pulse is at least more than 50 milliseconds, and generally 80 milliseconds or 160 milliseconds.
The invention provides a three-relay interlocking circuit implementation method, which is simple in circuit structure and process flow, and easy to implement in engineering, and the types of devices are all conventional components. The invention provides a three-relay interlocking circuit implementation method, which realizes the function of at most one path of conduction on one hand, and realizes the three-relay interlocking function on the other hand from the reliability aspect of a hardware circuit.
The three-relay interlock circuit and method of the present invention will be described in further detail below with reference to fig. 1-2.
Referring to fig. 1, the triple relay interlock circuit includes actuating relays J1, J2, J3; isolation diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12; and power amplifying triodes Q1, Q2, Q3 and Q4. The signals "J1 on-J2J 3 off", "J2 on-J1J 3 off", "J3 on-J1J 2 off" and "J1J 2J3 off" are all level driving signals, and only one of the signals is in a single-pulse driving state at the same time. If the signal "J1 on-J2J 3 off" is in a single pulse state, the transistor Q1 is driven to be conducted, so that the signals "J1 on", "J2 off" and "J3 off" are conducted to the ground, the contact 1 and the contact 2 of the relay J1, the contact 3 and the contact 4 are driven to be conducted, the contact 1 and the contact 2 of the relay J2, the contact 3 and the contact 4 are disconnected, the contact 1 and the contact 2 of the relay J3, and the contact 3 and the contact 4 are disconnected, and the power "input power positive line" and the power "output power positive line" are ensured to be conducted only through the relay J1; if the signal "J2 on-J1J 3 off" is in a single pulse state, the transistor Q2 is driven to be conducted, so that the signals "J2 on", "J1 off" and "J3 off" are conducted to the ground, the contact 1 and the contact 2 of the relay J2, the contact 3 and the contact 4 are driven to be conducted, the contact 1 and the contact 2 of the relay J1, the contact 3 and the contact 4 are disconnected, the contact 1 and the contact 2 of the relay J3, and the contact 3 and the contact 4 are disconnected, and the power "input power positive line" and the power "output power positive line" are ensured to be conducted only through the relay J2; if the signal "J3 on-J1J 2 off" is in a single pulse state, the transistor Q3 is driven to be conducted, so that the signals "J3 on", "J1 off" and "J2 off" are conducted to the ground, the contact 1 and the contact 2 of the relay J3, the contact 3 and the contact 4 are driven to be conducted, the contact 1 and the contact 2 of the relay J1, the contact 3 and the contact 4 are disconnected, the contact 1 and the contact 2 of the relay J2, and the contact 3 and the contact 4 are disconnected, and the power "input power positive line" and the power "output power positive line" are ensured to be conducted only through the relay J3; if the signal "J1J 2J3 off" is in a single pulse state, the driving transistor Q4 is turned on, so that the signals "J1 off", "J2 off", and "J3 off" are turned on to the ground, the contact 1 and the contact 2 of the driving relay J1 and the contact 3 and the contact 4 are turned off, the contact 1 and the contact 2 of the relay J2 and the contact 3 and the contact 4 are turned off, the contact 1 and the contact 2 of the relay J3 and the contact 3 and the contact 4 are turned off, and the complete disconnection of the power "input power positive line" and the power output positive line "is ensured. The three-relay interlocking function can be realized by reasonably setting the level states of signals 'J1 on-J2J 3 off', 'J2 on-J1J 3 off', 'J3 on-J1J 2 off' and 'J1J 2J3 off', so that the function of either full off or only one relay is on is realized.
The logic diagram of the three-relay interlock of the embodiment is shown in fig. 2, and the single pulse time of four signals, such as the signal "J1 on-J2J 3 off", the signal "J2 on-J1J 2 off", the signal "J3 on-J1J 2 off", the signal "J1J 2J3 off" is not less than the maximum action time of the relays J1, J2, and J3. The detailed explanation analysis according to the time axis is as follows:
0 to t 1: the contacts 1 and 2, and the contacts 3 and 4 of the relays J1, J2 and J3 are in initial states and are in off states by default;
t 1-t 2: the relay J1 is in the on action state, and the relays J2 and J3 are in the off action time;
t 2-t 3: the contact 1 and the contact 2 of the relay J1 and the contact 2 and the contact 4 are in on states, the contact 1 and the contact 2 of the relay J2 and the contact 2 and the contact 4 are in off states, and the contact 1 and the contact 2 of the relay J3 and the contact 4 are in off states;
t 3-t 4: the relay J2 is in the on action state, and the relays J1 and J3 are in the off action time; (ii) a
t 4-t 5: the contact 1 and the contact 2 of the relay J2 and the contact 2 and the contact 4 are in on states, the contact 1 and the contact 2 of the relay J1 and the contact 2 and the contact 4 are in off states, and the contact 1 and the contact 2 of the relay J3 and the contact 4 are in off states;
t 5-t 6: the relay J3 is in the on action state, and the relays J1 and J2 are in the off action time; (ii) a
t 6-t 7: the contact 1 and the contact 2 of the relay J3 and the contact 2 and the contact 4 are in on states, the contact 1 and the contact 2 of the relay J1 and the contact 2 and the contact 4 are in off states, and the contact 1 and the contact 2 of the relay J2 and the contact 4 are in off states;
t 7-t 8: the relays J1, J2, J3 are in the off action time; (ii) a
t 8-t 9: the contact 1 and the contact 2 of the relay J1 and the contact 2 and the contact 4 are in an open state, the contact 1 and the contact 2 of the relay J1 and the contact 2 and the contact 4 are in an open state, and the contact 1 and the contact 2 of the relay J2 and the contact 4 are in an open state;
to this end, the interlocking logic descriptions of the four signals "J1 ON-J2J 3 OFF", "J2 ON-J1J 2 OFF", "J3 ON-J1J 2 OFF", and "J1J 2J3 OFF" are completed. The subsequent logics from t9 to t10 are consistent with the logics from t1 to t2, the logics from t10 to t11 are consistent with the logics from t2 to t3, and the logics from t11 to t12 are consistent with the logics from t3 to t 4.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (1)
1. A three-relay interlock circuit, comprising: executive relays J1, J2, J3; isolation diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12; power amplifying triodes Q1, Q2, Q3 and Q4; wherein,
the contact 8 of the relay J1 is connected with the anode of an isolation diode D1, the contact 7 of the relay J2 is connected with the anode of an isolation diode D2, the contact 7 of the relay J3 is connected with an isolation diode D3, the cathodes of the isolation diodes D1, D2 and D3 are connected with the collector C of a triode Q1, and the emitter E of the triode Q1 is connected with a command power supply ground;
the contact 8 of the relay J2 is connected with the anode of an isolation diode D4, the contact 7 of the relay J1 is connected with the anode of an isolation diode D5, the contact 7 of the relay J3 is connected with an isolation diode D6, the cathodes of the isolation diodes D4, D5 and D6 are connected with the collector C of a triode Q2, and the emitter E of the triode Q2 is connected with a command power supply ground;
the contact 8 of the relay J3 is connected with the anode of an isolation diode D7, the contact 7 of the relay J1 is connected with the anode of an isolation diode D8, the contact 7 of the relay J2 is connected with an isolation diode D9, the cathodes of the isolation diodes D7, D8 and D9 are connected with the collector C of a triode Q3, and the emitter E of the triode Q3 is connected with a command power supply ground;
the contact 7 of the relay J1 is connected with the anode of an isolation diode D10, the contact 7 of the relay J2 is connected with the anode of an isolation diode D11, the contact 7 of the relay J3 is connected with an isolation diode D12, the cathodes of the isolation diodes D10, D11 and D12 are connected with the collector C of a triode Q4, the emitter E of the triode Q4 is connected with a command power ground,
after the signal 'J1 ON-J2J 3 OFF' is in a single pulse state, the relay J1 is turned on, the relay J2 is turned off, and the relay J3 is turned off; after the signal 'J2 ON-J1J 3 OFF' is in a single pulse state, the relay J2 is turned on, the relay J1 is turned off, and the relay J3 is turned off; after the signal 'J3 ON-J1J 2 OFF' is in a single pulse state, the relay J3 is turned on, the relay J1 is turned off, and the relay J2 is turned off; after the signal "J1J 2J3 is OFF" is in the single pulse state, the relay J1 is open, the relay J2 is open, the relay J3 is open,
at most one of the 4 signals is in a single-pulse state at the same time.
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| CN111697643B (en) * | 2020-05-22 | 2022-03-25 | 杭州高特电子设备股份有限公司 | Multi-path relay interlocking circuit and device |
| CN112614743B (en) * | 2020-12-24 | 2024-03-08 | 通号万全信号设备有限公司 | Non-gate control relay interlocking circuit |
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| CN205900444U (en) * | 2016-08-16 | 2017-01-18 | 湖北三江航天红峰控制有限公司 | Interlock circuit of relay control |
| CN206421188U (en) * | 2017-01-17 | 2017-08-18 | 嘉兴市世恒电子科技有限公司 | A kind of electronic interlocking controls circuit |
| CN107276211A (en) * | 2017-06-27 | 2017-10-20 | 合肥尚硕新能源有限公司 | A kind of dual power supply interlocks switching circuit |
| CN207853873U (en) * | 2018-02-27 | 2018-09-11 | 北京新能源汽车股份有限公司 | Drive interlocking circuit and car |
| CN208400741U (en) * | 2018-05-09 | 2019-01-18 | 浙江华云信息科技有限公司 | Phase-change switch device systems are not powered off with mechanical interlocked and electronic interlocking |
| CN108933586A (en) * | 2018-07-24 | 2018-12-04 | 南京雨花智高科教工作坊 | Electronic interlocking circuit structure |
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