CN111697643B - Multi-path relay interlocking circuit and device - Google Patents

Multi-path relay interlocking circuit and device Download PDF

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Publication number
CN111697643B
CN111697643B CN202010441141.2A CN202010441141A CN111697643B CN 111697643 B CN111697643 B CN 111697643B CN 202010441141 A CN202010441141 A CN 202010441141A CN 111697643 B CN111697643 B CN 111697643B
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driving
pole
double
type mos
relay
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CN111697643A (en
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夏建兵
杨煜光
蔡景国
夏晨强
林存业
钱程隆
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Hangzhou Gold Electronic Equipment Co Ltd
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0069Charging or discharging for charge maintenance, battery initiation or rejuvenation
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0014Circuits for equalisation of charge between batteries
    • H02J7/0019Circuits for equalisation of charge between batteries using switched or multiplexed charge circuits
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0047Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with monitoring or indicating devices or circuits
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

The application relates to the field of battery pack charging, in particular to a battery pack charging multi-path relay interlocking circuit and device. A multi-path relay interlocking circuit comprises a double-pole normally open relay, a plurality of diodes, a driving P-type MOS tube and a driving isolation resistor R1; the driving isolation resistor is connected with the output port; the diodes are used for connecting or connecting the cathode of the battery pack monitoring module with the G pole of the driving P-type MOS tube Q1 in parallel aiming at the number of the batteries reduced by one; the driving isolation resistor R1 is connected with the G pole of the driving P-type MOS tube; and the D pole of the driving P-type MOS tube is connected with a power supply input VCC. The interlocking function is added on the basis that the self-locking of the decoder is adopted in the driving circuit.

Description

Multi-path relay interlocking circuit and device
Technical Field
The application relates to the field of battery pack charging, in particular to a battery pack charging multi-path relay interlocking circuit and device.
Background
Whether it is a power substation, a communication/IDC room, a communication base station, a railway/rail traffic signal system, or an Uninterruptible Power Supply (UPS), the battery pack plays an extremely important role in the system as a backup power source, but there may be a faster decay in part of the battery life due to long-term float operation. Therefore, the battery pack monitoring module in the current backup power supply generally has the functions of charging and discharging maintenance and plays a certain role in maintaining the batteries in the battery pack.
However, for reasons of size and cost, most of the schemes using a common channel implement the maintenance function for each battery. The method is characterized in that a relay or an electronic switch is used for switching on only one battery needing to be maintained in a battery pack and a public channel each time to carry out charging and discharging maintenance. As shown in figure 1, the number of the double-pole relays is matched with the number of the sections of the battery pack, and a group of moving points (or static points) of all the relays are connected to the positive end and the negative end of a common channel. Therefore, a possible risk is brought, although the relay controller has a design of preventing misoperation, the battery pack monitoring module still brings interference to the driving tube of the relay under strong interference such as surge, and the driving tube is conducted by mistake, so that the local short circuit of the battery pack is caused, and the serious consequence is caused.
Disclosure of Invention
In order to prevent the action of more than two paths of relays at the same time on hardware, the application provides a multi-path relay interlocking circuit and a multi-path relay interlocking device, and an interlocking function is added on the self-locking basis of a decoder in a driving circuit.
In order to achieve the above object, the present application adopts the following technical solutions:
a multi-path relay interlocking circuit comprises a double-pole normally open relay, a plurality of diodes, a driving P-type MOS tube and a driving isolation resistor R1; the driving isolation resistor is connected with the output port;
the diodes are used for connecting or connecting the cathode of the battery pack monitoring module with the G pole of the driving P-type MOS tube Q1 in parallel aiming at the number of the batteries reduced by one;
the driving isolation resistor R1 is connected with the G pole of the driving P-type MOS tube;
the D pole of the driving P-type MOS tube is connected with a power supply input VCC;
the input ports of the double-pole normally open relay are respectively connected with the S poles of the driving P-type MOS tubes; a pair of dead points of the double-pole normally open relay is simultaneously connected with positive and negative ends B + and B-of the common channel; the other pair of the moving points of one double-pole normally open relay is connected with one battery, and the first double-pole normally open relay is connected with the batteries B1+ and B2+ (namely B1-).
The application also discloses multi-way relay interlock, the device includes:
1) the controller comprises output ports I-K1, I-K2 and I-K3 … … I-Kn which respectively correspond to the n paths of relay interlocking circuits;
2) each relay interlocking circuit comprises a double-pole normally open relay, a quick switch diode, a driving P-type MOS tube and a driving isolation resistor;
the n driving isolation resistors are respectively R1, R2 and R3 … … Rn and are respectively connected with output ports I-K1, I-K2 and I-K3 … … I-Kn;
n drive P-type MOS tubes, Q1, Q2 and Q3 … … Qn;
n double-pole normally open relays are respectively K1, K2 and K3 … … Kn, and input ports are respectively O-K1, O-K2 and O-K3 … … O-Kn; each input port is connected with the S pole of the driving P-type MOS tube;
n (n-1) diodes, D1, D2, D3, D4, D5, D6 … … Dn (n-1) -1 and Dn (n-1); one driving unit is connected with 1 double-pole normally-open relay, and each driving unit is provided with (n-1) diode cathodes which are connected in parallel and connected with the G pole of a driving P-type MOS tube Q1 in an OR relationship;
d poles of the driving P-type MOS tubes are respectively connected with a common power supply input VCC;
a pair of dead points of the n double-pole normally open relays are simultaneously connected with positive and negative ends B + and B-of the common channel; the other pair of moving points of one double-pole normally-open relay is connected with a battery, the first double-pole normally-open relay is connected with batteries B1+ and B2+, the second double-pole normally-open relay is connected with batteries B2+ and B3+, and so on, the nth double-pole normally-open relay is connected with batteries Bn + and Bn-.
Due to the adoption of the technical scheme, the relay is not influenced by factors such as external voltage, the condition that the relays are simultaneously switched on due to abnormal driving can be completely avoided, and the cost is low.
Drawings
Fig. 1 is a circuit structure view of a conventional charge and discharge common channel.
Fig. 2 is a circuit diagram of the battery monitoring module of the present application for 3 segments of the number of batteries.
Fig. 3 is a circuit diagram of the battery monitoring module of the present application for a battery count of 5 segments.
FIG. 4 is a schematic diagram of the operation of BMM-S1022.
Detailed Description
The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings.
As shown in fig. 2, in the present application, the three battery packs in the above figure are taken as an example, and the controller, the 3 relay driving circuits, and the 3 battery packs are respectively arranged from left to right.
The main components of the drive circuit:
Figure BDA0002504070950000021
Figure BDA0002504070950000031
the output ports I-K1, I-K2 and I-K3 of the controller correspond to I-K1, I-K2 and I-K3 of 3 drive circuits respectively. The port numbers O-K1, O-K2 and O-K3 correspond to the input ports of coils of 3 relays K1, K2 and K3 respectively.
A pair of dead points of 3 double-pole normally open relays are simultaneously connected with positive and negative ends B + and B-of a common channel.
D1, D2, D3, D4, D5, and D6 are fast switching diodes, and the first driving unit is a column: d1, D2 two diode cathodes are connected in parallel and connected with G pole of Q1 in an OR relationship; similarly, the cathodes of two diodes D3 and D4 are connected in parallel and connected with the G pole of Q2 in an OR relationship; the cathodes of two diodes D5 and D6 are connected in parallel and are connected with the G pole of Q3 in an OR relationship.
Q1, Q2 and Q3 are driving P-type MOS of 3 relays respectively, and R1, R2 and R3 are driving isolation resistors of driving tubes respectively. This resistor has 2 functions: the preceding stage control chip and the MOS play a role in impedance matching; in addition, when D1 or D2 is conducted, the impact of the relay coil voltage on the IO port of the preceding stage control chip can be prevented.
K1, K2 and K3 are double-pole normally-open relays and are used for connecting or disconnecting corresponding batteries and a public maintenance channel;
VCC supplies power to the relay coil, and the voltage is matched with the rated voltage of the relay coil.
In actual operation, only one port of the controllers O-K1, O-K2 and O-K3 is in low level at the same time, namely only 1 of the 3 relays is in a conducting state at the same time. If the first relay is operated, the other two relays are not operated and are in an off state.
The interlocking principle of the circuit is realized as follows:
when Q1 is turned on, O-K1 is at high level, K1 is closed, and D3 and D5 connected with O-K1 make Vgs of Q2 and Q3 at high level, and according to the P-type MOS turn-on characteristic, Vgs of Q2 and Q3 is cut off due to positive bias, and K2 and K3 are not closed.
Similarly, when Q2 is turned on, Q1 and Q3 are clamped, and relays of K1 and K3 are in an off state; when Q3 is turned on, Q1 and Q2 are clamped, and relays of K1 and K2 are in an off state.
As can be seen from the above, when only one of the 3 relays is in the on state, the other two relays are always in the off state because the drive is clamped, thereby performing the interlocking function.
The circuit is used in a BMM-S1022 product of a battery pack monitoring module, as shown in FIG. 4, the voltage measurement of single batteries can be realized through the switching of a switch, the direct current discharge of a plurality of batteries is used for testing the internal resistance of the batteries, and the online discharge maintenance of each single battery can also be carried out.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention, including any reference to the above-mentioned embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art. The general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (1)

1. A multiplex relay interlock, comprising:
1) the controller comprises output ports I-K1, I-K2 and I-K3 … … I-Kn which respectively correspond to the n paths of relay interlocking circuits;
2) each relay interlocking circuit comprises a double-pole normally open relay, a quick switch diode, a driving P-type MOS tube and a driving isolation resistor;
the n driving isolation resistors are respectively R1, R2 and R3 … … Rn and are respectively connected with output ports I-K1, I-K2 and I-K3 … … I-Kn;
n drive P-type MOS tubes, Q1, Q2 and Q3 … … Qn;
n double-pole normally open relays are respectively K1, K2 and K3 … … Kn, and input ports are respectively O-K1, O-K2 and O-K3 … … O-Kn; each input port is connected with the S pole of the driving P-type MOS tube;
n (n-1) diodes, D1, D2, D3, D4, D5, D6 … … Dn (n-1) -1 and Dn (n-1); one driving unit is connected with 1 double-pole normally-open relay, and each driving unit is provided with (n-1) diode cathodes which are connected in parallel and connected with the G pole of a driving P-type MOS tube Q1 in an OR relationship;
d poles of the driving P-type MOS tubes are respectively connected with a common power supply input VCC;
a pair of dead points of the n double-pole normally open relays are simultaneously connected with positive and negative ends B + and B-of the common channel; the other pair of moving points of one double-pole normally-open relay is connected with a battery, the first double-pole normally-open relay is connected with batteries B1+ and B2+, the second double-pole normally-open relay is connected with batteries B2+ and B3+, and so on, and the nth double-pole normally-open relay is connected with batteries Bn + and Bn-;
when Q1 is turned on, O-K1 is at high level, K1 is closed, and D3 and D5 connected with O-K1 enable Vgs of Q2 and Q3 to be at high level, and according to the P-type MOS turn-on characteristic, Vgs of Q2 and Q3 is cut off due to positive bias, and K2 and K3 are not closed;
when the Q2 is switched on, the Q1 and the Q3 are clamped, and the relays of the K1 and the K3 are in an off state; when the Q3 is switched on, the Q1 and the Q2 are clamped, and the relays of the K1 and the K2 are in an off state;
when only one of the 3 relays is in a conducting state, the other two relays are always in a disconnected state because the driving is clamped, and therefore the interlocking effect is achieved.
CN202010441141.2A 2020-05-22 2020-05-22 Multi-path relay interlocking circuit and device Active CN111697643B (en)

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CN112614743B (en) * 2020-12-24 2024-03-08 通号万全信号设备有限公司 Non-gate control relay interlocking circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1747279A (en) * 2004-09-09 2006-03-15 范明亮 Structural plan of separated driven switch set
CN110758165A (en) * 2019-10-17 2020-02-07 广州市晨威电子科技有限公司 Output control circuit of charging pile
CN110993438A (en) * 2019-11-13 2020-04-10 上海空间电源研究所 Three-relay interlocking circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1747279A (en) * 2004-09-09 2006-03-15 范明亮 Structural plan of separated driven switch set
CN110758165A (en) * 2019-10-17 2020-02-07 广州市晨威电子科技有限公司 Output control circuit of charging pile
CN110993438A (en) * 2019-11-13 2020-04-10 上海空间电源研究所 Three-relay interlocking circuit

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