CN207780768U - The interface multiplexing circuit and QSFP modules of QSFP modules - Google Patents
The interface multiplexing circuit and QSFP modules of QSFP modules Download PDFInfo
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- CN207780768U CN207780768U CN201820141556.6U CN201820141556U CN207780768U CN 207780768 U CN207780768 U CN 207780768U CN 201820141556 U CN201820141556 U CN 201820141556U CN 207780768 U CN207780768 U CN 207780768U
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Abstract
The utility model provides a kind of interface multiplexing circuit and QSFP modules of QSFP modules, the wherein described QSFP modules include QSFP interfaces, the QSFP modules further include controller, the controller includes the first GPIO, the 2nd GPIO and C2 interfaces, and the interface multiplexing circuit includes the first single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT), first resistor, second resistance and 3rd resistor.The utility model passes through single-pole double-throw switch (SPDT), the remaining pin that can be used for logic control of QSFP interfaces is multiplexed, make QSFP interface compatibility QSFP standard interfaces, serial line interface and C2 interfaces, realize the extension of QSFP interface functions, very convenient QSFP modules are communicated by multiplex interface, firmware operation.
Description
Technical field
The utility model is related to interface circuit field, more particularly to a kind of QSFP (Quad Small Form-factor
(Small Form-factor Pluggables, kilomegabit electric signal are converted to connecing for optical signal by Pluggable, four-way SFP
Mouthpart part)) interface multiplexing circuit and QSFP modules of module.
Background technology
QSFP MSA Rev1.0 (i.e. QSFP multi-source agreement Rev1.0, QSFP multi-source agreements 1.0
Version) specified in more detail has been made to 38 pins of QSFP interfaces, power supply, signal ground, high-speed-differential are removed in this 38 pins
Signal wire, I2C interface, only surplus 5 control for Digital Logic, respectively LPMode (Low Power Mode, power consumption control
End, corresponding 31st pin), ResetL (Module Reset, module resets end, corresponding 9th pin), ModSelL (Module
Select, module select end, corresponding 8th pin), IntL (Interrupt, interrupt signal end, corresponding 28th pin),
ModPrsL (Module Present, module id end, corresponding 27th pin).It is internal to be mostly for QSFP 100G optical modules
Using 8051 microcontrollers as controller, it is frequently necessary to use serial ports in developing debugging process and C2 interfaces (is used for controller
Download emulation), both debugging interface circuits are typically designed on PCB (printed circuit board), can be led to when debugging early stage in this way
It crosses wire jumper (such as fly line or thimble) mode and connects external debugging device to realize serial communication, firmware emulation and upgrading.Due to production
The external QSFP interfaces of product simultaneously do not include both debugging interfaces, cause after optical module Product Assembly, the later stage is in optical module
Firmware when carrying out the operations such as exploitation debugging, edition upgrading, bring great inconvenience.
Utility model content
The technical problems to be solved in the utility model is to overcome in the prior art since QSFP interfaces are not used to adjust
The interface of examination causes QSFP modules in the exploitation very inconvenient defect during upgrading of firmware, provides a kind of connecing for QSFP modules
Mouth multiplex circuit and QSFP modules, it is real by the way that the remaining interface that can be used for logic control in QSFP interfaces to be multiplexed
The interface types such as the QSFP interface compatibility QSFP standard interfaces and C2 interfaces of existing QSFP modules.
The utility model is to solve above-mentioned technical problem by following technical proposals：
The utility model provides a kind of interface multiplexing circuit of QSFP modules, and the QSFP modules include QSFP interfaces,
Feature is that the QSFP modules further include controller, and the controller includes the first GPIO (GPIO：General Purpose
Input Output, universal input output pin), the 2nd GPIO and C2 interfaces, the interface multiplexing circuit include the first hilted broadsword
Commutator, the second single-pole double-throw switch (SPDT), first resistor, second resistance and 3rd resistor；
Module selection end, the module resets end of the QSFP interfaces pass through the first resistor, the second resistance respectively
It is connected to the power end of the controller；The module id end of the QSFP interfaces is connected to the control by the 3rd resistor
The signal ground of device processed；
The module selection end of the common end of first single-pole double-throw switch (SPDT) and the QSFP interfaces connect, normal-closed end and institute
State the first GPIO connections, normally open end is connect with the data terminal of the C2 interfaces, the module id of control terminal and the QSFP interfaces
End connection；
The common end of second single-pole double-throw switch (SPDT) connect with the module resets end of the QSFP interfaces, normal-closed end and institute
State the 2nd GPIO connections, normally open end is connect with the clock end of the C2 interfaces, the module id of control terminal and the QSFP interfaces
End connection；
When the level state at the module id end of the QSFP interfaces is low level, first single-pole double-throw switch (SPDT)
Common end, normal-closed end conducting, the common end of second single-pole double-throw switch (SPDT), normal-closed end conducting, the controller is for passing through
First GPIO and the 2nd GPIO receives the module selection logic level of the QSFP interfaces respectively and module resets are patrolled
Collect level；
When the level state at the module id end of the QSFP interfaces is high level, first single-pole double-throw switch (SPDT)
Common end, normally open end conducting, the common end of second single-pole double-throw switch (SPDT), normally open end conducting, the controller is for passing through
The C2 interfaces are communicated with external download emulator.
In the present solution, being connect by first single-pole double-throw switch (SPDT), second single-pole double-throw switch (SPDT) and the QSFP
The module of the QSFP interfaces is selected end (i.e. QSFP interfaces by the module id end (i.e. the ModPrsL pins of QSFP interfaces) of mouth
ModSelL pins), module resets end (i.e. the ResetL pins of QSFP interfaces) be connected to the different GPIO of the controller.
When due to QSFP standard traffics, the module id ends of the QSFP interfaces is low level, at this moment the module selection end of QSFP interfaces,
Module resets end has no effect on original QSFP after being pulled up by pull-up resistor (first resistor and the second resistance) and connects
Mouth function；In addition, only the module id end of the QSFP interfaces need to be set to high level in outside, so that it may by the QSFP
Module selection end, the module resets end of interface are multiplexed with the download emulation interface of the controller, i.e. C2 interfaces.Therefore, it only needs
Increase a small amount of components such as first single-pole double-throw switch (SPDT), second single-pole double-throw switch (SPDT), you can so that the QSFP connects
The compatible QSFP standard interfaces of mouth and C2 interfaces are not necessarily to open QSFP modules in this way, so that it may which the C2 interfaces come out by multiplexing are to institute
The firmware for stating controller carries out upgrading update and artificial debugging.
Preferably, the controller further includes the 3rd GPIO, the 4th GPIO, the 5th GPIO and the 6th GPIO, described first
The normal-closed end of single-pole double-throw switch (SPDT) is also connect with the 3rd GPIO, the normal-closed end of second single-pole double-throw switch (SPDT) also with it is described
4th GPIO connections；
The controller is additionally operable to the I by the 5th GPIO, the 6th GPIO and the QSFP interfaces2C interface
Communication connection, and external data is received, the external data includes com-state instruction or the instruction of QSFP standard state；
After receiving com-state instruction, the controller is by the first GPIO, the 2nd GPIO, described
3rd GPIO and the 4th GPIO is disposed as the OD outputs open-drain of GPIO (export), and close the first GPIO and
The input/output function of 2nd GPIO, and serial communication is carried out by the 3rd GPIO and the 4th GPIO；
After receiving QSFP standard state instruction, the controller by the first GPIO, the 2nd GPIO,
3rd GPIO and the 4th GPIO is disposed as OD outputs, and closes the serial communication, and passes through described first
GPIO and the 2nd GPIO receives the module selection logic level and module resets logic level of the QSFP interfaces respectively.
In the present solution, by the controller by the first GPIO, the 2nd GPIO, the 3rd GPIO and described
4th GPIO is disposed as OD outputs, this 4 GPIO can be into line and function, further according to I in this way2Include in C data connects
The input/output function of this 4 GPIO is arranged in mouthful status command, so that re-multiplexing goes out one on the basis of QSFP standard interfaces
A serial line interface, the controller described in this way can carry out serial communication by the serial line interface.
Preferably, the interface multiplexing circuit further includes the 4th resistance and the 5th resistance, the 5th GPIO passes through described
The I that 4th resistance, the 6th GPIO pass through the 5th resistance and the QSFP interfaces2C interface communicates to connect.
Preferably, the interface multiplexing circuit further includes the 6th resistance, the controller further includes the 7th GPIO, described
Seven GPIO are connect with the power consumption control end of the QSFP interfaces, and the power consumption control end of the QSFP interfaces passes through the 6th resistance
It is connected to the power end of the controller；
Preferably, the interface multiplexing circuit further includes the 7th resistance, the controller further includes the 8th GPIO, described
Eight GPIO are connect with the interrupt signal end of the QSFP interfaces, and the interrupt signal end of the QSFP interfaces passes through the 7th resistance
It is connected to the power end of the controller.
Preferably, the interface multiplexing circuit further includes analog switch, first single-pole double-throw switch (SPDT), second list
Double-pole double throw switch is integrated in the analog switch.Pass through the integrated electricity of the analog switch of preferred twin-channel single-pole double-throw switch (SPDT)
Road is further simplified circuit design.
Preferably, the controller includes 8051 microcontrollers.
The utility model also provides a kind of QSFP modules, its main feature is that, including QSFP modules described in any one of the above embodiments
Interface multiplexing circuit.
The positive effect of the utility model is：The utility model is remained QSFP interfaces by single-pole double-throw switch (SPDT)
The remaining pin (such as ResetL, ModSelL, ModPRSL) that can be used for logic control is multiplexed so that QSFP interface compatibilities
The multiple interfaces such as QSFP standard interfaces, serial line interface and C2 interfaces realize the extension of QSFP interface functions, facilitate QSFP modules
The exploitation of internal firmware and updating operation.
Description of the drawings
Fig. 1 is the interface multiplexing circuit of the QSFP modules of the utility model preferred embodiment and the circuit diagram of QSFP modules.
Specific implementation mode
The utility model is further illustrated below by the mode of embodiment, but is not therefore limited in the utility model
Among the embodiment described range.
As shown in Figure 1, the interface multiplexing circuit for the QSFP modules that the present embodiment is related to, the QSFP modules include that QSFP connects
Mouth J1, the QSFP modules further include controller U1, and controller U1 includes the first GPIO, the 2nd GPIO and C2 interfaces；Specific
When implementation, controller U1 preferably 8051 microcontrollers, the microcontroller is efm8lb12f series, wherein the first GPIO, the 2nd GPIO phases
The P0.0 and P0.4 of controller U1 are should be, the data terminal of C2 interfaces, clock end are respectively P3.7/C2D, RST/ of controller U1
C2CK；
The interface multiplexing circuit includes the first single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT), first resistor R1, second
Resistance R2 and 3rd resistor R3；In the specific implementation, it to improve circuit level, can be opened by preferably integrated two-way single-pole double throw
The analog switch U2 of pass, model specification SGM2268, the first single-pole double-throw switch (SPDT) described in this way and second single-pole double throw are opened
Close just be respectively the analog switch the first via and the second tunnel, wherein the common end of first single-pole double-throw switch (SPDT), normal-closed end,
Normally open end mutually should be COM1, NC1, NO1 and IN1 of analog switch U2 with control terminal；Second single-pole double-throw switch (SPDT) it is public
End, normal-closed end, normally open end and control terminal mutually should be COM2, NC2, NO2 and IN2 of analog switch U2；The power supply of analog switch U2
End V+ is connected to the power end VDD of controller U1, signal ground GND is connected to the reference ground DGND of QSFP modules, wherein controller
The power supply being adapted with QSFP interfaces J1 can be used in the power end VDD of U1, is used uniformly 3.3V power supplys here and is powered.
Module selection end ModSelL, the module resets end ResetL of QSFP interfaces J1 passes through first resistor R1, second respectively
Resistance R2 is connected to the power end VDD of controller U1, this egf block selection end ModSelL, module resets end ResetL are pulled up
To 3.3V；The module id end ModPrsL of QSFP interfaces J1 is connected to the signal ground EPAD of controller U1 by 3rd resistor R3,
Here the signal ground EPAD of controller U1 is connected to the reference ground DGND of QSFP modules, such module id end ModPrsL drop-downs
To reference ground DGND；
The module selection end ModSelL of the common end COM1 of first single-pole double-throw switch (SPDT) and QSFP interfaces J1 connect,
Normal-closed end NC1 is connect with the first GPIO, normally open end NO1 is connect with the data terminal of the C2 interfaces, control terminal IN1 and QSFP
The module id end ModPrsL connections of interface J1；The common end COM2's and QSFP interfaces J1 of second single-pole double-throw switch (SPDT)
The ResetL connections of module resets end, normal-closed end NC2 connect with the 2nd GPIO, the clock of normally open end NO2 and the C2 interfaces
End connection, control terminal IN2 are connect with the module id end ModPrsL of QSFP interfaces J1, the first single-pole double-throw switch (SPDT) described in this way,
Second single-pole double-throw switch (SPDT) is controlled by the module id end ModPrsL of QSFP interfaces J1：QSFP interfaces J1's
When the level state of module id end ModPrsL is low level, common end COM1, the normal-closed end of first single-pole double-throw switch (SPDT)
NC1 is connected, the common end COM2 of second single-pole double-throw switch (SPDT), normal-closed end NC2 conductings, and at this moment controller U1 is just used to pass through
First GPIO and the 2nd GPIO receives the module selection logic level and module resets logic of QSFP interfaces J1 respectively
The level of level, i.e., described first GPIO and the 2nd GPIO meets QSFP standard interface requirements；
When the level state of the module id end ModPrsL of QSFP interfaces J1 is high level, first single-pole double throw
Common end COM1, the normally open end NO1 of switch are connected, and common end COM2, the normally open end NO2 of second single-pole double-throw switch (SPDT) are led
Logical, at this moment controller U1 is just used to communicate with external download emulator by the C2 interfaces, in this way by downloading emulation
Device, which is connected in the cable of QSFP interfaces J1, draws high the module id end ModPrsL of QSFP interfaces J1 for high level, can be from
The C2 interfaces are multiplexed out in QSFP interfaces J1, so as to directly by the C2 interfaces, easily to controller U1 into
Row firmware development, debugging, emulation and upgrading.
By increasing two-way single-pole double-throw switch (SPDT), and the level shape of the module id end ModPrsL using QSFP interfaces J1
The module of QSFP interfaces J1 can be selected end ModSelL, module resets end ResetL to be multiplexed, make QSFP interfaces J1 by state
Compatible QSFP standard interfaces and C2 interfaces.
In the present embodiment, serial communication, the also QSFP in QSFP interfaces J1 are carried out with external for ease of the QSFP modules
Serial line interface is multiplexed out in standard interface.Specifically, controller U1 further includes the 3rd GPIO, the 4th GPIO, the 5th GPIO and
Six GPIO, wherein corresponding P0.1, P0.5, the P2.0 of device U1 in order to control of the 3rd GPIO, the 4th GPIO, the 5th GPIO and the 6th GPIO
And P2.1, the normal-closed end NC1 of first single-pole double-throw switch (SPDT) are also connect with the 3rd GPIO, second single-pole double throw is opened
The normal-closed end NC2 of pass is also connect with the 4th GPIO；
Controller U1 is additionally operable to the I by the 5th GPIO, the 6th GPIO and QSFP interfaces J12C interface (clock
Signal end SCL, data terminal SDA) it communicates to connect, the 5th GPIO described herein also passes through the 4th resistance R4 connection QSFP interfaces J1
I2The clock end SCL, the 6th GPIO of C interface also pass through the I of the 5th resistance R5 connection QSFP interfaces J12The data of C interface
Hold SDA, such controller U1 that can pass through I2C communicates to receive external data, and the external data includes com-state instruction
Or QSFP standard state instruction；
After receiving com-state instruction, controller U1 is just by the first GPIO, the 2nd GPIO, described
3rd GPIO and the 4th GPIO is disposed as OD outputs, and the input for closing the first GPIO and the 2nd GPIO is defeated
Go out function, and serial communication is carried out by the 3rd GPIO and the 4th GPIO；And works as and receive the QSFP standards
After status command, the first GPIO, the 2nd GPIO, the 3rd GPIO and the 4th GPIO are all provided with by controller U1
OD outputs are set to, and close the serial communication, and described in being received respectively by the first GPIO and the 2nd GPIO
The module selection logic level and module resets logic level of QSFP interfaces.Since the OD for the GPIO that controller U1 is utilized is defeated
Go out, so can then pass through I in the enterprising lines of these GPIO and logic2C interface sends out Interface status instruction to controller U1,
Controller U1 so just configures corresponding GPIO according to instruction so that the state of QSFP standard interfaces and serial line interface will not be same
When exist, and then select end ModSelL in the module of identical QSFP interfaces J1, realize that difference connects on the ResetL of module resets end
Mouth function, makes the compatible QSFP standard interfaces of QSFP interfaces J1, C2 interfaces and serial line interface in this way.
Come into line and logic by using the OD outputs of the GPIO of controller U1, end is selected in the module of QSFP interfaces J1
It is multiplexed out QSFP standard interfaces, C2 interfaces and serial line interface on ModSelL, module resets end ResetL, so no longer being needed on PCB
The contact pin and solder joint that additionally reserve serial line interface and C2 interfaces can save more PCB space, and in debugging and follow-up dimension
Shield also no longer needs to borrow fly line and thimble, need not also dismantle the QSFP modules shell can carry out the exploitation of firmware,
Debugging, emulation and upgrading, QSFP standard interfaces, serial line interface, C2 interfaces can arbitrarily, be switched fast, considerably increase convenience,
Effectively reduce the time cost of exploitation debugging.
In the present embodiment, the interface multiplexing circuit further includes the 6th resistance R6, and controller U1 further includes the 7th GPIO, institute
It states the 7th GPIO to connect with the power consumption control end LPMode of QSFP interfaces J1, the power consumption control end LPMode of QSFP interfaces J1 passes through
6th resistance R6 is connected to the power end VDD of controller U1, and the 7th GPIO described here corresponds to the P3.0 of controller U1, passes through
The power consumption control end LPMode of QSFP interfaces J1 is pulled to 3.3V by the 6th resistance R6, it can be ensured that the 7th GPIO meets QSFP
Logic level requirement, at this moment the 7th GPIO receive the level of external setting, the QSFP modules can be allowed according to the electricity
It puts down to be operated in different power consumption pattern (low-power consumption mode or normal mode of operation).
Equally, the interface multiplexing circuit further includes the 7th resistance R7, and controller U1 further includes the 8th GPIO, and the described 8th
GPIO is connect with the interrupt signal end IntL of QSFP interfaces J1, and the interrupt signal end IntL of QSFP interfaces J1 passes through the 7th resistance R7
The power end VDD, the 8th GPIO described here for being connected to controller U1 correspond to the P0.2 of controller U1, pass through the 7th resistance R7
The interrupt signal end IntL of QSFP interfaces J1 is pulled to 3.3V, it can be ensured that the logic level that the 8th GPIO meets QSFP is wanted
It asks.
As shown in Figure 1, the present embodiment also provides a kind of QSFP modules, the QSFP modules include the interface clothes above-mentioned
Be illustrative simplicity with circuit, the QSFP interface J1 in figure, illustrate only can digital logic control 5 signal ends and I2C interface
Totally 7 terminals are held, do not show that remaining 31 terminal in QSFP interfaces J1, but have no effect on those skilled in the art according to this
Utility model is designed.
Although the foregoing describe specific embodiment of the present utility model, it will be appreciated by those of skill in the art that
This is merely illustrative of, and the scope of protection of the utility model is defined by the appended claims.Those skilled in the art
Under the premise of without departing substantially from the principles of the present invention and essence, many changes and modifications may be made,
But these change and modification each fall within the scope of protection of the utility model.
Claims (8)
1. a kind of interface multiplexing circuit of QSFP modules, the QSFP modules include QSFP interfaces, which is characterized in that the QSFP
Module further includes controller, and the controller includes the first GPIO, the 2nd GPIO and C2 interfaces, and the interface multiplexing circuit includes
First single-pole double-throw switch (SPDT), the second single-pole double-throw switch (SPDT), first resistor, second resistance and 3rd resistor；
Module selection end, the module resets end of the QSFP interfaces are connected by the first resistor, the second resistance respectively
To the power end of the controller；The module id end of the QSFP interfaces is connected to the controller by the 3rd resistor
Signal ground；
The module selection end of the common end of first single-pole double-throw switch (SPDT) and the QSFP interfaces connect, normal-closed end and described the
One GPIO connections, normally open end are connect with the data terminal of the C2 interfaces, control terminal and the module id end of the QSFP interfaces connect
It connects；
The common end of second single-pole double-throw switch (SPDT) connect with the module resets end of the QSFP interfaces, normal-closed end and described the
Two GPIO connections, normally open end are connect with the clock end of the C2 interfaces, control terminal and the module id end of the QSFP interfaces connect
It connects；
The module id end of the QSFP interfaces level state be low level when, first single-pole double-throw switch (SPDT) it is public
End, normal-closed end conducting, the common end of second single-pole double-throw switch (SPDT), normal-closed end conducting, the controller are used for by described
First GPIO and the 2nd GPIO receives the module selection logic level and module resets logic electricity of the QSFP interfaces respectively
It is flat；
The module id end of the QSFP interfaces level state be high level when, first single-pole double-throw switch (SPDT) it is public
End, normally open end conducting, the common end of second single-pole double-throw switch (SPDT), normally open end conducting, the controller are used for by described
C2 interfaces are communicated with external download emulator.
2. the interface multiplexing circuit of QSFP modules as described in claim 1, which is characterized in that the controller further includes third
GPIO, the 4th GPIO, the 5th GPIO and the 6th GPIO；
The normal-closed end of first single-pole double-throw switch (SPDT) is also connect with the 3rd GPIO；
The normal-closed end of second single-pole double-throw switch (SPDT) is also connect with the 4th GPIO；
The controller is additionally operable to the I by the 5th GPIO, the 6th GPIO and the QSFP interfaces2C interface communication link
It connects, and receives external data, the external data includes com-state instruction or the instruction of QSFP standard state；
After receiving com-state instruction, the controller is by the first GPIO, the 2nd GPIO, the third
GPIO and the 4th GPIO is disposed as OD outputs, and closes the input and output work(of the first GPIO and the 2nd GPIO
Can, and serial communication is carried out by the 3rd GPIO and the 4th GPIO；
After receiving QSFP standard state instruction, the controller is by the first GPIO, the 2nd GPIO, described
3rd GPIO and the 4th GPIO is disposed as OD outputs, and closes the serial communication, and passes through the first GPIO
Receive the module selection logic level and module resets logic level of the QSFP interfaces respectively with the 2nd GPIO.
3. the interface multiplexing circuit of QSFP modules as claimed in claim 2, which is characterized in that the interface multiplexing circuit also wraps
The 4th resistance and the 5th resistance are included, the 5th GPIO passes through the 5th electricity by the 4th resistance, the 6th GPIO
The I of resistance and the QSFP interfaces2C interface communicates to connect.
4. the interface multiplexing circuit of QSFP modules as described in claim 1, which is characterized in that the interface multiplexing circuit also wraps
The 6th resistance is included, the controller further includes the 7th GPIO, and the power consumption control end of the 7th GPIO and the QSFP interfaces connect
It connects, the power consumption control end of the QSFP interfaces is connected to the power end of the controller by the 6th resistance.
5. the interface multiplexing circuit of QSFP modules as described in claim 1, which is characterized in that the interface multiplexing circuit also wraps
The 7th resistance is included, the controller further includes the 8th GPIO, and the interrupt signal end of the 8th GPIO and the QSFP interfaces connect
It connects, the interrupt signal end of the QSFP interfaces is connected to the power end of the controller by the 7th resistance.
6. the interface multiplexing circuit of QSFP modules as described in claim 1, which is characterized in that the interface multiplexing circuit also wraps
Analog switch is included, first single-pole double-throw switch (SPDT), second single-pole double-throw switch (SPDT) are integrated in the analog switch.
7. the interface multiplexing circuit of QSFP modules as described in claim 1, which is characterized in that the controller includes 8051 single
Piece machine.
8. a kind of QSFP modules, which is characterized in that include the interface of the QSFP modules as described in any one of claim 1 to 7
Multiplex circuit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109116484A (en) * | 2018-10-31 | 2019-01-01 | 深圳市亚派光电器件有限公司 | Golden finger multiplex circuit and optical module |
| CN111367203A (en) * | 2018-12-26 | 2020-07-03 | 圣邦微电子（北京）股份有限公司 | Control chip, driving chip and communication interface multiplexing method |
| CN113258993A (en) * | 2021-07-14 | 2021-08-13 | 深圳市迅特通信技术股份有限公司 | Communication interface circuit and control device of PAM4 optical module |
-
2018
- 2018-01-26 CN CN201820141556.6U patent/CN207780768U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109116484A (en) * | 2018-10-31 | 2019-01-01 | 深圳市亚派光电器件有限公司 | Golden finger multiplex circuit and optical module |
| CN109116484B (en) * | 2018-10-31 | 2024-04-19 | 深圳市亚派光电器件有限公司 | Golden finger multiplexing circuit and optical module |
| CN111367203A (en) * | 2018-12-26 | 2020-07-03 | 圣邦微电子（北京）股份有限公司 | Control chip, driving chip and communication interface multiplexing method |
| CN111367203B (en) * | 2018-12-26 | 2021-12-28 | 圣邦微电子（北京）股份有限公司 | Control chip, driving chip and communication interface multiplexing method |
| CN113258993A (en) * | 2021-07-14 | 2021-08-13 | 深圳市迅特通信技术股份有限公司 | Communication interface circuit and control device of PAM4 optical module |
| CN113258993B (en) * | 2021-07-14 | 2021-11-19 | 深圳市迅特通信技术股份有限公司 | Communication interface circuit and control device of PAM4 optical module |
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Effective date of registration: 20200415 Address after: 201100 floor 5, building 8, No. 2388, Chenhang Road, Minhang District, Shanghai Patentee after: CIG SHANGHAI Co.,Ltd. Address before: 201114 room 8, building 2388, 501 Chen Cheng Road, Shanghai, Minhang District Co-patentee before: ZHEJIANG JIANQIAO ELECTRONIC TECHNOLOGY Co.,Ltd. Patentee before: CIG SHANGHAI Co.,Ltd. |