CN207719197U - A kind of HSIP14 encapsulating leads - Google Patents
A kind of HSIP14 encapsulating leads Download PDFInfo
- Publication number
- CN207719197U CN207719197U CN201721794070.4U CN201721794070U CN207719197U CN 207719197 U CN207719197 U CN 207719197U CN 201721794070 U CN201721794070 U CN 201721794070U CN 207719197 U CN207719197 U CN 207719197U
- Authority
- CN
- China
- Prior art keywords
- chip
- dao
- pin
- balanced circuit
- hsip14
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
The utility model provides a kind of HSIP14 encapsulating leads,Its encapsulation is identical with the encapsulation of the HSIP14 of standard,It can be widely used,It is integrated with multiple chip devices with a chip package,Reduce aerial lug in application,Improve the stability of performance,Reduce manufacturing cost,Including frame,The center of frame is provided with center Ji Dao,Center Ji Dao is equipped with chip DS4440,Pin one is centrally located the surrounding of Ji Dao to pin 14,Chip DS4440 is equipped with pad,Pad and pin two are connected between pin 13 by lead,Frame is equipped with the second Ji Dao and third Ji Dao,Second Ji Dao and third Ji Dao is equipped with balanced circuit chip,One balanced circuit chip connects pin one and chip DS4440 by lead,Another balanced circuit chip connects pin 14 and chip DS4440 by lead,It is connected by lead between two balanced circuit chips.
Description
Technical field
The utility model is related to the technical field of semiconductor packages, specially a kind of HSIP14 encapsulating leads.
Background technology
The lead frame of the HSIP14 encapsulation patterns of standard is the islands Dan Ji, and there are one cores for the center placement of Ji Dao
Along with the continuous complication of product, the add ons combined still are connected in application for the perfect needs of function for piece,
It is connected again by outside lead, such setting is so that stability is poor；And due to the use of multiple packagings, make
The chip package volume of product is big, and increases cost, design can be related to if redesigning encapsulating lead, producing line changes
Make the cost problem brought.
Utility model content
In view of the above-mentioned problems, the utility model provides a kind of HSIP14 encapsulating leads, encapsulation and standard
The encapsulation of HSIP14 is identical, can be widely used, and multiple chip devices are integrated with a chip package, subtracts in application
Lack aerial lug, improved the stability of performance, reduced the usage quantity of device, reduces manufacturing cost, and adapted to mesh
The growth requirement of preceding electronics industry miniaturization, micromation.
Its technical solution is such：A kind of HSIP14 encapsulating leads, including frame, the center of the frame
It is provided with center Ji Dao, the center Ji Dao is equipped with chip DS4440, and pin one to pin 14 is distributed in the center base
The surrounding on island, the chip DS4440 are equipped with pad, and the pad and pin two are connected between pin 13 by lead,
It is characterized in that：The frame is equipped on the second Ji Dao and third Ji Dao, second Ji Dao and the third Ji Dao respectively
Equipped with balanced circuit chip, one of balanced circuit chip connects pin one and the chip DS4440 by lead, another
A balanced circuit chip connects pin 14 and the chip DS4440 by lead, two balanced circuit chips it
Between connected by lead.
Further, second Ji Dao and the third Ji Dao are separately positioned on pin one and pin 14.
Further, the balanced circuit chip is 7133 chips.
Further, the balanced circuit chip is 6206A33 chips.
Further, the balanced circuit chip is the transistor circuit chip to match with the chip DS4440.
Further, the lead is gold thread.
Further, the chip DS4440 and the balanced circuit chip are divided in plastic packaging layer.
The HSIP14 encapsulating leads of the utility model have it is following a little：It is constant in overall appearance and outer pin spacing
In the case of, idle pin in the original encapsulation utilized will be combined with the related balanced circuit chips of chip DS4440
It is encapsulated in a plastic-sealed body, has saved packaging cost, the high-performance and high reliability of electronic system are realized, particularly suitable for vapour
The occasion of vehicle acoustic electronic system requirements harshness；Production cost is low, the market dispensing period is short, and each function module can be set respectively in advance
Meter, and the existing general integrated chip in market and module can be largely used, significantly reduce cost, the design cycle shortens, throwing
It is very fast to put market；Function admirable, reliability is high, which reduces the connection between each functional component so that due to even
Various losses between connecing, interference such as are reduced to minimum, while fully utilizing microelectronics, solid electronic at the multinomial technology,
Polytechnic advantage is given full play to.To improve the comprehensive performance of system.
Description of the drawings
Fig. 1 is the schematic diagram of the HSIP14 encapsulating leads of the utility model.
Specific implementation mode
See that Fig. 1, a kind of HSIP14 encapsulating leads of the utility model, including frame 1, the centre bit of frame 1 install
It is equipped with center base island 2, center base island 2 is equipped with chip 3, model DS4440, pin 1, pin 2 402, pin three
403 are centrally located the surrounding of Ji Dao to pin 14, and chip 3 is equipped with pad 4, pad 4 and pin 2 402 to pin
It is connected by lead 5 between 13, frame 1 is equipped with the second Ji Dao and third Ji Dao, the second Ji Dao and third Ji Dao difference
It is arranged on pin 1 and pin 14, balanced circuit chip 61,62 is respectively equipped on the second Ji Dao and third Ji Dao,
One of balanced circuit chip 61 connects pin 1 by lead 5 and chip 3, another balanced circuit chip 62 pass through
Lead 5 connects pin 14 and chip 3, is connected by lead 4 between two balanced circuit chips 61,62, regulator circuit core
Piece uses 7133 chips, 6206A33 chips or the transistor circuit chip to match with chip DS4440, in the present embodiment
Lead is gold thread, and chip DS4440 and balanced circuit chip are in plastic packaging layer.
The HSIP14 encapsulating leads of the utility model, are transformed former frame structure, are utilized in untouched dress
Idle pin one and pin 14, three islands Ge Ji, the entire length and width of frame are changed to by an intrinsic base island structure
Spend constant, outer pin spacing is constant, and multiple chips are encapsulated in a frame, have saved packaging cost, realize electronic system
High-performance and high reliability require harsh occasion particularly suitable for electronic system；Production cost is low, the market dispensing period is short,
Each function module can separately design in advance, and can largely use the existing general integrated chip in market and module, be effectively reduced
Cost, design cycle shorten, and launch very fast；Function admirable, reliability is high, which reduces each functional component
Between connection so that since various losses, the interference between connection are reduced to minimum, while fully utilizing microelectronics, solid
The multinomial technology such as body electronics, has given full play to polytechnic advantage.To improve the comprehensive performance of system.
More than, the only preferable specific implementation mode of the utility model, but the scope of protection of the utility model is not limited to
In this, any people for being familiar with the technology is in the technical scope disclosed by the utility model, the change or replacement that can be readily occurred in,
It should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model should be with claim
Subject to protection domain.
Claims (7)
1. the center of a kind of HSIP14 encapsulating leads, including frame, the frame is provided with center Ji Dao, in described
The islands Xin Ji are equipped with chip DS4440, and pin one to pin 14 is distributed in the surrounding of the center Ji Dao, the chip
DS4440 is equipped with pad, and the pad and pin two are connected between pin 13 by lead, it is characterised in that：The frame
Frame is equipped on the second Ji Dao and third Ji Dao, second Ji Dao and the third Ji Dao and is respectively equipped with balanced circuit chip,
One of balanced circuit chip connects pin one and the chip DS4440, another described balanced circuit chip by lead
Pin 14 and the chip DS4440 are connected by lead, is connected by lead between two balanced circuit chips.
2. a kind of HSIP14 encapsulating leads according to claim 1, it is characterised in that：Second Ji Dao and described
Third Ji Dao is separately positioned on pin one and pin 14.
3. a kind of HSIP14 encapsulating leads according to claim 1, it is characterised in that：The balanced circuit chip is
7133 chips.
4. a kind of HSIP14 encapsulating leads according to claim 1, it is characterised in that：The balanced circuit chip is
6206A33 chips.
5. a kind of HSIP14 encapsulating leads according to claim 1, it is characterised in that：The balanced circuit chip is
The transistor circuit chip to match with the chip DS4440.
6. a kind of HSIP14 encapsulating leads according to claim 1, it is characterised in that：The lead is gold thread.
7. a kind of HSIP14 encapsulating leads according to claim 1, it is characterised in that：The chip DS4440 and institute
Balanced circuit chip is stated to be divided in plastic packaging layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721794070.4U CN207719197U (en) | 2017-12-20 | 2017-12-20 | A kind of HSIP14 encapsulating leads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721794070.4U CN207719197U (en) | 2017-12-20 | 2017-12-20 | A kind of HSIP14 encapsulating leads |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207719197U true CN207719197U (en) | 2018-08-10 |
Family
ID=63056815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721794070.4U Active CN207719197U (en) | 2017-12-20 | 2017-12-20 | A kind of HSIP14 encapsulating leads |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207719197U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010900A (en) * | 2017-12-20 | 2018-05-08 | 无锡红光微电子股份有限公司 | A kind of HSIP14 encapsulating leads |
-
2017
- 2017-12-20 CN CN201721794070.4U patent/CN207719197U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010900A (en) * | 2017-12-20 | 2018-05-08 | 无锡红光微电子股份有限公司 | A kind of HSIP14 encapsulating leads |
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