CN207689628U

CN207689628U - Modularization chip encapsulation assembly tests system

Info

Publication number: CN207689628U
Application number: CN201720863304.XU
Authority: CN
Inventors: M·H·马尔迪
Original assignee: Xilinx Inc
Current assignee: Xilinx Inc
Priority date: 2016-07-18
Filing date: 2017-07-17
Publication date: 2018-08-03
Anticipated expiration: 2027-07-17

Abstract

The utility model provides a kind of modularization chip encapsulation assembly test system.In one example, the test system includes the robot of setting in the shell, has a motion range, operable to transmit chip encapsulation assembly between first queue platform, second queue platform and multiple testboards.It is operable to read the identification label being adhered on the barrow being set in the first and second queues platform the system also includes automatic identification and data capture (AIDC) equipment；And controller, it is configured in response to from the information obtained in the predefined test program for being coupled to the test processor of the identification label being arranged on the barrow of at least one of the first and second queues platform, the predefined test program of the test processor of first testboard and the secondary test board is read, the placement of the chip encapsulation assembly is controlled by the robot.

Description

Modularization chip encapsulation assembly tests system

Technical field

The embodiment of the present invention is usually related to the modular test system with multi-function robot, and in particular to has The modularization chip encapsulation assembly of multi-function robot tests system.

Background technology

Such as tablet computer, computer, duplicator, digital camera, smart phone, control system and ATM etc. are electric Sub- equipment generally use electronic unit, the electronic unit obtain increased function and higher component using chip encapsulation assembly Density.As chip encapsulation assembly becomes much larger more complicated, the test of chip encapsulation assembly becomes more time-consuming and difficult, this is not Unit manufacturing cost is increased sharply.It simply makes larger and more complex test equipment and is not an ideal solution party Case, because of the high capital cost of equipment needs that the floor space of typical manufacturing facility is very big and larger and more complicated.

Therefore, it is necessary to a kind of improved test systems being suitable for test chip package assembling in production environment.

Utility model content

There is provided herein the modularization chip encapsulation assemblies for test chip package assembling to test system and method.One In a example, the test system includes the robot of setting in the shell, has a motion range, operable to be arranged Chip encapsulation assembly is transmitted between arbitrary first queue platform in the housing, second queue platform and multiple testboards.Institute The system of stating further includes automatic identification and data capture (AIDC) equipment, and operable be adhered to reading is set to first He Identification label on barrow during both second queue platforms are any and controller exist in response to being coupled to setting from reading The test processes of identification label, first testboard on the barrow of at least one of the first and second queues platform The information obtained in the scheduled test program of the scheduled test program of device and the test processor of the secondary test board is led to The robot is crossed to control the placement of the chip encapsulation assembly.

In another example, chip encapsulation assembly test system includes the robot of setting in the shell, has a fortune Dynamic range transmits core between operable arbitrary first queue platform, second queue platform and multiple testboards in the housing Piece package assembling.The system also includes the automatic identifications for being coupled to the robot and data capture (AIDC) equipment, can Operation is to read the identification label on the barrow for being adhered to and being set in the first and second queues platform.Provide control Device is configured to respond to be coupled to the barrow being arranged at least one of the first and second queues platform from reading On identification label, first testboard test processor scheduled test program, the secondary test board test The scheduled test program of processor and the information obtained from the test data that the testboard obtains, pass through the machine Device people controls the placement of the chip encapsulation assembly.

In another example, a kind of method for test chip package assembling is provided comprising：In modularization chip Setting includes the first barrow of the first multi-chip package component for test in the shell of encapsulation component test system, uses The automatic identification and data capture (AIDC) equipment for being coupled to robot determine the chip package group being arranged in the first barrow The type of part, setting includes the second multi-chip package for test in the shell that modularization chip encapsulation assembly tests system Second barrow of component determines the type for the chip encapsulation assembly being arranged in the second barrow using AIDC equipment, and Type based on the chip encapsulation assembly and the test program that will be executed in each testboard will be arranged described first First chip encapsulation assembly of the first multi-chip package component in barrow is transmitted to the first testboard or the second test Platform.

In another example, IC test systems are provided comprising robot, input rank platform are configured as receiving Multiple chip encapsulation assemblies for being tested in IC test systems, output queue platform are configured as receiving and be surveyed in the IC The chip encapsulation assembly and testboard for the multi-chip package component tested in test system.The testboard includes the One test interface and the second test interface.First test interface can be configured to receive and communicatedly connection has a kind of soldered ball Connect the first chip encapsulation assembly of arrangement.Second test interface can be configured to receive and communicatedly connection has different welderings Second chip encapsulation assembly of ball connection arrangement.The testboard further includes the first test processor, is configured as by making The chip encapsulation assembly connected by first interface is tested with scheduled first test program；And second test processor, It is configured as testing the chip encapsulation assembly connected by second interface by using scheduled second test program.

In another example, a kind of method for test chip package assembling is provided.This method includes：It will be used to survey First chip encapsulation assembly of examination is sent to the first test interface of the testboard of chip encapsulation assembly test system；It is pre- first Determine to test first chip encapsulation assembly with the first predefined test program at temperature；It will be sealed for the second chip of test Arrangement is sent to the second test interface of the testboard of the chip encapsulation assembly test system, wherein the first and second chips Package assembling is different type；And second chip encapsulation assembly is tested using the second scheduled test program, wherein It tests first and second chip encapsulation assembly while occurring.

Description of the drawings

In order to which the mode of features described above of the invention is understood in detail, can short summary be come by reference to embodiment The more specific description of aforementioned present invention, some of them are shown in the accompanying drawings.It should be noted, however, that attached drawing illustrates only this hair Bright exemplary embodiments, therefore its range is should not be considered as limiting, because the present invention can allow other equally effective reality Apply example.

Fig. 1 is the schematic plan of chip encapsulation assembly test system.

Fig. 2 is the schematic side elevation of a part for the chip encapsulation assembly test system of Fig. 1, shows showing for queue platform Example.

Fig. 3 is the schematic side elevation of a part for the chip encapsulation assembly test system of Fig. 1, shows the another of queue platform One example.

Fig. 4 A-4F are the schematic side elevations of testboard, are shown as the testboard transmits chip encapsulation assembly One example of sequence.

Fig. 5 is the schematic side elevation of a part for testboard, is shown for chip encapsulation assembly to be placed in test Pusher in the interface of platform.

Fig. 6 is the schematic plan of another chip encapsulation assembly test system.

Fig. 7 is the flow chart for the method for test chip package assembling in chip encapsulation assembly test system.

Fig. 8 is the schematic plan of chip encapsulation assembly test system.

Fig. 9 is the schematic side elevation of a part for the chip encapsulation assembly test system of Fig. 8, shows showing for testboard Example.

Figure 10 is the schematic plan of another chip encapsulation assembly test system.

Figure 11 A-B are in chip encapsulation assembly test system while the method for testing different chip encapsulation assemblies Flow chart.

In order to make it easy to understand, in the conceived case, making to be denoted by the same reference numerals identical member common in figure Part.It is contemplated that the element of one embodiment can be beneficially incorporated in other embodiments.

Specific implementation mode

Compared with legacy test system, the chip encapsulation assembly disclosed herein for test chip package assembling tests system System and method improve test handling capacity, without increasing space requirement.In addition, chip encapsulation assembly test system is flexible , because test system can be configured as while the test chip package assembling of test different types.The chip encapsulation assembly Test system can be additionally configured to classify to the chip encapsulation assembly of test, more effectively to handle.In addition, the core The modularization of piece encapsulation component test system allows to add additional queue or testboard, so as to limited additional paid-in capital The downtime that expenditure or system reconfigure meets the variation of production requirement.

In other examples, chip encapsulation assembly test system disclosed herein and the side for test chip package assembling Method improves test handling capacity by allowing the test chip package assembling of test different types simultaneously.The chip package assembling Test system can also run different tests at a temperature of hot and cold, to allow more effectively test.In addition, the chip The modularization of encapsulation component test system allows to add additional queue or testboard, so as to limited additional paid-in capital branch Go out or downtime that system reconfigures meets the variation of production requirement.

Illustrative chip encapsulation assembly, such as ball grid array (BGA) encapsulation, generally include to be arranged on the package substrate At least one or more integrated circuit (IC) bare die.In some embodiments, middle layer can be used for providing two or more naked Improved interconnection between piece and/or between bare die and package substrate.IC chip can be programmable logic device, such as scene Programmable gate array (FPGA), memory device, optical device, MEMS device, processor or other IC logics or memory construction. Optical devices include photoelectric detector, laser, light source etc..The function of IC bare dies is carried by the solid-state circuit formed in bare die For.At the end of chip package assembling manufacture process, chip encapsulation assembly is tested, to ensure robust and predictable property Energy.

Fig. 1 is the schematic plan of the chip encapsulation assembly test system 100 suitable for chip encapsulation assembly 126.Mould Block chip encapsulation assembly test system 100 generally includes the shell 102 with interior zone 104.At least first queue platform 114, multiple testboards, robot 150 and automatic identification and data capture (AIDC) equipment 160 are arranged in shell 102 In portion region 104.Robot 150 has motion range, operable with the appointing in test system 100 by chip encapsulation assembly 126 It is transmitted between meaning queue and testboard.

It further includes controller 170 that modularization chip encapsulation assembly, which tests system 100, is used to control chip encapsulation assembly survey The operation of test system 100, including robot 150 operation and the processing information that is read by AIDC equipment 160.Controller 170 1 As include for control chip encapsulation assembly test system 100 operation central processing unit (CPU), memory and support Circuit.The CPU can be any type of general-purpose computer processor that can be used in industrial environment.Software program or Sequence of program instructions is stored in the memory, such as random access memory, read-only memory, floppy disk or hard drive The digital storage of device or other forms.The support circuits are usually coupled to CPU, and may include cache, clock Circuit, input/output, power supply etc..

Controller 170 is usually connect with AIDC equipment 160 to track and the unique relevant letter of each chip encapsulation assembly 126 Breath.For example, each chip encapsulation assembly 126 may include machine readable identification associated with each chip encapsulation assembly 126 (ID) label 144.In one example, identification label 144 is square printing, embossing, laser-induced thermal etching, label or bonding such as passing through Formula is coupled to each chip encapsulation assembly 126.

ID labels 144 can be bar code, radio frequency (RF) transponder (i.e. RFID tag) or other machines readable tag.Cause This, AIDC equipment 160 must be compatible type, the type for reading machine sensible information label currently in use.One In a example, AIDC equipment 160 can be that RFID reader, barcode reader, camera or other suitable labels are read Device.

Individual files (the discreet of ID labels 144 and memory storage or addressable information by controller 170 File) it is associated.Individual files associated with ID labels 144 can be handled by the distance host communicated with the controller 170 System 180 is inputted by the user interface of the controller 170.Information associated with ID labels 144 may include but not It is limited to the one or more of following message：Unique chip encapsulation assembly identification number, the type of chip encapsulation assembly 126, core Test result (such as passing through, failure or test data), defect information and the chip encapsulation assembly 126 of piece package component 126 Position in test system 100 and other information.

First queue platform 114 is configured as receiving at least the first barrow 118, which includes multiple use In the chip encapsulation assembly 126 tested in chip encapsulation assembly test system 100.For example, first queue platform 114 can be with Including support surface 128, for by the first barrow 118 (and/or other chip encapsulation assembly barrows) be maintained at suitable for by Robot 150 picks up and places and (shift) position of chip encapsulation assembly 126 from the first barrow 118.

First queue platform 114 is arranged adjacent to enters port 106 by what shell 102 was formed.Into port 106 It is sized to allow the first barrow 118 by wherein.Lid 108 is for opening and closing entrance port 106.With lid 108 It is removed and in the open state into port 106, the first barrow 118 can be transferred in shell 102 and be put It sets on the support surface 128 of first queue platform 114, or removes described first from first queue platform 114 in a similar way Barrow 118.It, can into port 106 when the first barrow 118 is not transmitted by shell 102 into port 106 The cleannes of the interior zone 104 to help to maintain chip encapsulation assembly to test system 100 are closed by lid 108.

First barrow 118 be typically divided into remain set at chip encapsulation assembly 126 on the first barrow 118 it One multiple regions.Each region can be identified by the preferred coordinates system of the first barrow 118 so that controller 170 is other Processor knows which chip encapsulation assembly 126 resides in the specific sole zone of the first barrow 118.For example, described Region can be arranged with row and column so that the specific region of the first barrow 118 will have the combination of unique number of lines and columns.Pass through , the identity, survey associated with the certain chip package assembling 126 being disposed therein by the sole zone of the first barrow 118 It tries information and other information can be sealed in the case where chip encapsulation assembly 126 does not have ID labels 144 with the chip of unique identification Arrangement 126 is associated and tracks.Chip envelope by the tracking of controller 170 as the unique identification of chip encapsulation assembly 126 Arrangement 126 is moved by robot 150 in test system 100, and can be with the first barrow 118 or (if robot 150 by chip encapsulation assembly 126 back on the barrow different from 126 barrow of chip encapsulation assembly is initially picked up when) with Different sole zones on other barrows are associated.

First barrow 118 further include by AIDC devices 160 can machine read first information label 122.The first information Label 122 can be bar code, radio frequency (RF) transponder (i.e. RFID tag) or other machines readable tag.Therefore, AIDC is set Standby 160 must be compatible type, the type for reading machine sensible information label currently in use.

First information label 122 to by controller 170 memory storage or the individual files of addressable information it is related Connection.Individual files associated with first information label 122 can be by the distance host processing system that is communicated with controller 170 180 are inputted by the user interface of controller 170.Information associated with first information label 122 may include but unlimited In：Unique barrow identification number, the chip package group included in the barrow (for example, first barrow 118) of carrying label The type of part 126, included in the first barrow 118 certain chip package assembling 126 (for example, by row and column position, or Sequence number) mark, the test result of certain chip package assembling 126 included in the first barrow 118 and be included in One kind or multiple in defect information of certain chip package assembling 126 in first barrow 118 etc..

Controller 170 can manage information associated with first information label 122 and/or ID labels 144.For example, having The information for closing test result (such as by, failure or specifically shows matrix, such as power consumption, resistance, RC retardation ratio, temperature increase Deng) can be added to and included in first barrow associated with first information label 122 and/or ID labels 144 118 126 associated file of certain chip package assembling in.In addition, if being included in the certain chip in the first barrow 118 Package assembling 126 is transferred on another barrow with itself unique information label, then can will be with the chip package 126 associated information of component removed from file associated with first information label 122 and be added to it is described another In the relevant information of information labels of a barrow adherency.

As described above, although specific information label and batch and/or specific core of the information usually by adhering to barrow Piece package assembling 126 is associated, but when chip encapsulation assembly 126 itself includes machine readable unique ID tag 144, AIDC Device 160 and controller 170 can be used for tracking and store associated with those chip encapsulation assemblies 126 information, without will be special Fixed chip encapsulation assembly 126 is associated with specific barrow.

In the example depicted in fig. 1, modularization chip encapsulation assembly test system 100, which also comprises, is arranged in interior zone At least second queue platform 116 in 104.Second queue platform 116 includes support surface 128, is configured as receiving comprising multiple Second barrow 120 of chip encapsulation assembly 126, for being surveyed in modularization chip encapsulation assembly test system 100 Examination.

Second barrow 120 can be configured as based on identical as above-mentioned first barrow 118, in addition to the second barrow 120 include except the second information labels 124.Second information labels 124 be based on it is identical as above-mentioned first information label 122, in addition to Second information labels 124 and the independent information that can be stored or be accessed by the memory of controller 170 are uniquely associated, It is different from 122 associated information of first information label.

It can also include aligner 142 that chip encapsulation assembly, which tests system 100,.Aligner 142 is directed at and/or adjusts chip Solder projection on the bottom of package assembling 126 so that chip encapsulation assembly 126 is in the testboard or most with test system 100 It is not damaged when the printed circuit board connection of whole purposes.

In one example, before chip encapsulation assembly 126 is transmitted to the testboard of test system 100, robot Chip encapsulation assembly 126 is transmitted to aligner 142 to adjust solder projection by 150 from queue platform 114,116.

In one example, AIDC equipment 160 can be positioned adjacent at aligner 142, with identification chip encapsulation group Part 126.Because each chip encapsulation assembly 126 must be before test by aligner 142, by AIDC equipment 160 It is placed in certain position to be advantageous, in the position the AIDC equipment when chip encapsulation assembly 126 is in aligner 142 160 can read be arranged each chip encapsulation assembly 126 on ID labels 144.

In another example, the position that AIDC equipment 160 can be between queue platform 114,116 and testboard 130,132 It sets, the ID labels 144 being provided on each chip encapsulation assembly 126 can be in chip encapsulation assembly 126 by robot 150 It is read while transmission.

Before chip encapsulation assembly 126 is transmitted to the testboard of test system 100 by robot 150, immediately by borrowing It helps its ID label 144 to be identified as chip encapsulation assembly 126, advantageously simplifies the programming of each chip encapsulation assembly 126 (programming) it and tracks, and allows test result easily associated with the chip encapsulation assembly of test 126, and nothing Need fine trace routine.

As described above, multiple testboards are arranged in the interior zone 104 of shell 102.In the illustrated example shown in fig. 2, show The first testboard 130 and secondary test board 132 are gone out.It is contemplated, however, that any amount of testboard can be used, as long as in shell There are spaces in 102, and robot 150 can access all testboards.

Each of testboard 130,132 includes interface 134,136, and being configured as can be in chip package with one kind The mode that test is executed on component 126 receives and is communicatively connected to a few chip encapsulation assembly 126.Interface 134,136 can Including on one or more chips socket, daughter board, probe or to be adapted to set up chip encapsulation assembly 126 and testboard 130,132 The other electrical interfaces communicated between test circuit.In one example, two interfaces 134,136 can be configured to receive identical The chip encapsulation assembly 126 of type, to realize the test handling capacity of bigger.In another example, in interface 134,136 Each, which can be configured as, receives different types of chip encapsulation assembly 126, to make different types of chip encapsulation assembly 126 are tested simultaneously.

First interface 134, which can be configured as, receives one single chip package assembling 126 or multiple chip encapsulation assemblies 126. First interface 134 easily can remove and replace with another interface on the first testboard 130, be configured to from it is different The chip encapsulation assembly 126 of quantity and/or type interacts.Therefore, the ability that other interfaces are exchanged with first interface 134 is permitted Perhaps the first testboard 130 is easily adapted for meeting production requirement with minimum cost and downtime.136 quilt of second interface It is similarly configured.

First testboard 130 includes the first test processor 138.First test processor 138 is generally included for controlling Central processing unit (CPU), memory and the support circuits of the operation of first testboard 130.The CPU can be used for work Any type of general-purpose computer processor of industry environment.Software program or sequence of program instructions are stored in the memory In, such as random access memory, read-only memory, floppy disk or hard disk drive or the digital storage of other forms.It is described Support circuits are usually coupled to CPU, and may include cache, clock circuit, input/output, power supply etc..First Test processor 138 is coupled to the chip encapsulation assembly 126 for the first interface 134 for being connected to the first testboard 130.

Test program (for example, scheduled test program) is stored or is accessed by the first test processor 138.The test journey Sequence can be input to the first test processor 138 by user interface, or from controller 170 and/or host processing systems 180 upload or access.With in the on one or more chips package assembling coupled with the first interface 134 of the first testboard 130 The mode of predefined test is run on 126, first test processor 138 executes test program.The test program can be with Be program after one or more DC test programs, aging procedure, aging, final test program or other will be in chipset The predefined test program executed on part 126.

In one example, DC is executed on the chip encapsulation assembly 126 in being arranged in the first testboard 130 test journey Sequence.The DC test programs may include the high DC loads for making chip encapsulation assembly 126 be subjected to a period of time, and test chip is sealed Short circuit, resistance, temperature raising, RC delays, speed, other performance characteristics or the failure or other defect of arrangement 126.The DC Test program may include that will test information (such as by, failure or other performance informations) to be added to and be stored in controller 170 It is upper and in the unique associated information of tested chip encapsulation assembly 126.The result of the DC test programs can also be by Controller 170 utilizes, to guide the chip encapsulation assembly tested 126 to be transferred to specific barrow based on the test result Or the specific region of barrow.For example, all chip encapsulation assemblies 126 by DC test programs can be transferred to it is selected Barrow adjacent area so that it is all by chip encapsulation assembly 126 be grouped together on the barrow, and with It is all not to be separated by the chip encapsulation assembly 126 of DC test programs.In another example, all by DC test programs Chip encapsulation assembly 126 can be sent to a barrow, such as the first barrow 118, and all not test journey by DC The chip encapsulation assembly 126 of sequence can be sent to different barrows, for example, the second barrow 120.

In another example, burn-in test journey is executed on the chip encapsulation assembly 126 in being arranged in the first testboard 130 Sequence.Burn-in test program may include so that chip encapsulation assembly 126 is subjected to hyperbaric environment, such as high voltage, high current, high temperature and / or high frequency electrical signal.Burn-in test program may include the hyperbaric environment for making chip encapsulation assembly 126 be subjected to a period of time, and And short circuit, resistance, temperature raising, RC retardation ratio, speed, other performance characteristic or the failure of test chip package assembling 126 or its His defect.Burn-in test program may include that will test information (such as by, failure or other information) to be added to and be stored in control On device 170 processed and in the unique associated information of the chip encapsulation assembly 126 tested.The result of burn-in test program also may be used To be used by controller 170, such as described above, to guide the chip encapsulation assembly 126 tested based on the test result It is transferred to the specific region of specific barrow or barrow.

In another example, it is tested after executing aging on the chip encapsulation assembly 126 in being arranged in the first testboard 130 Program (post burn-in test routine).Test program may include in room temperature or less than the environment of room temperature after aging The electrical characteristics and function of lower test chip package assembling 126.Test program may include making chip encapsulation assembly 126 after aging Undergo the room temperature environment of a period of time, and the electric characteristic and function of test chip package assembling 126.Test program is also after aging It may include the room temperature environment that is less than for making chip encapsulation assembly 126 undergo a period of time, and test chip package assembling 126 Electrical characteristic and function.After aging test program may include will test information (such as performance, function, by, failure or other Performance information) be added to be stored on controller 170 and with the unique associated information of tested chip encapsulation assembly 126 In.Other performance can include but is not limited to resistance, temperature raising, RC retardation ratio, speed, failure or one kind in other defect or It is a variety of.The result of test program can also be used by controller 170 after the aging, such as described above, to be based on the test As a result the chip encapsulation assembly 126 that guidance was tested is transferred to the specific region of specific barrow or barrow.

In another example, final test journey is executed on the chip encapsulation assembly 126 in being arranged in the first testboard 130 Sequence.Final test program may include the test chip envelope at the temperature (for example, raised temperature) being lifted on room temperature The electrical characteristics and function of arrangement 126.Final test program may include the liter for making chip encapsulation assembly 126 undergo a period of time The electrical characteristics and function of high temperature environment and test chip package assembling 126.Final test program may include that will test Information (such as performance, function, pass through, failure or other performance informations) be added to be stored on controller 170 and with it is tested In the unique associated information of the chip encapsulation assembly 126 of examination.The result of the final test program can also be by controller 170 It uses, such as described above, specific carrying is transferred to the chip encapsulation assembly 126 tested based on test result guidance The specific region of frame or barrow.

In another example, the final test program executed on chip encapsulation assembly 126 can simulate and chip package The operating condition for the device that component 126 is connected.The operating condition of final test program may include temperature change and voltage wave It is dynamic.

It is expected that other test programs can be executed in the first testboard 130 or other testboards in test system 100.

In the embodiment shown in fig. 1, test system 100 includes secondary test board 132.Secondary test board 132 can lead to It crosses robot 150 and the first testboard 130 is separated.Secondary test board 132 can by one or more queue platforms 114, 116 and first testboard 130 be separated.Secondary test board 132 is configured similar to the first testboard 130.Secondary test board 132 include the second test processor 140.Second test processor 140 is configured similar to the first test processor 138, and And generally include the central processing unit (CPU) of the operation for controlling secondary test board 132, memory and support circuits.

Second test processor 140 is stored with or can access test program (for example, presumptive test program).By second The test program that test processor 140 is run can be identical or different with the test program that is run by the first test processor 138. When the test program run by test processor 138,140 is identical, or at least it is used for the chip encapsulation assembly of same type When 126, compared with conventional test system, test handling capacity can be enhanced.When the test journey run by test processor 138,140 When sequence is used for different types of chip encapsulation assembly 126, test system 100 can advantageously test two distinct types of simultaneously Chip encapsulation assembly 126, and in some embodiments, the chip encapsulation assembly 126 after defective test is categorized into altogether Same barrow is inferred to the overall test time of a collection of chip encapsulation assembly 126 to save space.

As described above, robot 150 be arranged in interior zone 104, and have a motion range, it is operable with Chip encapsulation assembly 126 is transmitted between arbitrary queue platform 114,116 and testboard 130,132.In one example, robot 150 include robot base 152, robot linkage 154, robot wrist 156 and at least one robot end behaviour Vertical device (effector) 158.Robot base 152 can be located at the center of shell 102, and in one embodiment, by institute It states queue platform and testboard 114,116,130,132 surrounds.The robot linkage 154 is coupled to machine in proximal end People's pedestal 152.Motor in the robot base 152 it is operable with by robot linkage 154 around robot bottom Seat 152 rotates to up to 360 degree.

Robot wrist 156 is coupled to the distal end of robot linkage 154.At least one robot end effector 158 are coupled to robot wrist 156.

Robot end effector 158 is typically configured each work in test system 100 for ease of robot 150 Pickup and chip placement package assembling 126 between platform.In the example depicted in fig. 1, robot 150 includes at least two robots End effector 158.It is following described below, there are at least two robot end effectors 158 to allow in test system Chip encapsulation assembly 126 is more effectively transmitted in 100.

Robot linkage 154 is configured as radially extending and retracting robotic end relative to robot base 152 Portion's manipulation device 158 and robot wrist 156.Robot linkage 154 can be additionally configured to control robot end behaviour Vertical height of the device 158 in shell 102.Alternatively, robot base 152 may include being configured as control robot linkage dress It sets 154 and is coupled to the actuator of the height of its robot end effector 158.

Robot wrist 156 also allows robot end effector 158 to be rotated relative to robot linkage 154. The rotation of robot wrist 156 and the movement of robot linkage 154 allow robot end effector 158 for example to hang down Directly the mode in the direction of the support surface of barrow 128 is directed, and allows one be selected in chip encapsulation assembly 126 It is picked up from any one in queue platform and testboard 114,116,130,132 or placed thereon.

Robot end effector 158 is commonly configured to, and is being arranged in queue platform 114,116 and testboard 130, During being transmitted between barrow 118,120 between 132, chip encapsulation assembly 126 is selectively secured to robot 150.In other words, robot end effector 158 makes it possible to through robot end effector 158 at any one Pickup and chip placement package assembling 126 between queue platform 114,116 and testboard 130,132.

Shown in embodiment also shown in FIG. 1, the AIDC equipment 160 is arranged suitable for reading to adhere in the first He It is coupled to robot at the position of identification label 122,124 on barrow 118,120 on second queue platform 114,116 150.For example, AIDC devices 160 may be coupled to the distal end of robot linkage 154, robot wrist 156 or robotic end One of portion's manipulation device 158 so that AIDC devices 160 can be can be easily positioned at by robot 150 is more than or close to queue The position of platform 114,116, wherein label 122,124 can be reliably read by AIDC equipment 160 here.Alternatively, one or Multiple AIDC equipment 160 can be located in shell 102, and enable to that identification is arranged in queue platform 114,116 specific removes Transport frame 118,120.

Fig. 2 is the schematic side elevation of a part for the chip encapsulation assembly test system 100 of Fig. 1, shows and is configured For an example of the first queue platform 114 of the multiple barrows of receiving.In the illustrated example shown in fig. 2, the first barrow 118 is arranged On the first support surface 128 of first queue platform 114, and second in first queue platform 114 is arranged in the second barrow 120 It supports on surface 128.First and second support surfaces 128 can be at the different height in queue platform 116.For example, first and Two support surfaces 128 could be provided as one on top of the other so that the first and second barrows 118,120 are stacked on team In row platform 116, to allow greater number of barrow, and therefore greater number of chip encapsulation assembly 126 is disposed in Without increasing floor space (foot print) in single queue platform.The distance between first and second support surfaces 128 are One and second provides enough distances between barrow 118,120, is arranged in barrow so as to be accessed by robot 150 118, all chip encapsulation assemblies 126 on 120.

It is also shown in FIG. 2, into being dimensioned for from the transfer barrow of support surface 128 for port 106 118、 120.As described above, during the operation of test system 100, can be closed into port 106 by lid 108.

In order to help to prevent the chip encapsulation assembly 126 being arranged on barrow 118,120 contaminated, shell 102 can To optionally include the air inlet through-hole 110 in the interior zone 104 for filtered air to be provided to shell 102.One or The air filter 112 of more outsides or other suitable positions for being installed to shell 102 can provide filtered air.

Fig. 3 be Fig. 1 chip encapsulation assembly test system 100 a part schematical side top, show by It is configured to receive another example of the first queue platform 114 of multiple laterally spaced barrows.In the example depicted in fig. 3, until Few two barrows 118,120 are arranged in first queue platform 114 with the direction of lateral separation.In one embodiment, at least Two laterally spaced barrows 118,120 can be arranged on common single support surface 128.It is larger range of with needs Movement is compared with the robot for adapting to the barrow of different height, and laterally spaced barrow 118,120 advantageouslys allow for passing through Simpler and less expensive bot access chip encapsulation assembly 126.

Although it is not shown, the first queue platform 114 for being configured as receiving at least two sideways transfer framves 118,120 is gone back It may include the second support surface 128 at the as shown in Figure 2 lower height being arranged in first queue platform 114.

Also as shown in figure 3, being dimensioned so as to adapt to from the first barrow 118 transfer lateral separation into port 106 Barrow 118,120.As described above, during the operation of test system 100, can be closed into port 106 by lid 108.

Fig. 4 A-4F are the schematic side elevations of testboard, show to transmit the testboard together with chip encapsulation assembly One example of sequence.Although executing sequence shown in Fig. 4 A-4F using testboard 130, what is shown is used for by machine People 150 transfer a chip encapsulation assembly 126 and pick up another chip encapsulation assembly 126 technology can this paper be retouched It is similarly executed in any stated.

Referring initially to Fig. 4 A, robot 150 is shown, there is the robot end effector 158 by robot 150 One of first chip encapsulation assembly 126 that keeps, and another robot end effector 158 is idle (that is, empty). It will be tested in testboard 130 by the first chip encapsulation assembly 126 that robot end effector 158 is kept.And show The second chip encapsulation assembly 126 for going out the interface 134 to be coupled to testboard 130 is complete when being placed in testboard 130 At test.

As shown in Figure 4 B, robot 150 reduces idle robot end effector 158 and is arranged in testboard with engaging The second chip encapsulation assembly 126 tested in 130.As shown in Figure 4 C, in the robot end effector of robot 150 After 158 secure the second chip encapsulation assembly 126 tested, robot wrist 156 is increased by robot 150 so that not The first test chip package assembling 126 after tested and the second chip encapsulation assembly 126 for testing are all on testboard 130 Fang Shenggao.Leave the interface 134 of testboard 130 by chip encapsulation assembly 126,150 transverse shifting of robot is with by the first core Piece package assembling 126 is located on the interface 134 of testboard 130.

As shown in Figure 4 D, once the first chip encapsulation assembly 126 is on the interface 134 of testboard 130, robot wrist 156 are just reduced by robot 150 so that the first chip encapsulation assembly 126 that do not test is moved to and 130 interface of testboard 134 engage and are communicatively coupled.

As shown in Fig. 4 E-4F, robot end effector 158 discharge now with the interface of testboard 130 134 communicatedly First chip encapsulation assembly 126 of coupling, and the second chip encapsulation assembly 126 is raised off testboard 130.Institute as above It states, the first chip encapsulation assembly 126 of the interface 134 for being communicably coupled to testboard 130 now is tested in testboard 130.

Therefore, as shown in figs. 4 a-4f, allow quickly to load and unload using two robot end effectors 158 Testboard 130.Therefore, load faster and unloading result in the faster handling capacity by testboard 130, and eventually reduce The manufacture of chip encapsulation assembly 126 and testing cost.

In some cases, chip encapsulation assembly 126 may need to be pushed correct with the interface 134 with testboard 130 Contact.Although multiple technologies can be used to complete by the suitably seating of chip encapsulation assembly 126, with the interface with testboard 130 134 correctly contact, and provide an example in Fig. 5, pusher 502 is located in chip encapsulation assembly 126 using rack 500 On.Rack 500 can be any suitable XY positioning devices.Pusher 502 can be any suitable linear actuators, such as Pneumatic actuator or electric actuator.

Fig. 6 is the schematic plan of another chip encapsulation assembly test system 600.Chip encapsulation assembly tests system 600 generally similar to said chip encapsulation component test system 100, in addition to wherein workbench 114,116,130,132 by along The track 604 that robot 150 advances is arranged rather than surrounds 150 radial arrangement of robot.A few thing platform uses dotted line in figure 6 It shows, two or more certain types of workbench can be utilized with instruction.

Test system 600 generally includes pedestal 602, and workbench 114,116,130,132 is arranged on the pedestal 602. In one embodiment, at least three in workbench 114,116,130,132 are usually aligned with linear array.Aligner 142 It can also substantially linearly be arranged with workbench 114,116,130,132.In one example, aligner 142 is located at queue platform Between 114 and testboard 130.

Robot 150 is arranged in transverse shifting in test system 600.For example, robot 150 can be in workbench 114, it is linear between 116,130,132.In the example depicted in fig. 6, robot 150 is mounted to guiding device 606, It advances along the track 604 fixed to pedestal 602.Alternatively, guiding device 606 can hang or be fixed to ceiling or shell 102 (being not shown in Fig. 6).It is contemplated that can using more than one robot 150 come increase workbench 114,116,130, Transmission efficiency between 132.Although being not shown, two or more additional robots 150 can be used.For example, one A or multiple robots 150 can be movably attached to track 604 with input rank platform 114 and testboard 130,132 it Between moving chip package assembling 126, and one or more additional machine people 150 can be movably attached to track 604 with Moving chip package assembling 126 between testboard 130,132 and unloading queue platform 116.

The linear arrangement of test system 600 allows to utilize more queue platforms or testboard, while to floor area requirement Influence it is minimum.In addition, the linear arrangement of test system 600 makes robot 150 be able to carry out faster transmission.

Fig. 7 is for test chip encapsulation component test system (chip encapsulation assembly test system as described above 100,600) flow chart of another method 700 of the chip encapsulation assembly 126 in.By that will include more than first for test First barrow 118 of chip encapsulation assembly 126 is set to the shell of modularization chip encapsulation assembly test system 100,600 In 102, the method 700 starts at operation 702.It is associated with chip encapsulation assembly 126 using reading at operation 704 Machine sensible information label 122 AIDC devices 160, come the chip package for determining with obtaining from first barrow 118 An associated information in component 126.The readable information label 122 can be arranged in chip encapsulation assembly 126 or the On one barrow 118.It is described associated with the first barrow 118 (or chip encapsulation assembly 126) that is being read by AIDC equipment 160 The unique marks of information labels 122 be provided to controller 170, the storage of the controller 170 or access related setting the The information of chip encapsulation assembly 126 on one barrow 118, be such as, but not limited to present in the first barrow 118 and because The type of this chip encapsulation assembly associated with label 122 126.The AIDC devices 160 are arranged in shell 102, and It is may be coupled to the robot being arranged in shell 102 150, and for the moving chip package assembling 126 in shell 102.Or Another appropriate location in shell 102 can be arranged in person, AIDC equipment 160.

At operation 706, including the second barrow 120 setting of the second multi-chip package component 126 for test exists Modularization chip encapsulation assembly is tested in system 100,600.Operation 708 at, by with operation 704 it is described it is identical in a manner of, make The type for being arranged in the second barrow 120 or the chip encapsulation assembly 126 being taken out is determined with AIDC equipment 160.

At operation 710, type based on chip encapsulation assembly 126 and it will be executed in corresponding testboard 130,132 Predefined test program, be arranged in the first multi-chip package component 126 in the first barrow 118 the first chip envelope Arrangement 126 is sent to the first testboard 130 or the secondary test board 132 of test system 100,600.For example, if by machine The type for the chip encapsulation assembly 126 that device people 150 transmits is needed using the predefined test program progress in testboard 130 Test, and be loaded with different predefined test programs in testboard 132, then robot 150 can be by chip package group The transmission of part 126 (routeing) is tested to testboard 130.Alternatively, based on being arranged at least one testboard 130,132 The configuration of interface 134,136 and predefined test program, the first multi-chip package component being arranged in the first barrow 118 The first chip encapsulation assembly 126 in 126 is sent to the first testboard 130 or the secondary test board of test system 100,600 132.For example, if the type of the chip encapsulation assembly 126 transmitted by robot 150 is needed using in testboard 130 Predefined test program test and have being configured as being electrically connected with what interface 134 coordinated, and in testboard 132 With different predefined test programs and it is loaded with incoherent interface, robot 150 passes chip encapsulation assembly 126 It send and (route) and tested to testboard 130.

The method 700 can also include the test result based on the first chip encapsulation assembly 126, after a test by One chip encapsulation assembly 126 is transported back to the region of the first barrow 118.For example, robot 150 can by with by test knot The chip encapsulation assembly 126 of fruit is transmitted to a region of the first barrow 118, and by the core with unsanctioned test result Piece package assembling 126 is transferred to the different zones of the first barrow 118, to by with unsanctioned chip encapsulation assembly 126 classify.

The method 700 can also include by the test result of the first chip encapsulation assembly 126 and the first chip package group Position of the part 126 in the first barrow 118 (or other barrows) be transmitted to far from chip encapsulation assembly test system 100, The host processing systems 180 of 600 settings.

The method 700 can also be included in tested after in response to the acceptable of the first chip encapsulation assembly 126 Test result the first chip encapsulation assembly 126 is returned into the first barrow 118, and in response to the after being tested First chip encapsulation assembly 126 is returned to different barrows by the unacceptable test result of one chip encapsulation assembly 126. For example, robot 150 can by with by the chip encapsulation assembly 126 of test result be transmitted to the first barrow 118, and Chip encapsulation assembly 126 with unsanctioned test result is transmitted to different barrows, therefore sorts by and does not lead to The chip encapsulation assembly 126 crossed.

The method 700 can also include, and type based on chip encapsulation assembly 126 and be held on corresponding testboard Row test program, by the first chip package in second group of multiple chip encapsulation assembly 126 being arranged in the second barrow 120 Component 126 is transmitted to the first testboard 130 or secondary test board 132, wherein in first group of multiple chip encapsulation assembly 126 First chip encapsulation assembly 126 of one chip encapsulation assembly 126 and second group of multiple chip encapsulation assembly 126 is different type , and wherein the first testboard 130 or secondary test board 132 are configured as executing different tests.

Fig. 8 is adapted for testing the chip encapsulation assembly test system 800 of the chip encapsulation assembly with different structure simultaneously Schematic plan.For example, chip encapsulation assembly test system 800 can be configured as while test the first chip package group Part 126_AWith the second chip encapsulation assembly 126_B, wherein the first chip encapsulation assembly 126_ADifferent from the second chip encapsulation assembly 126_B.First chip encapsulation assembly 126_AWith the second chip encapsulation assembly 126_BThe ruler of (also referred to collectively as chip encapsulation assembly 126) Very little, soldered ball connecting interface configuration, performance, structure or other attributes are different so that cannot be with identical interface with identical test Program is come to different chip encapsulation assemblies 126_A, 126_BIt is tested.

Modularization chip encapsulation assembly test system 800 generally includes the shell 102 with interior zone 104.At least one A input rank platform 114, at least one output queue platform 116, at least one testboard 130, robot 150 and optional automatic Identification and data capture (AIDC) device 160 are arranged in the interior zone 104 of shell 102.Robot 150 has a movement model It encloses, it is operable to transmit chip encapsulation assembly 126 between the arbitrary queue platform and testboard of test system 800. In embodiment shown in Fig. 8, test system 800 includes two input rank platforms 114_A, 114_B(be referred to as input rank platform 114) and Two output queue platforms 116_A, 116_B(being referred to as queue platform 116).Input rank platform 114_AIt is configured as receiving and keep will be The first chip encapsulation assembly 126 tested in test system 800_A, and input rank platform 114_BIt is configured as receiving and keep will be The second chip encapsulation assembly 126 tested in test system 800_B.Similarly, output queue platform 116_AIt is configured as receiving and protect Hold the first chip encapsulation assembly 126 tested in test system 800_A, and output queue platform 116_BIt is configured as receiving and protect Hold the second chip encapsulation assembly 126 tested in test system 800_B.With at least two input rank platforms 114 and at least Two output queue platforms 116 allow each type of chip encapsulation assembly 126_A、126_BWith dedicated input and output queue platform 114_A/B、116_A/B, which simplify the entirety in the route selection of the chip encapsulation assembly 126 in test system 800 and factory Processing, both of which advantageously reduce the manufacturing cost of chip encapsulation assembly 126.

It further includes controller 170 that modularization chip encapsulation assembly, which tests system 800, is used to control chip encapsulation assembly survey The operation of test system 800 includes operation and the information (when it is present) that is read by AIDC equipment 160 of processing of robot 150.Control Device 170 processed generally includes the central processing unit (CPU) of the operation for controlling chip encapsulation assembly test system 800, storage Device and support circuits.The CPU can be any type of general-purpose computer processor that can be used for industrial environment.Software journey Sequence or sequence of program instructions are stored in the memory, such as random access memory, read-only memory, floppy disk or hard disk The digital storage of driver or other forms.The support circuits are usually coupled to CPU, and may include cache, Clock circuit, input/output, power supply etc..

In one example, controller 170 is usually connect with AIDC equipment 160 to track and each chip encapsulation assembly 126 unique relevant information.For example, each chip encapsulation assembly 126 may include related to each chip encapsulation assembly 126 Machine readable identification (ID) label of connection.In one example, label 144 is identified_ASuch as by printing, embossing, laser-induced thermal etching, Label or bonding etc. are coupled to chip encapsulation assembly 126_A.It is coupled to chip encapsulation assembly 126_AIdentification label 144_AIncluding extremely It can be used to identify chip encapsulation assembly 126 less_AWith chip encapsulation assembly 126_BFor different types of information, chip encapsulation assembly 126_BWith coupled identification label 144_B。

ID labels 144_A、144_B(being referred to as ID labels 144) can be bar code, (i.e. RFID is marked radio frequency (RF) transponder Label) or other machines readable tag.Therefore, AIDC equipment 160 must be compatible type, for reading machine currently in use The type of readable information label.In one example, AIDC equipment 160 can be RFID reader, barcode reader, photograph Machine or other suitable tag readers.

ID labels 144 can optionally with by controller 170 memory storage or addressable information individual files It is associated.Individual files associated with ID labels 144 can be inputted by the user interface of controller 170, or from long-range Host processing systems 180 are sent to controller 170.Information associated with ID labels 144 can include at least chip package The type of component 126, and can optionally include but be not limited to the one or more of following message：Unique chip package group Part identification number, the test result (such as passing through, failure or test data) of chip encapsulation assembly 126, defect information and core Position etc. of the piece package assembling 126 in test system 800.

In the example depicted in fig. 8, the first input rank platform 114_AIt includes multiple chips to be configured as receiving at least one Package assembling 126_AThe first barrow 118_A, for being tested in chip assembly test system 800.For example, input rank Platform 114_AMay include support surface 128, support surface 128 is suitable for the first barrow 118_AIt is maintained at suitable for by robot 150 from the first barrow 118_APickup and placement (that is, transfer) chip encapsulation assembly 126_APosition.

Shown in Fig. 8, the second input rank platform 114_BIt includes multiple chip packages to be configured as receiving at least one Component 126_BThe second barrow 118_B, for being tested in chip encapsulation assembly test system 800.For example, the second team Row platform 114_BMay include support surface 128, support surface 128 is suitable for the second barrow 118_BIt is maintained at suitable for by robot 150 from the second barrow 118_BPickup and placement (that is, transfer) chip encapsulation assembly 126_BPosition.As described above, chip package Component 126_BWith chip encapsulation assembly 126_ACompared to being different type, thus cannot use identical interface and test program into Row test.

Input rank platform 114 is arranged adjacent to enters port 106 by what shell 102 was formed.Into the big of port 106 It is small to be arranged to allow the first and second barrows 118_A、118_BBy wherein.Lid 108, which can be used for opening and closing, enters port 106.As lid 108 is removed and in the open state, the barrow 118 into port 106_A、118_BShell can be transferred to In 102, and it is placed on the support surface 128 of input rank platform 114 appropriate.When barrow 118_A、118_BNot over outer When being transmitted into port 106 of shell 102, can be closed into port 106 by lid 108, to assist in keeping chip package group Part tests the cleannes of the interior zone 104 of system 800.

Similarly, output queue platform 116 is disposed proximate to be formed by shell 102 another into port 106.As above It is described, it is sized to the first and second barrows 120 of permission into port 106_A、120_BBy wherein.Lid 108 is available Enter port 106 in opening and closing.As lid 108 is removed and in the open state, the barrow into port 106 120_A, 120_BIt can be transferred in shell 102, and be placed on the rack surface 128 of input rank platform 114 appropriate. When barrow 120_A, 120_BIt, can be by lid 108 into port 106 when being transmitted into port 106 not over shell 102 It closes, to assist in keeping the cleannes that chip encapsulation assembly tests the interior zone 104 of system 800.

Controller 170 can manage information associated with ID labels 144.For example, can add about test result Information (such as by, failure or specific performance matrix, such as power consumption, resistance, RC retardation ratio, temperature increase etc.) in file, This document be included in and ID labels 144_AAssociated first barrow 118_AIn certain chip package assembling 126_AIt is related Connection.

It can also include at least two aligners 142 that chip encapsulation assembly, which tests system 800,_A、142_B(it is referred to as aligner 142).Aligner 142 be aligned and/or adjust chip encapsulation assembly 126 bottom on solder projection so that when with test system 800 or final use printed circuit board testboard connection when, chip encapsulation assembly 126 is not damaged.This aligner is logical It is often known, such as Micron Technologies is transferred after submitting on October 20th, 2000, the U.S. of Inc is special Sharp No.6, described in 685,080, the patent entirely through being incorporated by.

First aligner 142_AIt is configured to be directed at and/or adjust chip encapsulation assembly 126_ABottom on solder projection, And the second aligner 142_BIt is configured to be directed at and/or adjust chip encapsulation assembly 126_BBottom on solder bump.With extremely Few two aligners 142 advantageously enable test system 800 to handle and test simultaneously tool, and there are two types of different configuration of solders The chip encapsulation assembly 126 of convex block.

In one example, by chip encapsulation assembly 126_AIt is transmitted to before the testboard 130 of test system 800, machine Device people 150 is by chip encapsulation assembly 126_AFrom first queue platform 114_AIt is transmitted to the first aligner 142_ATo adjust solder projection.Class As, by chip encapsulation assembly 126_BIt is transmitted to before the testboard 130 of test system 800, robot 150 can be by chip Package assembling 126_BFrom second queue platform 114_BIt is transmitted to the second aligner 142_BTo adjust solder projection.Therefore, two differences are matched The detector 142 set allows test system 800 to use single testboard 130 while the chip package of load and test different types Component 126.

In one example, AIDC equipment 160 can be positioned at close to aligner 142_A/_B, to be positioned over aligner Identification chip package assembling 126 before in 142, is configured as so that it is guaranteed that the chip encapsulation assembly of right type is loaded into In the aligner 142 for receiving the chip encapsulation assembly of this type.Single AIDC equipment 160 can be with more than one aligner 142 are used together.However, aligner 142 and AIDC equipment 160 with identical quantity, especially in 160 quilt of AIDC equipment When being situated next to aligner 142, allow faster handling capacity by reducing robot motion.

In another example, the position that AIDC equipment 160 can be between input rank platform 114 and testboard 130, with Permission is read when chip encapsulation assembly 126 is shifted by robot 150 to be arranged on each chip encapsulation assembly 126 ID labels 144.In another example, AIDC equipment 160 can be arranged in robot 150 so that when chip encapsulation assembly 126 ID labels 144 can be read in any position in test system 800 when being kept by robot 150.

As described above, at least the first testboard 130 is arranged in the interior zone 104 of shell 102.Shown in Fig. 8 shows In example, the first testboard 130 and secondary test board 132 are shown.Secondary test board 132 can be configured as and the first testboard 130 is identical or different.As long as however, it is contemplated that there are spaces in shell 102, then any amount of test can be used Platform, and robot 150 may access all testboards.

Testboard 130 includes two interfaces 134_A、134_B, each interface 134_A、134_BIt is configured as, with can be single To chip encapsulation assembly 126 in testboard 130_AWith chip encapsulation assembly 126_BThe mode that test can be executed is received and is communicated Ground connects chip encapsulation assembly 126_A/BMiddle different one.Interface 134_A、134_BIt can respectively be inserted including on one or more chips Seat, daughter board, probe or the other electricity for the communication being adapted to set up between chip encapsulation assembly 126 and the test circuit of testboard 130 Interface.For example, interface 134_AIt can be configured as and receive chip encapsulation assembly 126_A, and interface 134_BIt is configured as receiving chip Package assembling 126_B, it is enable to while the chip encapsulation assembly of test different types 126.Addition and 130 phase of testboard Another same testboard 132 allows two chip encapsulation assemblies 126 of bigger_A、126_BHandling capacity.Relative to chip package Component 126_BHandling capacity, addition is only configured with one of interface (such as interface 134_A) another testboard 132 will allow to have The chip encapsulation assembly 126 of bigger_AHandling capacity, this advantageously allow for using single test system 800 to chip encapsulation assembly 126_AHigh power capacity operation and chip encapsulation assembly 126_BLow capacity operation both be carried out at the same time test.

The first interface 134 of testboard 130_AIt is coupled to the first test processor 138_A.First test processor 138_AUsually Include central processing unit (CPU), memory and the support circuits of the operation for controlling the first testboard 130.The CPU It can be used for any type of general-purpose computer processor of industrial environment.Software program or sequence of program instructions storage In the memory, such as random access memory, read-only memory, floppy disk or hard disk drive or the number of other forms Word memory.The support circuits are usually coupled to CPU, and may include cache, clock circuit, input/output system System, power supply etc..First test processor 138_AIt is coupled to the first interface 134 for being connected to the first testboard 130_AChip package Component 126_A。

The second interface 134 of testboard 130_BIt is coupled to the second test processor 138_B.Second test processor 138_BUsually It is configured as and the first test processor 138_AIt is identical.Second test processor 138B, which is coupled to, is connected to the first testboard 130 Second interface 134_BChip encapsulation assembly 126_B。

The test processor 138 of separation_A、138_BIt is different convenient for being run simultaneously on different types of chip encapsulation assembly Test program.It is also contemplated that the test processor 138 of separation_A、138_BFunction can be by locally or remote from testboard 130 single processor operation.

Referring now to Figure 9, it illustrates the schematic side elevation that chip encapsulation assembly tests a part for system 800, exhibition The testboard 130 illustrated in greater detail is shown.In order to help prevent the chip encapsulation assembly 126 being arranged in test system 130 It is contaminated, shell 102 can optionally include in the interior zone 104 for filtered air to be provided to shell 102 into Wind through-hole 110.Filtered air can be by the sky of one or more outsides for being installed to shell 102 or other suitable positions Air filter 112 provides.

The support surface 128 of testboard 130 is so shown so that illustrates only first interface 134_A.The of testboard 130 One interface 134_ABe configured as substantially with second interface 134_BIt is identical, in addition to second interface 134_BIt is configured as receiving and test Different chip encapsulation assemblies are (for example, chip encapsulation assembly 126_B), and first interface 134_AIt is configured as receiving and test chip Package assembling 126_A。

First interface 134_AIt is configured as receiving one single chip package assembling 126_AOr multiple chip encapsulation assemblies 126_A.It connects Mouth 134_AThe chip package group being configured to different number easily can be removed and replaced on the first testboard 130 Part 126_AAnother interface engaged.Therefore, interface 134 is replaced using other interfaces_AAbility allow testboard 130 easily It adapts to meet production needs with minimum cost and downtime.Interface 134_BIt is similarly configured.

The first interface 134 of testboard 130_AIncluding pcb board 906 and at least one chip carrier socket 904.The chip carrier socket 904 are configured to and are arranged in chip encapsulation assembly 126_ABottom on the predetermined configurations of solder bump array match.The One interface 134_AMultiple chip carrier sockets 904 can be configured with to test multiple chip assemblies 126_A.It is configurable for sealing with chip The chip carrier socket 904 of the particular solder bump array connection of arrangement can be replaced with different configuration of chip carrier socket 904, to permit Perhaps it is attached with different configuration of solder bump array from different chip encapsulation assemblies.In one example, it first connects Mouth 134_AChip carrier socket 904 have first encapsulation receiving area 146A (that is, receive chip encapsulation assembly 126_AAnd it is engaged with it Region), be more than second interface 134_BChip carrier socket 904 second encapsulation receiving area 146_B。

Test system 130 further includes plunger 908, and the plunger 908 is operable with by chip encapsulation assembly 126_ABe pushed into Socket 904 comes into full contact with, it is ensured that chip encapsulation assembly 126_AGood signal transmits between socket 904, in order to which chip seals Arrangement 126_ATest.Each socket 904 can be matched with the plunger 908 of their own.Plunger 908 is coupled to actuator 910, such as pneumatic linear actuator, ball-screw or other linear actuators, it can control and push chip encapsulation assembly 126_AAgainst insert The power that the plunger 908 of seat 904 applies.In one example, the operable power with about 105 grams of each solder projection of actuator 910 Plunger 908 is pressed down against on chip encapsulation assembly 126.Actuator 910 and plunger 908 are supported by pillar or rack 912 On support surface 128.

Optional shield 920 may be coupled to plunger 908.When plunger 908 is pushed against on chip encapsulation assembly 126, Shield 920 is around plunger 908 to cover chip encapsulation assembly 126 and socket 904 at least partly.In one embodiment, when When plunger 908 is pushed against on chip encapsulation assembly 126, shield 920 can be contacted with support surface 128.Shield 920 is used for It is isolated and maintains the control of the environmental condition around chip encapsulation assembly 126 dduring test.

Test system 130 additionally includes temperature control unit 930.Temperature control unit 930 for controlling dduring test The temperature of chip encapsulation assembly 126 processed.In one example, temperature control unit 930 can be by the temperature of chip encapsulation assembly 126 Degree is maintained at scheduled high temperature during a test program, such as at about 155 degrees Celsius, and in another test program It is maintained at scheduled low temperature, such as at about -40 degrees Celsius.

In one example, temperature control unit 930 can be arranged below socket 904, such as in support surface 128 Top, the inside or lower section.In another example, temperature control unit 930 can be arranged in plunger 908 or be connected to plunger 908.In plunger 908 or when being connected to plunger 908, heat (or cooling) is closely limited using optional shield 920 Around chip encapsulation assembly 126, this advantageously accelerates heating (or cooling) speed and reduces temperature drift dduring test It moves.

In one example, temperature control unit 930 may include heater 940 and cooler 950.Heater 940 can To be resistance heater, pharoid, induction heater or other heat sources.In one example, heater 940 includes coupling To the heating element 942 of heater power source 941.Heating element 942 can be resistor or lamp.Heater power source 941 is to heating Element 942 provides electric power, in response to coming from the first test processor 138_AOrder generated by heating element 942 to control Heat.

Cooler 950 can be thermoelectric device or for making heat transfer fluid circulation pass through conduit therein.In an example In, cooler 950 includes the conduit 952 for being coupled to cooling device 951.In response to coming from the first test processor 138_AFinger It enables, the temperature for the heat-transfer fluid that the control of cooling device 951 is recycled by conduit 952, for control chip encapsulation assembly 126 Temperature level.

Each interface 134_A、134_BIt can be matched with individual temperature control unit 930, to allow in each interface 134_A, 134_BThe temperature (and test program therefore) of middle execution is different.In one example, 930 quilt of temperature control unit It is configured to the first test interface 134 selectively_AThe first temperature is maintained during the first test program, and is surveyed second The second temperature different from the first temperature is maintained during examination program, to allow to execute high temperature and low temperature from single test interface Test.In another example, a temperature control unit 930 is configured as selectively during the first test program by first Test interface 134_AThe first temperature is maintained, and another temperature control unit 930 is configured as selectively in the second test By the second test interface 134 of same testboard 130 during program_BMaintain second temperature, the second test interface 134_BIt is surveyed second It tries to be in the second temperature different from the first temperature during program, to allow to seal in different chips in single testboard 130 Arrangement 126_A、126_BOn be performed simultaneously high temperature and low-temperature test.

It is discussed above with reference to Fig. 8, the first interface 134 of testboard 130_AIt is coupled to the first test processor 138_A.The One test processor 138_AUsually execute by the first test processor 138_AStorage or addressable test program are (for example, pre- location survey Try program).The test program can be input to the first test processor 138 by user interface_AIn, or from controller 170 and/or host processing systems 180 upload or access.First test processor 138, to be coupled to the first testboard 130 First interface 134_AOn one or more chips package assembling 126_AThe mode of the upper predefined test of operation, executes the test Program.The test program can be program after DC test programs, aging procedure, aging, final test program or other are predetermined Adopted will be in chip encapsulation assembly 126_AOne or more of the test program of upper execution.

In one example, the first interface 134 in the first testboard 130 is being set_AIn chip encapsulation assembly 126_AOn Execute DC test programs.The DC test programs may include making chip encapsulation assembly 126_AThe high DC for being subjected to a period of time is negative It carries, and the electric short circuit of test chip package assembling 126A, resistance, temperature raising, RC retardation ratio, speed, other performance characteristics or event Barrier or other defect.DC test programs may include will test information (such as by, failure or other performance informations) be added to Be stored on controller 170 and with tested chip encapsulation assembly 126_AUniquely in associated information.Controller 170 is also Can use DC test programs as a result, chip encapsulation assembly 126 to be tested according to test result_AIt is transferred to specific Barrow or barrow specific region.For example, all can be turned by the chip encapsulation assembly 126 of DC test programs Move on to the adjacent area of selected barrow so that it is all by chip encapsulation assembly 126 be grouped on the barrow Together, and with all it is not separated by the chip encapsulation assembly 126 of DC test programs.In another example, all to pass through DC The chip encapsulation assembly 126 of test program can be sent to a barrow, such as be arranged in output queue platform 116_AIn Second barrow 120_AFirst, and all difference can be transmitted to by the chip encapsulation assembly 126 of DC test programs Barrow, such as be arranged in output queue platform 116_AIn the second barrow 120_ASecond.

In another example, in the first interface 134 for being arranged in the first testboard 130_AIn chip encapsulation assembly 126_AOn Execute burn-in test program.Burn-in test program may include making chip encapsulation assembly 126_AIt is subjected to hyperbaric environment, such as high electricity Pressure, high current, high temperature and/or high frequency electrical signal.Burn-in test program may include making chip encapsulation assembly 126_AIt is subjected to one section The hyperbaric environment of time, and test chip package assembling 126_AShort circuit, resistance, temperature raising, RC retardation ratio, speed, other property It can feature or failure or other defect.Burn-in test program may include will test information (such as by, failure or other letter Breath) be added to be stored on controller 170 and with the chip encapsulation assembly 126 tested_AUniquely in associated information.Control Device 170 processed can also be using burn-in test program as a result, will be tested to be based on test result (as discussed above) Chip encapsulation assembly 126_AIt is transferred to the specific region of specific barrow or barrow.

In another example, it is being arranged in the first testboard 130_AIn chip encapsulation assembly 126_AIt is surveyed after upper execution aging Try program.Test program may include in room temperature or test chip package assembling 126 in the environment of less than room temperature after aging_AElectricity Characteristic and function.Test program may include making chip encapsulation assembly 126 after aging_AThe room temperature environment of a period of time is undergone, and Test chip package assembling 126_AElectric characteristic and function.Test program can also include making chip encapsulation assembly after aging 126_AUndergo the room temperature environment that is less than of a period of time, and test chip package assembling 126_AElectrical characteristic and function.It is surveyed after aging Examination program may include addition test information (such as performance, function, by, failure or other performance informations) to be stored in control On device 170 and with tested chip encapsulation assembly 126_AIn unique associated information.Other performance may include but unlimited It is one or more in resistance, temperature raising, RC retardation ratio, speed, failure or other defect.Test program after the aging As a result it can also be used by controller 170, such as described above, be used to instruct the chip package tested based on test result Component 126_AIt is transferred to the specific region of specific barrow or barrow.

In another example, it is being arranged in the first testboard 130_AIn chip encapsulation assembly 126_AUpper execution final test Program.Final test program may include in temperature (such as the raised temperature, such as Celsius 155 for being increased to room temperature or more Degree left and right) and/or less than test chip package assembling at the temperature (for example, cold temperature, for example, about -55 degrees Celsius) of room temperature 126_AElectrical characteristics and function.Final test program may include making chip encapsulation assembly 126_ABe subjected to a period of time raising (and / or cold) temperature environment, and test chip package assembling 126_AElectrical characteristics and function.Final test program may include by Test information (such as performance, function, by, failure or other performance informations) be added to be stored on controller 170 and with quilt The chip encapsulation assembly 126 of test_AUniquely in associated information.Controller 170 can also utilize final test program As a result, for example as discussed above, the chip encapsulation assembly 126 tested is controlled based on test result_AIt is transferred to specific The specific region of barrow or barrow.

In another example, in chip encapsulation assembly 126_AThe final test program of upper execution can be with analog chip and encapsulation The operating condition for the device that component 126A is connected.The operating condition of final test program may include temperature change and voltage Fluctuation.

It is expected that other test programs can be executed in the first testboard 130 or other testboards in test system 800.

Similarly, the second interface 134 of testboard 130_BIt is coupled to the second test processor 138_B.Second test processor 138_BUsually execute by the second test processor 138_BStorage is addressable different from by the first test processor 138_AIt executes Test the test program (for example, presumptive test program) returned.The test program can be input to the second survey as described above Try processor 138_B.Second test processor 138_B, in the second interface 134 with the first testboard 130_BCoupling one or Multiple chip encapsulation assemblies 126_BThe mode of the upper predefined test of operation, to execute test program.The test program can be Program after DC test programs, aging procedure, aging, final test program or other in chip encapsulation assembly 126_BUpper execution it is pre- One or more of test program of definition.Above with reference to by the second test processor 138_BThe test program of execution discusses The example of this test program.

Referring back to Fig. 8 and as described above, robot 150 is arranged in interior zone 104 and has operable fortune Dynamic range, to transmit chip encapsulation assembly 126 between arbitrary queue platform 114,116 and testboard 130,132.Show at one In example, robot 150 includes robot base 152, robot linkage 154, robot wrist 156 and at least one machine People's end effector 158.Robot base 152 can be located at the center in shell 102, and in one embodiment by team Row platform and testboard 114,116,130,132 surround.Robot linkage 154 is connected to robot base 152 in proximal end. Motor in robot base 152 is operable to rotate at most robot linkage 154 around 152 surrounding of robot base Up to 1060 degree.

Robot wrist 156 is coupled to the distal end of robot linkage 154.At least one robot end effector 158 are coupled to mechanical wrist 156.

Robot end effector 158 is typically configured each work in test system 800 for ease of robot 150 Pickup and chip placement package assembling 126 between platform.In the example depicted in fig. 8, robot 150 includes at least two robots End effector 158, wherein each end effector is adapted to pick up and places different types of chip encapsulation assembly 126.

Robot linkage 154 be configured as relative to robot base 152 radially with retraction robotic end Portion's manipulation device 158 and robot wrist 156.Robot linkage 154 can be additionally configured to controling shell end effector Height of the device 158 in shell 102.Alternatively, robot base 152 may include being configured as control robot linkage 154 and be coupled to its robot end effector 158 height actuator.

Robot wrist 156 also allows robot end effector 158 to be rotated relative to robot linkage 154. The rotation of robot wrist 156 and the movement of robot linkage 154 allow robot end effector 158 for example to hang down Directly the mode in the direction of the support surface of barrow 128 is directed, and allows chosen one in chip encapsulation assembly 126 It is a by the pickup from any one in queue platform and testboard 114,116,130,132 or placed thereon.

Robot end effector 158 is commonly configured to, be arranged in queue platform 114,116 and testboard 130, During being transmitted between barrow 118,120 between 132, chip encapsulation assembly 126 is selectively secured to robot 150.In other words, robot end effector 158 makes it possible to through robot end effector 158 at any one Pickup and chip placement package assembling 126 between queue platform 114,116 and testboard 130,132.

Shown in embodiment also shown in FIG. 8, AIDC equipment 160 can suitable for read adhere to setting input and It is coupled to robot 150 at the position of identification label 144 on barrow 118,120 on output queue platform 114,116.Example Such as, AIDC devices 160 may be coupled to the distal end of robot linkage 154, robot wrist 156 or robot end manipulation One of device 158 so that AIDC devices 160 can be easily located in by robot 150 or close to queue platform 114,116, Wherein label 144 can be reliably read by AIDC equipment 160 here.Alternatively, one or more AIDC equipment 160 may In shell 102, the specific barrow 118,120 that identification is arranged in queue platform 114,116 is enabled to.

Figure 10 is the schematic plan of another chip encapsulation assembly test system 1000.Chip encapsulation assembly test system System 1000 generally similar to said chip encapsulation component test system 800, in addition to wherein station platform 114,116,130 by along The track 1004 that robot 150 advances is arranged, rather than surrounds 150 radial arrangement of robot.Secondary test board 130 is in Fig. 10 It is shown in dotted line, one or more testboards can be utilized with instruction.Additionally, it is contemplated that more than two can be utilized to input team Row platform 114 and/or two output queue platforms 116.

Test system 1000 generally includes pedestal 1002, and station platform 114,116,130 is arranged on the pedestal 1002. In one embodiment, at least three in workbench 114,116,130 are usually aligned with linear array.Workbench 114, 116, there are two aligners 142 for setting between at least two in 130,132.In one example, aligner 142_A, 142_BPosition Between queue platform 114 and testboard 130.

Robot 150 is arranged in transverse shifting in test system 1000.For example, robot 150 can be in workbench 114,116,130 and aligner 142_A, 142_BBetween be linear.In the example depicted in fig. 10, robot 150 is mounted to Guiding device 1006, the guiding device 1006 are advanced along the track 1004 fixed to pedestal 1002.Alternatively, guiding device 1006 can be with Suspension is fixed to ceiling or shell 102 (being not shown in Fig. 10).It is contemplated that more than one robot can be utilized 150 increase the transmission efficiency between workbench 114,116,130.Although it is not shown, two or more can be used Additional robot 150.For example, one or more robots 150 can be movably attached to track 1004 in input team Row platform 114, aligner 142_A、142_BThe moving chip package assembling 126 between testboard 130, and one or more additional machines People 150 can be movably attached to track 1004 with the moving chip between testboard 130,132 and output queue platform 116 Package assembling 126.

The linear arrangement of test system 1000 allows to utilize more queue platforms or testboard, to the shadow of floor area requirement It rings minimum.In addition, the linear arrangement of test system 1000 makes robot 150 be able to carry out faster transmission.

Figure 11 A-B are another methods for the chip encapsulation assembly 126 in test chip encapsulation component test system 1100 flow chart, chip encapsulation assembly as described above test system 100,1000.The method 1100 is operating Start at 1102, the first multi-chip package component 126 for test will be included_AThe first barrow 118_A, it is arranged in module Change the first input rank platform 114 in the shell 102 of chip encapsulation assembly test system 800,1000_AIn.At operation 1104, The second barrow 118 of the second multi-chip package component 126B for test will be included_B, it is arranged in modularization chip package group Part tests the second input rank platform 114 in the shell 102 of system 800,1000_BIn.Chip encapsulation assembly 126_AAnd chip package Component 126_BIt is different types of.

At operation 1106, the chip encapsulation assembly 126 for test_AIn one by from the first barrow 118_AIt fetches, And it is transmitted to for adjusting chip encapsulation assembly 126_ASolder projection aligner 142_A.Chip envelope is adjusted in aligner 142A Arrangement 126_ASolder projection after, operation 1108 at, chip encapsulation assembly 126_AIt is sent to the first of testboard 130 Interface 134_A。

Optionally, at operation 1110, it can use and read and chip encapsulation assembly 126_AAssociated machine readable letter Cease label 144_AAIDC devices 160 determine and chip encapsulation assembly 126_ARelevant information.It is read by AIDC equipment 160 The unique mark of information labels 144 is provided to controller 170, and controller 170 stores or access related chip encapsulation assembly 126_AInformation, such as, but not limited to chip encapsulation assembly 126_AType.

At operation 1112, chip encapsulation assembly 126_BIn one by from the second barrow 118_BIt fetches, and is transmitted to use In adjusting chip encapsulation assembly 126_BSolder projection aligner 142_BFor test.In aligner 142_BAdjust chip envelope After the solder projection of arrangement 126B, at operation 1114, chip encapsulation assembly 126_BIt is sent to the first of testboard 130 Interface 134_B.Optionally, at operation 1116, with chip encapsulation assembly 126_BRelevant information can use with it is described above Identical or different AIDC devices 160 determine.

At operation 1118, the first chip encapsulation assembly 126_AIt is being arranged on the first test interface 134_ASlot 904 in When tested according to the first test program.At operation 1120, the second chip encapsulation assembly 126B is being arranged on the second survey It tries mouth 134_BSocket 904 in when tested according to the second test program.First and second test programs are different, because It is different for the type of chip encapsulation assembly.First and second test programs independently execute, therefore, can be at least in each test The first and second test programs are performed simultaneously in a part for program.First and second test programs can be described above What test program etc..

When completing to test, at operation 1122, the first chip encapsulation assembly 126_AIt is sent to and is arranged in output queue Platform 116_AIn the first barrow 118_A.According to the first chip encapsulation assembly 126_ATest result can be in the first barrow 118_AIt is interior to the first chip encapsulation assembly 126_AClassification.For example, robot 150 can will be with being sealed by the chip of test result Arrangement 126_AIt is transferred to the first barrow 118_AA region, while by the chip encapsulation assembly with failure testing result 126_AIt is transferred to the first barrow 118_ADifferent zones, to which classification passes through and fail chip encapsulation assembly 126.

Alternatively, the first chip encapsulation assembly 126 can be based on_ATest result, in multiple barrows 118_ABetween to first Chip encapsulation assembly 126_AClassify.For example, robot 150 can by with by test result chip encapsulation assembly 126_AIt is transferred to the first barrow 118_A, while by with failure test result chip encapsulation assembly 126_AIt is transferred to second Barrow 118_A, in output queue platform 116_AIn to by with failure chip encapsulation assembly 126 classify.

Similarly, when completing to test, in operation 1124, the second chip encapsulation assembly 126_BIt is sent to and is arranged in output Queue platform 116_BIn the second barrow 118_B.According to the second chip encapsulation assembly 126_BTest result, can second carry Frame 118_BIt is interior to the second chip encapsulation assembly 126_BClassify.For example, robot 150 can by with by test result Chip encapsulation assembly 126_BIt is transferred to the second barrow 118_BA region, while by with failure test result core Piece package assembling 126_BIt is transferred to the second barrow 118_BDifferent zones, to the classification chip encapsulation assembly that passes through and fail 126。

Alternatively, the second chip encapsulation assembly 126 can be based on_BTest result, in multiple barrows 118_BBetween to second Chip encapsulation assembly 126_BClassify.For example, robot 150 can by with by test result chip encapsulation assembly 126_BIt is transmitted to the second barrow 118_B, while by with failure test result chip encapsulation assembly 126_BIt is transmitted to second Barrow 118_B, in output queue platform 116_BIt will be by classifying with the chip encapsulation assembly 126 of failure.

The method 1100 can also include by the first chip encapsulation assembly 126_AWith the first chip encapsulation assembly 126_BSurvey Test result is transmitted to the host processing systems 180 being arranged far from chip encapsulation assembly test system 800,1000.

It thus provides chip encapsulation assembly tests system, test handling capacity is improved compared with conventional test system Without increasing space requirement.The chip encapsulation assembly test system can be configured as while the test core of test different types Piece package assembling.The chip encapsulation assembly test system can be additionally configured to divide the chip encapsulation assembly tested Class, more effectively to handle.Advantageously, the modularization of chip encapsulation assembly test system allows additional queue or test Platform provides additional flexibility, to meet continually changing production requirement, and with limited additional paid-in capital expenditure or downtime Carry out system reconfigures.In addition, chip encapsulation assembly test system in the application for needing small tool to occupy can by with It is set to the workbench for surrounding individual machine people and being serviced by individual machine people, or is configured with linear arrangement, enabling Faster handling capacity is obtained using greater number of workbench, be equal to reduce the unit of each chip encapsulation assembly at This.

Some embodiments describe in the following claims, and other embodiments are non-poor in the examples below that Act property.

In the first example, a kind of method for test chip package assembling is described comprising：It will be for test First chip encapsulation assembly is sent in the first test interface of the testboard of chip encapsulation assembly test system, predetermined first At a temperature of using the first predefined test program test first chip encapsulation assembly, by the second chip package for test Component is sent in the second test interface of the testboard of chip encapsulation assembly test system, wherein first and second chip Package assembling is different type, and tests second chip encapsulation assembly using the second predefined test program, wherein It tests the first and second chip encapsulation assemblies while occurring.

In the second example, the first example can be further defined as：It includes inciting somebody to action wherein to transmit the first chip encapsulation assembly First chip encapsulation assembly is arranged on the first socket with the first encapsulation receiving area；And the wherein transmission described the Two chip encapsulation assemblies include that second chip encapsulation assembly is arranged in the second socket with the second encapsulation receiving area On, wherein first encapsulation receiving area is more than described second and encapsulates receiving area.

In third example, the first example can also include using automatic identification and data capture (AIDC) obtains and third The related information of chip encapsulation assembly, and the information about third chip encapsulation assembly in response to being obtained by AIDC equipment will Third chip encapsulation assembly is transmitted to one in first or second test interface.

In the 4th example, the first example can also include keeping the first core by the first end manipulation device of robot Piece package assembling, and the second chip encapsulation assembly is kept by the second manipulation device of robot.

In the 5th example, the first example can also include the first chip encapsulation assembly of heating, and cooling second chip Package assembling.

In the 6th example, the first example can be defined further in the following manner：Wherein test the second chip envelope Arrangement includes testing the first core using the test program different from the test program for testing the second chip encapsulation assembly Piece package assembling.

In the 7th example, the first example can also be defined as：Wherein the first chip encapsulation assembly is more than the second chip Package assembling.

In the 8th example, the first example can be further defined as：Wherein surveyed using the second predefined test program It includes testing the second chip encapsulation assembly at a temperature to try the second chip encapsulation assembly, and the temperature is predefined with using first Test program test the first chip encapsulation assembly temperature it is different.

In the 9th example, a kind of method for test chip package assembling is described comprising：It will be for test First chip encapsulation assembly is sent in the first test interface of the testboard of chip encapsulation assembly test system, predetermined first At a temperature of using the first predefined test program test first chip encapsulation assembly, by the second chip package for test Component is sent in the second test interface of the testboard of chip encapsulation assembly test system, and different from the first pre- constant temperature Second chip encapsulation assembly is tested using the second predefined test program under the second temperature of degree, wherein test first and the Two chip encapsulation assemblies occur simultaneously.

In the tenth example, the 9th example can also limit in the following manner：Wherein test the first chip package group Part includes the first chip encapsulation assembly of heating, and it includes cooling second chip package group wherein to test the second chip encapsulation assembly Part.

In the 11st example, the 9th example can also limit in the following manner：Wherein first predefined test journey Sequence is different from the second predefined test program.

In the 13rd example, the 9th example can limit in the following manner：Wherein the first predetermined temperature is different from Second predetermined temperature.

In the 14th example, the 9th example can be limited further in the following manner：Wherein transmit the first chip Package assembling includes that the first chip encapsulation assembly is arranged on the first socket with the first encapsulation receiving area；And wherein It includes that second chip encapsulation assembly is arranged in the second encapsulation receiving area to transmit second chip encapsulation assembly The second socket on, wherein it is described first encapsulation receiving area be more than it is described second encapsulate receiving area.

In the 15th example, the 9th example can also include：Using automatic identification and data capture (AIDC) obtain with The related information of third chip encapsulation assembly, and in response to by the AIDC equipment obtain about third chip encapsulation assembly Information third chip encapsulation assembly is transmitted to one in first or second test interface.

In the 16th example, the 9th example can also include：The is kept by the first end manipulation device of robot One chip encapsulation assembly, and the second chip encapsulation assembly is kept by the second manipulation device of robot.

In the 17th example, the 9th example can also include：Heat the first chip encapsulation assembly, and cooling second core Piece package assembling.

In the 18th example, the 9th example can also limit in the following manner：Wherein test the second chip package Component includes testing the first chip using the test program for being different from the test program for testing the second chip encapsulation assembly to seal Arrangement.

In the 19th example, the 9th example can also limit in the following manner：Wherein the first chip encapsulation assembly More than the second chip encapsulation assembly.

In the 20th example, the 9th example can also limit in the following manner：It is wherein predefined using second Test program come to test the second chip encapsulation assembly include testing the second chip encapsulation assembly at a temperature, the temperature with make The temperature that the first chip encapsulation assembly is tested with the first predefined test program is different.

Therefore, compared with conventional test system, there has been provided improve core of the test handling capacity without increasing space requirement Piece encapsulates assembling test system.The chip encapsulation assembly test system can be configured as while the test of test different types Chip encapsulation assembly.The chip encapsulation assembly test system can be additionally configured to carry out the chip encapsulation assembly tested Classification, more effectively to handle.Advantageously, the modularization of chip encapsulation assembly test system allows additional queue or survey Test stand provides additional flexibility, to meet continually changing production requirement, and with limited additional paid-in capital expenditure or when shutting down Between carry out system reconfigure.In addition, the chip encapsulation assembly test system can in the application for needing small tool to occupy Individual machine people and the workbench that is serviced by individual machine people are surrounded to be configured with, or is configured with linear arrangement so that Faster handling capacity can be obtained using greater number of workbench, be equal to the unit for reducing each chip encapsulation assembly Cost.

It, can be the case where not departing from the base region of the present invention although foregoing teachings are related to the embodiment of the present invention Other and the other embodiment of the lower design present invention, and the range is determined by appended claims.

Claims

1. a kind of modularization chip encapsulation assembly tests system, which is characterized in that including：

First queue platform is configured as receiving the first barrow, and first barrow includes in the modularization chip The multiple chip encapsulation assemblies tested in encapsulation component test system；

Second queue platform is configured as receiving the second barrow, and second barrow includes in the modularization chip The multiple chip encapsulation assemblies tested in encapsulation component test system；

Multiple testboards, include at least the first testboard and secondary test board, and each testboard includes：

First test interface is configured as receiving and being communicatively connected to a few chip encapsulation assembly；With

First test processor is configured with predefined test program and is connected by first test interface to test Chip encapsulation assembly；

Robot has a motion range, operable in the arbitrary first queue platform, the second queue platform and institute It states and transmits chip encapsulation assembly between multiple testboards；

Automatic identification and data capture AIDC devices, it is operable to identify that label, the identification label are adhered to setting to read On barrow in the first and second queues platform, or it is adhered to the chip encapsulation assembly being set in the test system On；With

Controller is configured to respond to be coupled to setting at least one of described first and second queues platform from reading Barrow on identification label, first testboard test processor predefined test program and it is described second survey The information obtained in the predefined test program of the test processor of test stand controls the chip envelope by the robot The placement of arrangement.

2. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that the AIDC devices coupling The robot is closed, and the AIDC devices include RFID reader or barcode reader.

3. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that the controller also by It is configured to：

The placement of tested chip encapsulation assembly is controlled based on the test result of tested chip encapsulation assembly, wherein institute First queue platform is stated to be additionally configured to receive third barrow；With

Based on the test result of tested chip encapsulation assembly, the chip encapsulation assembly tested is placed on described first and is removed It transports on frame or third barrow.

4. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that first testboard Test processor and the test processor of the secondary test board be configured with different predefined test programs.

5. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that first testboard Test processor be configured as at least one of operation DC test programs, aging procedure or final test program.

6. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that first testboard Further include：

Second test interface can be configured to receive and communicatedly connect the second chip encapsulation assembly；With

Second test processor is configured as the chip encapsulation assembly that test is connected by second test interface, wherein institute The first test interface is stated to can be configured to receive and communicatedly connect to have there are one the first chip encapsulation assembly of soldered ball connection arrangement, Wherein described second test interface can be configured to receive and communicatedly connect the second chip encapsulation assembly, second chip package Component relative to the first chip encapsulation assembly there is different soldered ball to connect arrangement, and wherein described first test processor and Second test processor is configured as running different test programs.

7. modularization chip encapsulation assembly according to claim 6 tests system, which is characterized in that further include：

There is temperature control unit heater and cooler, the temperature control unit to be configured as testing by described first First test interface is selectively maintained into the first temperature during the test program of processor operation, and by Second test interface is selectively maintained second during the test program of the second test processor operation Temperature, wherein the second temperature is different from first temperature.

8. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that first testboard Including：

Plunger, it is operable to selectively propel chip encapsulation assembly and the first test interface communication contact；With

Temperature control unit with heater and cooler, the temperature control unit are configured as described selectively One test interface is maintained at the first temperature during predefined first test program, and by first test interface It is maintained at the second temperature different from first temperature during predefined second test program, wherein the heating Device and cooler are coupled to the plunger.

9. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that the robot also wraps It includes：

First end manipulation device is configured as selectively keeping the first chip encapsulation assembly during transmission；With

The second end manipulation device is configured as selecting during the first end manipulation device keeps the first chip encapsulation assembly Keep to selecting property the second chip encapsulation assembly.

10. modularization chip encapsulation assembly according to claim 1 tests system, which is characterized in that including：

Temperature control unit with heater and cooler, the temperature control unit are configured as described predefined The first test interface of first testboard is selectively maintained into the first temperature during one test program, and described Selectively the first test interface of the secondary test board is maintained and described during predefined second test program The different second temperature of one temperature.