CN207542272U - Communication GaN base RF power amplification chip - Google Patents
Communication GaN base RF power amplification chip Download PDFInfo
- Publication number
- CN207542272U CN207542272U CN201721603377.1U CN201721603377U CN207542272U CN 207542272 U CN207542272 U CN 207542272U CN 201721603377 U CN201721603377 U CN 201721603377U CN 207542272 U CN207542272 U CN 207542272U
- Authority
- CN
- China
- Prior art keywords
- tube core
- package substrate
- dovetail groove
- coattail strip
- dovetail
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Led Device Packages (AREA)
Abstract
The utility model discloses communication GaN base RF power amplification chips, belong to LED chip technical field, chip includes the first die for setting gradually and being fixedly connected from top to bottom, second tube core and package substrate, package substrate upper surface below the second tube core is provided with boss, boss upper surface offers at least two dovetail grooves, all dovetail grooves are arranged in parallel, second tube core lower end is provided with coattail strip, the height of coattail strip is less than the depth of dovetail groove, second tube core is by the cooperation of coattail strip and dovetail groove and package substrate grafting, the side wall of coattail strip is contacted with dovetail groove, adhesive linkage is provided between coattail strip and the bottom surface of dovetail groove, at least two bonding wires are provided between two pads being connected between second tube core and package substrate.The second tube core can be prevented to be detached from package substrate, conductive effect is more preferable, even if some bonding wire goes wrong, will not influence the normal use of chip, can extend the service life of chip.
Description
Technical field
The utility model belongs to LED chip technical field, is related to communication GaN base RF power amplification chip.
Background technology
LED is a kind of semiconductor devices that can convert electrical energy into luminous energy, is referred to as forth generation light source, have it is energy saving,
Environmental protection, safety, long lifespan, low-power consumption, low-heat, high brightness, waterproof, miniature, shockproof, easy light modulation, light beam concentration, easy maintenance etc.
Feature can be widely applied to the fields such as various instructions, display, decoration, backlight, general lighting.Gallium nitride GaN belongs to third
For semi-conducting material, have that energy gap is big, thermal conductivity is high, high temperature resistant, radioresistance, acid and alkali-resistance, high intensity and high rigidity etc. are excellent
Point.GaN base RF power amplification chip includes the first die, the second tube core and the package substrate that set gradually from top to bottom, the first pipe
Core and the second die bond, the second tube core is Nian Jie with package substrate, and existing second tube core is adhered directly on package substrate, is not had
Other position limiting structures, if so bonding is insecure, the second tube core is easy to be detached from package substrate.In addition, on the second tube core
It is connected between pad on pad and package substrate by bonding wire, generally one is all only connected between connected two pads
Bonding wire once this bonding wire goes wrong, will influence the normal use of chip.
Invention content
The defects of the utility model is in order to overcome the prior art devises communication GaN base RF power amplification chip so that the
Connection between two tube cores and package substrate is more solid and reliable, and the second tube core can be prevented to be detached from package substrate, conductive effect
More preferably, and between two connected pads at least two bonding wires are connected with, even if some bonding wire goes wrong, also
There are other bonding wires can be used, do not interfere with the normal use of chip, the service life of chip can be extended.
The specific technical solution that the utility model is taken is：Communication GaN base RF power amplification chip, including from top to bottom
First die, the second tube core and the package substrate for setting gradually and being fixedly connected, the pad on the second tube core is by bonding wire
It is connect with the pad on package substrate, it is important to：Package substrate upper surface below the second tube core is provided with boss, boss
Upper surface offers at least two dovetail grooves, and all dovetail grooves are arranged in parallel, and the second tube core lower end is provided with coattail strip, dovetail
The height of item is less than the depth of dovetail groove, and the second tube core is by the cooperation of coattail strip and dovetail groove and package substrate grafting, dovetail
The side wall of item is contacted with dovetail groove, and adhesive linkage, the second tube core and package substrate are provided between coattail strip and the bottom surface of dovetail groove
Between be connected two pads between be provided at least two bonding wires.
Between the boss and package substrate, between coattail strip and the second tube core be all integral structure.
The length of the dovetail groove is less than length of the boss along dovetail groove length direction, the length and dovetail groove of coattail strip
Equal length.
The second tube core upper surface below first die is provided with solder joint, and first die lower face is corresponding with solder joint
Position be provided with conductive column, conductive column lower face opens up fluted, and filled with solder layer in groove, solder layer lower face is located at
The lower section of conductive column lower face.
The depth of groove is less than or equal to the half of conductive post height.
The chip further includes heat-shrink tube, all between two pads being connected between the second tube core and package substrate
Bonding wire is all located in same heat-shrink tube.
The beneficial effects of the utility model are：During inserting, first the coattail strip on the second tube core is inserted on package substrate
In dovetail groove, then coattail strip and dovetail groove bottom is made to be adhesively fixed using adhesive linkage, firm and reliable connection can prevent
Second tube core shakes, and the second tube core is effectively prevent to be detached from package substrate, and conductive effect is more preferable, and can extend chip uses the longevity
Life.At least two bonding wires are connected between two pads being connected between second tube core and package substrate, even if some key
It closes lead to go wrong, the normal use of chip will not be influenced, the service life of chip can be extended.
Description of the drawings
Fig. 1 is the structure diagram of the utility model.
In attached drawing, 1 represents first die, and 2 represent the second tube core, and 3 represent package substrate, and 4 represent coattail strip, and 5 representatives are led
Electric column, 6 represent solder layer, and 7 represent bonding wire, and 8 represent adhesive linkage, and 9 represent heat-shrink tube.
Specific embodiment
It elaborates in the following with reference to the drawings and specific embodiments to the utility model：
Specific embodiment, as shown in Figure 1, communication GaN base RF power amplification chip, including setting gradually from top to bottom and admittedly
Surely first die 1, the second tube core 2 and the package substrate 3 connected, the pad on the second tube core 2 is by bonding wire 7 and encapsulation base
Pad connection on plate 3 is provided with boss positioned at 3 upper surface of package substrate of 2 lower section of the second tube core, and boss upper surface offers
At least two dovetail grooves, all dovetail grooves are arranged in parallel, and 2 lower end of the second tube core is provided with coattail strip 4, the height of coattail strip 4
Less than the depth of dovetail groove, the second tube core 2 by the cooperation of coattail strip 4 and dovetail groove and 3 grafting of package substrate, coattail strip 4
Side wall is contacted with dovetail groove, and adhesive linkage 8, the second tube core 2 and package substrate 3 are provided between coattail strip 4 and the bottom surface of dovetail groove
Between be connected two pads between be provided at least two bonding wires 7.
During inserting, first the coattail strip 4 on the second tube core 2 is inserted into the dovetail groove on package substrate 3, then utilizes bonding
Layer 8 makes coattail strip 4 and dovetail groove bottom be adhesively fixed, and firm and reliable connection can prevent the second tube core 2 from shaking, effectively
The second tube core 2 is prevented to be detached from package substrate 3, conductive effect is more preferable, can extend the service life of chip.Second tube core 2 and envelope
At least two bonding wires 7 are connected between two pads being connected between dress substrate 3, even if some bonding wire 7 is asked
Topic, also other bonding wires 7 can be used, not interfere with the normal use of chip, can also extend the service life of chip.
As to further improvement of the utility model, between boss and package substrate 3,4 and second tube core 2 of coattail strip it
Between be all integral structure, be integrally formed, manufacturing process is simpler, connection it is more solid and reliable, can prevent junction from breaking
It splits.
It is less than length of the boss along dovetail groove length direction as the length to further improvement of the utility model, dovetail groove
Degree, the length of coattail strip 4 and the equal length of dovetail groove.Dovetail groove is not a straight slot, and during grafting, coattail strip 4 is inserted into dovetail
It can not just be continued to move to behind slot end, can confirm the grafting of coattail strip 4 in time in place, stopped grafting, do not need to again
It is special to go to see whether grafting in place, the position of setting is inserted through without worry, can improve production efficiency coattail strip 4,
And it may insure the consistency of the second position on package substrate 3 of tube core 2 of each chip, more neat appearance.
As to further improvement of the utility model, it is provided with positioned at 2 upper surface of the second tube core of 1 lower section of first die
Solder joint, 1 lower face of first die and the corresponding position of solder joint are provided with conductive column 5,5 lower face of conductive column open up it is fluted,
Filled with solder layer 6 in groove, 6 lower face of solder layer is located at the lower section of 5 lower face of conductive column.Solder layer 6 is arranged on conduction
In the groove of 5 bottom of column, solder layer 6 is not in direct contact with first die 1, during welding, can reduce the high temperature pair on solder layer 6
The influence that first die 1 generates.The setting of groove can increase the contact area of solder layer 6 and conductive column 5 so that the first pipe
Connection between 1 and second tube core 2 of core is more solid and reliable.
As to further improvement of the utility model, the depth of groove is less than or equal to the half of 5 height of conductive column, it is ensured that
Conductive column 5 has sufficiently large intensity, makes the connection between 1 and second tube core 2 of first die more solid and reliable.
As to further improvement of the utility model, chip further includes heat-shrink tube 9, the second tube core 2 and package substrate 3 it
Between all bonding wires 7 between two pads being connected be all located in same heat-shrink tube 9, make chip whole more neat,
Whether the bonding wire 7 convenient for distinguishing adjacent is connected on same pad, and heat-shrink tube 9 has high-temperature shrinkage, soft resistance
Combustion and the function of insulation corrosion protection, can play the role of insulation protection, more securely and reliably.
Claims (5)
1. communication is with GaN base RF power amplification chip, including set gradually and be fixedly connected from top to bottom first die (1), the
Two tube cores (2) and package substrate (3), the pad on the second tube core (2) is by the weldering on bonding wire (7) and package substrate (3)
Disk connects, it is characterised in that：Package substrate (3) upper surface below the second tube core (2) is provided with boss, boss upper surface
At least two dovetail grooves are offered, all dovetail grooves are arranged in parallel, and the second tube core (2) lower end is provided with coattail strip (4), dovetail
The height of item (4) is less than the depth of dovetail groove, and the second tube core (2) is by coattail strip (4) and cooperation and the package substrate of dovetail groove
(3) grafting, the side wall of coattail strip (4) are contacted with dovetail groove, and coattail strip (4) is provided with adhesive linkage between the bottom surface of dovetail groove
(8), at least two bonding wires (7) are provided between two pads being connected between the second tube core (2) and package substrate (3)；
The chip further includes heat-shrink tube (9), between two pads being connected between the second tube core (2) and package substrate (3)
All bonding wires (7) be all located in same heat-shrink tube (9).
2. communication GaN base RF power amplification chip according to claim 1, it is characterised in that：The boss and encapsulation
Between substrate (3), between coattail strip (4) and the second tube core (2) be all integral structure.
3. communication GaN base RF power amplification chip according to claim 1, it is characterised in that：The length of the dovetail groove
Degree is less than length of the boss along dovetail groove length direction, the length of coattail strip (4) and the equal length of dovetail groove.
4. communication GaN base RF power amplification chip according to claim 1, it is characterised in that：Under first die (1)
The second tube core (2) upper surface of side is provided with solder joint, and first die (1) lower face is provided with conduction with the corresponding position of solder joint
Column (5), conductive column (5) lower face open up fluted, are located at conduction filled with solder layer (6), solder layer (6) lower face in groove
The lower section of column (5) lower face.
5. communication GaN base RF power amplification chip according to claim 1, it is characterised in that：The depth of groove be less than etc.
In the half of conductive column (5) height.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721603377.1U CN207542272U (en) | 2017-11-27 | 2017-11-27 | Communication GaN base RF power amplification chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721603377.1U CN207542272U (en) | 2017-11-27 | 2017-11-27 | Communication GaN base RF power amplification chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207542272U true CN207542272U (en) | 2018-06-26 |
Family
ID=62615310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721603377.1U Expired - Fee Related CN207542272U (en) | 2017-11-27 | 2017-11-27 | Communication GaN base RF power amplification chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207542272U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113169074A (en) * | 2018-09-11 | 2021-07-23 | Rjr技术公司 | Air cavity package with improved connection between components |
-
2017
- 2017-11-27 CN CN201721603377.1U patent/CN207542272U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113169074A (en) * | 2018-09-11 | 2021-07-23 | Rjr技术公司 | Air cavity package with improved connection between components |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180626 Termination date: 20201127 |