CN207381402U - The encapsulating structure of image chip - Google Patents
The encapsulating structure of image chip Download PDFInfo
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- CN207381402U CN207381402U CN201721183906.7U CN201721183906U CN207381402U CN 207381402 U CN207381402 U CN 207381402U CN 201721183906 U CN201721183906 U CN 201721183906U CN 207381402 U CN207381402 U CN 207381402U
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- circuit substrate
- chip
- image
- image sensing
- encapsulating structure
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Abstract
The utility model is related to a kind of encapsulating structures of image chip, it is provided with circuit substrate, multiple image sensing chips and packaging body, multiple hollow-out parts through surface and bottom surface are arranged at intervals in circuit substrate, the surface of image sensing chip is with solder connection in the bottom surface of circuit substrate, image sensing chip is made to be electrically connected with circuit substrate, and the sensing region of each image sensing chip is right against each hollow-out parts of circuit substrate respectively, and packaging body is filled in the bottom surface of circuit substrate with insulating cement, image sensing chip is coated in packaging body, multiple image sensing chips are disposably encapsulated using circuit substrate, effectively improve precision and optical property, and cost can be greatly reduced and facilitate image chip systematization.
Description
Technical field
The utility model is related to a kind of encapsulating structures of image chip.
Background technology
Current image chip encapsulating structure includes a circuit board and image chip, and image chip utilizes Flip Chip
(flip-chip) it is installed on circuit board surface, then optical filter is packaged on circuit board and compared with image chip, however
Circuit board is more soft and is easily deformed, and when encapsulating manufacture, is easy to cause circuit board deformation and damage, therefore has this field
Related technical personnel encapsulate image chip and optical filter with soft or hard combined type circuit board, and such practice has following defects：
1st, image chip is packaged to be single, can not break through the encapsulation design principle of traditional die and the reproduction of size
Property, and dustless grade, humidity and electrostatic for dust free room etc. has high requirement so that encapsulation yield and precision are subject to skill
Art is limited, and cost is more caused not reduce effectively.
2nd, image chip and optical filter are all arranged at circuit board homonymy, and because image chip is not chip supplied materials and flip
The limitation of technique causes whole encapsulating structure that can not be miniaturized, i.e., thickness can not reduce.
Utility model content
The main purpose of the utility model is that disposably encapsulating multiple image sensing chips using circuit substrate, have
Effect ground improves precision and optical property, and cost can be greatly reduced and facilitate image chip systematization.
In order to achieve the above object, the utility model is provided with rigid circuit substrate, multiple image sensing chips and packaging body,
Circuit substrate has surface and the bottom surface compared with surface, and is arranged at intervals in circuit substrate multiple to accommodating optical filter
Hollow-out parts, each hollow-out parts are through the surface and bottom surface of circuit substrate；Image sensing chip has surface and bottom surface, surface
Sensing region is provided with, each image sensing chip is located at the bottom surface of circuit substrate, and the surface of image sensing chip is connected with solder
The bottom surface of circuit substrate is connected to, and passing through solder makes image sensing chip be electrically connected with circuit substrate, and each image sense
The sensing region for surveying chip is right against each hollow-out parts of circuit substrate；Packaging body is filled in the bottom surface of circuit substrate with insulating cement,
Image sensing chip is coated in packaging body.
The bottom surface of the encapsulating structure of foregoing image chip, the wherein image sensing chip is provided with electronic component, electronics member
Part is coated in packaging body, and electronic component is electrically connected at circuit substrate.
The bottom surface of the encapsulating structure of foregoing image chip, the wherein image sensing chip is provided with circuit board, on circuit board
Multiple electronic components are provided with, electronic component is electrically connected by circuit board and circuit substrate.
The encapsulating structure of foregoing image chip, the wherein electronic component are microprocessor or memory.
The encapsulating structure of foregoing image chip, the wherein circuit substrate are multi-layered circuits substrate.
Description of the drawings
Fig. 1 is the outside drawing of the utility model circuit substrate.
Fig. 2 is the sectional view of the utility model circuit substrate.
Fig. 3 is the sectional view that the utility model circuit substrate connects image sensing chip.
Fig. 4 is that the utility model packaging body encapsulates the sectional view after image sensing chip.
Fig. 5 is the sectional view that optical filter is arranged at circuit substrate by the utility model.
Fig. 6 is the sectional view that single image chip packaging body is formed after the utility model is cut.
Fig. 7 is the sectional view of formation image chip group packaging body after the utility model cutting.
Fig. 8 is the schematic diagram that the utility model is ground after packaging.
Fig. 9 is the sectional view after the utility model grinding.
Figure 10 is the sectional view (one) of another packaged type of the utility model.
Figure 11 is the sectional view (two) of another packaged type of the utility model.
Figure 12 is the sectional view (three) of another packaged type of the utility model.
Figure 13 is the sectional view (one) of the another packaged type of the utility model.
Figure 14 is the sectional view (two) of the another packaged type of the utility model.
Figure 15 is the outside drawing of image sensing chip.
Reference sign
1 circuit substrate
11 surfaces
12 bottom surfaces
13 hollow-out parts
Weld pad on 14
15 times weld pads
2 image sensing chips
21 surfaces
211 sensing regions
212 weld pads
22 bottom surfaces
3 packaging bodies
4 optical filters
5 solders
6 electronic components
7 circuit boards.
Specific embodiment
It please refers to Fig.1 to shown in Fig. 7, it can be clearly seen from the figure that, the utility model includes circuit substrate 1, Duo Geying
As sensor chip 2 and packaging body 3, wherein：
The circuit substrate 1 is rigid multilayer circuit board, has surface 11 and the bottom surface 12 compared with surface 11, and in electricity
Multiple hollow-out parts 13 are arranged at intervals on base board 1, the surface 11 of circuit substrate 1, which is provided in 13 periphery of hollow-out parts on multiple, welds
Pad 14, the bottom surface 12 of circuit substrate 1 are provided with multiple lower weld pads 15 in 13 periphery of hollow-out parts, and each hollow-out parts 13 are through circuit base
The surface 11 of plate 1 and bottom surface 12, and optical filter 4 is provided in hollow-out parts 13.
The image sensing chip 2 has surface 21 and bottom surface 22, and surface 21 is provided with sensing region 211, image sensing
The surface 21 of chip 2 is provided with multiple weld pads 212 in 211 periphery of sensing region.
When the utility model is implemented, the surface 21 of image sensing chip 2 is connected to the bottom of circuit substrate 1 with solder 5
Face 12, and passing through solder 5 makes the weld pad 212 of image sensing chip 2 be electrically connected with the lower weld pad 15 of circuit substrate 1, and
The sensing region 211 of each image sensing chip 2 is made to be right against each hollow-out parts 13 of circuit substrate 1 respectively；It is continuous to be filled with insulating cement
Packaging body 3 is formed in the bottom surface of circuit substrate 1 12, and image sensing chip 2 is made to be coated in packaging body 3, then by circuit substrate 1
(such as Fig. 6 and Fig. 7) is cut, forms circuit substrate 1, image sensing chip 2 and packaging body 3 single or in groups (double-colored)
Image chip.Furthermore optical filter 4 can be set before packaging body 3 is packaged or after encapsulation, had no effect on encapsulation and carried out.
Due to using single circuit substrate 1 simultaneously encapsulate multiple image sensing chips 2, can effectively simplify processing procedure and
Manufacture cost is reduced, and can realize the management of big data, and packaging body 3 is when encapsulating image sensing chip 2, positioned at image sensing
Another side of the chip 2 away from sensing region 211, and sensing region 211 can effectively be prevented to be contaminated.Furthermore pass through circuit base
Plate 1 houses optical filter 4, can more reduce integral thickness, is conducive to electronic product slimming.
It refers to shown in Fig. 8 and Fig. 9, it can be clearly seen from the figure that, it is multiple due to being encapsulated simultaneously using single circuit substrate 1
Image sensing chip 2, therefore easily positioned, it, can be first to packaging body 3 and image sense before being cut circuit substrate 1
It surveys chip 2 and is ground the thickness for reducing entirety, cut again after the completion of to be ground, more reduce integral thickness.
It please refers to Fig.1 shown in 0 to Figure 12, it can be clearly seen from the figure that, the utility model is in packaging body 3 to image sensing core
Before piece 2 is packaged, first the bottom surface 22 of image sensing chip 2 is ground, to reduce the thickness of image sensing chip 2, then
Electronic component 6 is set in the bottom surface of image sensing chip 2 22, electronic component 6 is electrically connected in a manner of routing under circuit substrate 1
Weld pad 15 is coated on when packaging body 3 encapsulates in packaging body 3 together, and electronic component 6 can be microprocessor, memory or dissipate
Hot body, and then be conducive to image chip systematization.
It please refers to Fig.1 shown in 3 and Figure 14, it can be clearly seen from the figure that, the utility model is in the bottom surface of image sensing chip 2
22 are provided with circuit board 7, and multiple electronic components 6 are provided on circuit board 7, and electronic component 6 can weld or routing
Mode is electrically connected at circuit board 7, and lower weld pad 15 of the circuit board 7 again with circuit substrate 1 in a manner of routing is electrically connected, together
Sample is conducive to image chip systematization.
It please refers to Fig.1 shown in 4 and Figure 15, it can be clearly seen from the figure that, the surface 21 of the utility model image sensing chip 2
Set weld pad 212, is the lower weld pad 15 for being electrically connected circuit substrate 1 with welding manner using solder 5, therefore image sensing
The weld pad 212 of chip 2 can significantly reduce, and image chip manufactory is made to realize that weld pad 212 is contracted to 50um2~10um2 even more
Small, after significantly 212 size of weld pad is reduced, 2 quantum of output of image sensing chip of the single-wafer of chip factory can also obtain greatly
Amplitude improves, and reduces image chip cost, while but also image package body sizes surmount the ruler that existing encapsulation can not reach
Very little diminution.
Claims (8)
1. a kind of encapsulating structure of image chip, which is characterized in that it includes have：
Rigid circuit substrate (1), the bottom surface (12) with surface (11) and compared with surface (11), and circuit substrate
(1) it is arranged at intervals with multiple to house the hollow-out parts (13) of optical filter (4) on, each hollow-out parts (13) are through circuit substrate
(1) surface (11) and bottom surface (12)；
Multiple image sensing chips (2), the image sensing chip (2) have surface (21) and bottom surface (22), surface (21)
Sensing region (211) is provided with, each image sensing chip (2) is located at the bottom surface (12) of circuit substrate (1), and image sensing chip
(2) surface (21) is connected to the bottom surface (12) of circuit substrate (1) with solder (5), and passes through solder (5) and make image sensing chip
(2) it is electrically connected with circuit substrate (1), and the sensing region (211) of each image sensing chip (2) is right against circuit substrate
(1) each hollow-out parts (13)；
Packaging body (3), the bottom surface (12) of circuit substrate (1) is filled in insulating cement, and image sensing chip (2) is coated on envelope
It fills in body (3).
2. the encapsulating structure of image chip according to claim 1, which is characterized in that the wherein image sensing chip (2)
Bottom surface (22) be provided with electronic component (6), electronic component (6) is coated in packaging body (3), and electronic component (6) electrically connects
It is connected to circuit substrate (1).
3. the encapsulating structure of image chip according to claim 2, which is characterized in that wherein the electronic component (6) is micro-
Processor.
4. the encapsulating structure of image chip according to claim 2, which is characterized in that wherein the electronic component (6) is to deposit
Reservoir.
5. the encapsulating structure of image chip according to claim 1, which is characterized in that the wherein image sensing chip (2)
Bottom surface (22) be provided with circuit board (7), multiple electronic components (6) are provided on circuit board (7), electronic component (6) passes through electricity
Road plate (7) is electrically connected with circuit substrate (1).
6. the encapsulating structure of image chip according to claim 5, which is characterized in that wherein the electronic component (6) is micro-
Processor.
7. the encapsulating structure of image chip according to claim 5, which is characterized in that wherein the electronic component (6) is to deposit
Reservoir.
8. the encapsulating structure of image chip according to claim 1, which is characterized in that wherein the circuit substrate (1) is more
Laminar circuit substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721183906.7U CN207381402U (en) | 2017-09-15 | 2017-09-15 | The encapsulating structure of image chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721183906.7U CN207381402U (en) | 2017-09-15 | 2017-09-15 | The encapsulating structure of image chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207381402U true CN207381402U (en) | 2018-05-18 |
Family
ID=62339991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721183906.7U Active CN207381402U (en) | 2017-09-15 | 2017-09-15 | The encapsulating structure of image chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207381402U (en) |
-
2017
- 2017-09-15 CN CN201721183906.7U patent/CN207381402U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190506 Address after: Hongkong, China Patentee after: Dazhi Optical Technology Co., Ltd. Address before: Hsinchu County, Taiwan, China Co-patentee before: Ningbo Dali light Mdt InfoTech Ltd Patentee before: Dali light Polytron Technologies Inc |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200628 Address after: 22 / F, block a, Zhihui center, 1190 Bin'an Road, Changhe street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: SUNNY OPTICAL (ZHEJIANG) RESEARCH INSTITUTE Co.,Ltd. Address before: Hong Kong Patentee before: Dazhi Optical Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right |